JPS60121755A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60121755A
JPS60121755A JP58229708A JP22970883A JPS60121755A JP S60121755 A JPS60121755 A JP S60121755A JP 58229708 A JP58229708 A JP 58229708A JP 22970883 A JP22970883 A JP 22970883A JP S60121755 A JPS60121755 A JP S60121755A
Authority
JP
Japan
Prior art keywords
pellet
semiconductor
lead
electrodes
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58229708A
Other languages
English (en)
Inventor
Kiichi Futai
二井　喜一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58229708A priority Critical patent/JPS60121755A/ja
Publication of JPS60121755A publication Critical patent/JPS60121755A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。
〔発明の技術的背景〕
従来、例えばＧａＡｓ　Ｄｕａｌ　Ｇａｔｅイオン注入
型ＦＩＴからなる半導体装置は、第１図（４）及び同図
（Ｂ）に示す如く、半導体ベレッ）Ｚの主面に４個の取
出電極２・・・２を形成し、この取出電＆２・・・２と
リードｗＬ極３・・３とをリード線４・・・４で接続し
、リード電極３・・・３の一部分が外部に導出するよう
にしてこれらを樹脂封止体５で一体に封止した構造を有
している。
〔背景技術の問題点〕
このように構成された半導体装置互では、半導体ベレッ
トＩの主面に大きな占有面積を必要とする取出電極２・
・・２を４個形成するため、半導体ペレットＩが大型に
なる。その結果、製造コストが高くなる問題があった。
〔発明の目的〕
本発明は、半導体ペレットの小型化を図って製造コスト
の低減を達成した半導体装置を提供することをその目的
とするものである。
〔発明の概要」 本発明は、取出電極を半導体ベレットの主面及び側面に
分散して設けるようにしたことにより、半導体ペレット
を小型にして製造コストの低減を達成した半導体装置で
ある。
〔発明の実施例〕
以下、本発明の英施−例について図面を参照して説明す
る。
第２図（Ａ）は、本発明の一実施例の平面図、同図（Ｂ
）Ｆｉ、同実施例の側部を示す断面図である。
図中１０は、ＧａＡｓ　Ｄｕａｌ　Ｇａｔｅイオン注入
型ＦＩＴからなる半導体ベレットである。半導体ベレッ
ト１０は、リードフレームのベレットｉウント部に装着
されている。半導体ベレット１ｏには、その主面から側
面にかけて４個の取出電極ＩＩ・・・ＩＩが折曲して形
成されている。側面・に露出した取出電極ＩＺ・・ＩＩ
の部分には、リード線１２・・１２の一端部が接続され
ている。リード線１２・・１２の他端部は、ベレットマ
ウント部の周囲に配！されたリード電極１３・・・Ｉ３
に接続されている。半導体ベレット１ｏ、ペレツトマウ
ント部、リード線１２・・・Ｉ２及びリード電極Ｉ３・
・・１３は、リード電極Ｉ３・・・１３の端部を外部に
露出するようにして樹脂封止体Ｚ４で一体に封止されて
いる。
このように構成された半導体装置２ｏによれば、取出電
極ＩＩ・・・ＩＩが半導体ペレットｌ。
の主面から側面にかけて形成されているので、主面の面
積を小さくして半導体ベレット１０を小型にすることが
できる。その結果、リード線１２・・・１２を半導体ベ
レットＩＯから多数本導出する場合であっても、半導体
装置二を小型にして製造コストを低減させることができ
る。
なお、実施例では、取出電極１１・・・Ｚｌを半導体ベ
レット１０の主面から側面にかけて形成するものについ
て説明したが、１乃至２個の半導体ベレットＩＯを大型
にしない程度の数だけを主面に形成し、残フの取出電極
ＩＩ・・・ＩＩを側面に形成するようにしても良い。
〔発明の効果〕
以上説明した如く、本発明に係る半導体装置によれば、
半導体ベレットの小型化を図って製造コストの低減を達
成することができるものである。
【図面の簡単な説明】
第１図（４）は、従来の半導体装置の平面図、同図（Ｂ
）は、同半導体装置の側部を示す断面図、第２図（４）
は、本発明の一実施例の平面図、同図（Ｂ）は、同実施
例の側部を示す断面図である。 １０・・・半導体ベレット、１１・・・取出電極、１２
・・・リード線、１３・・・リード電極、１４・・・樹
脂封止体、２０−＝・半導体装置。 出願人代理人　弁理士　鈴　江　武　彦彫１　図 （Ａ） 第２　図 （Ａ）

Claims (1)

    【特許請求の範囲】
  1. 半導体ベレットの主面に少なくとも複数個の取出電極を
    設けた半導体装置において、取出電極を半導体ペレット
    の主面及び側面に分散して設けたことを特徴とする半導
    体装置。
JP58229708A 1983-12-05 1983-12-05 半導体装置 Pending JPS60121755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58229708A JPS60121755A (ja) 1983-12-05 1983-12-05 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58229708A JPS60121755A (ja) 1983-12-05 1983-12-05 半導体装置

Publications (1)

Publication Number Publication Date
JPS60121755A true JPS60121755A (ja) 1985-06-29

Family

ID=16896451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58229708A Pending JPS60121755A (ja) 1983-12-05 1983-12-05 半導体装置

Country Status (1)

Country Link
JP (1) JPS60121755A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118164A (ja) * 1984-07-04 1986-01-27 Mitsubishi Electric Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118164A (ja) * 1984-07-04 1986-01-27 Mitsubishi Electric Corp 半導体装置

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