JPH065593A - 多層配線基板及びその製造方法 - Google Patents
多層配線基板及びその製造方法Info
- Publication number
- JPH065593A JPH065593A JP1751793A JP1751793A JPH065593A JP H065593 A JPH065593 A JP H065593A JP 1751793 A JP1751793 A JP 1751793A JP 1751793 A JP1751793 A JP 1751793A JP H065593 A JPH065593 A JP H065593A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring layer
- layer
- insulating layer
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09018—Rigid curved substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09681—Mesh conductors, e.g. as a ground plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31678—Of metal
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1751793A JPH065593A (ja) | 1992-04-20 | 1993-02-04 | 多層配線基板及びその製造方法 |
| EP19940103803 EP0605399A3 (en) | 1992-04-20 | 1993-04-16 | Multi-layer circuit board and manufacturing process. |
| DE69300615T DE69300615T2 (de) | 1992-04-20 | 1993-04-16 | Mehrschichtige Leiterplatte und Herstellungsverfahren. |
| EP19930106238 EP0567016B1 (en) | 1992-04-20 | 1993-04-16 | Multi layered wiring board and method for manufacturing the same |
| US08/047,492 US5348792A (en) | 1992-04-20 | 1993-04-19 | Multilayered wiring board with wiring configurations to reduce crosstalk |
| US08/092,883 US5353499A (en) | 1992-04-20 | 1993-07-19 | Method of manufacturing a multilayered wiring board |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9957992 | 1992-04-20 | ||
| JP9942792 | 1992-04-20 | ||
| JP4-99427 | 1992-04-20 | ||
| JP4-99579 | 1992-04-20 | ||
| JP1751793A JPH065593A (ja) | 1992-04-20 | 1993-02-04 | 多層配線基板及びその製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH065593A true JPH065593A (ja) | 1994-01-14 |
Family
ID=27281864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1751793A Pending JPH065593A (ja) | 1992-04-20 | 1993-02-04 | 多層配線基板及びその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US5348792A (enExample) |
| EP (2) | EP0567016B1 (enExample) |
| JP (1) | JPH065593A (enExample) |
| DE (1) | DE69300615T2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016100600A (ja) * | 2014-11-26 | 2016-05-30 | インテル コーポレイション | 電子パッケージ用の電気インターコネクト |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06291216A (ja) * | 1993-04-05 | 1994-10-18 | Sony Corp | 基板及びセラミックパッケージ |
| DE4318463C3 (de) * | 1993-06-03 | 2001-06-21 | Schulz Harder Juergen | Verfahren zum Herstellen eines Metall-Keramik-Substrates |
| JP3389357B2 (ja) * | 1994-11-29 | 2003-03-24 | 新光電気工業株式会社 | 半導体チップ搭載用基板 |
| US5619018A (en) * | 1995-04-03 | 1997-04-08 | Compaq Computer Corporation | Low weight multilayer printed circuit board |
| KR100485628B1 (ko) | 1996-01-11 | 2005-09-14 | 이비덴 가부시키가이샤 | 프린트배선판및그의제조방법 |
| EP0940849A1 (en) * | 1998-03-05 | 1999-09-08 | Interuniversitair Micro-Elektronica Centrum Vzw | A low-loss conductive pattern on a substrate and a method for fabrication thereof |
| JP3307597B2 (ja) * | 1998-09-30 | 2002-07-24 | 株式会社 アドテック | 印刷配線装置 |
| DE19921867C2 (de) * | 1999-05-11 | 2001-08-30 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterbauelements mit mindestens einem verkapselten Chip auf einem Substrat |
| US7061094B2 (en) * | 2004-01-19 | 2006-06-13 | Matsushita Electric Industrial Co., Ltd. | Multilayer printed circuit board including first and second signal traces and a first ground trace |
| JP2006100699A (ja) * | 2004-09-30 | 2006-04-13 | Toshiba Corp | プリント配線板、情報処理装置、及びプリント配線板の製造方法 |
| US7292454B2 (en) * | 2004-12-03 | 2007-11-06 | Dell Products L.P. | System and method for optimizing printed circuit boards to minimize effects of non-uniform dielectric |
| US8797150B2 (en) * | 2006-08-31 | 2014-08-05 | Asoka Usa Corporation | Method and system for power line networking for industrial process control applications |
| CN101207968B (zh) * | 2006-12-22 | 2011-11-09 | 鸿富锦精密工业(深圳)有限公司 | 电路板 |
| JP5589595B2 (ja) * | 2010-06-21 | 2014-09-17 | 富士通株式会社 | 配線基板及びその製造方法 |
| JP2013093345A (ja) * | 2011-10-24 | 2013-05-16 | Hitachi Ltd | 光モジュールおよび多層基板 |
| KR102446889B1 (ko) * | 2015-12-28 | 2022-09-26 | 삼성디스플레이 주식회사 | 플렉서블 기판 및 이를 포함하는 플렉서블 표시 장치 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3466206A (en) * | 1962-06-01 | 1969-09-09 | Control Data Corp | Method of making embedded printed circuits |
| US3546775A (en) * | 1965-10-22 | 1970-12-15 | Sanders Associates Inc | Method of making multi-layer circuit |
| JPS5317970A (en) * | 1976-08-04 | 1978-02-18 | Fujitsu Ltd | Copper stacking board |
| JPS5987895A (ja) * | 1982-11-10 | 1984-05-21 | 富士通株式会社 | 多層プリント基板 |
| JPS61188946A (ja) * | 1985-02-18 | 1986-08-22 | Toshiba Corp | 多層配線半導体集積回路 |
| US4801489A (en) * | 1986-03-13 | 1989-01-31 | Nintendo Co., Ltd. | Printed circuit board capable of preventing electromagnetic interference |
| JPH0716094B2 (ja) * | 1986-03-31 | 1995-02-22 | 日立化成工業株式会社 | 配線板の製造法 |
| US4907127A (en) * | 1988-03-21 | 1990-03-06 | Lee John K C | Printed circuit board construction and method for producing printed circuit end products |
| JPH01276453A (ja) * | 1988-04-27 | 1989-11-07 | Ricoh Co Ltd | 光磁気記録媒体 |
| JPH0251255A (ja) * | 1988-08-13 | 1990-02-21 | Fuji Xerox Co Ltd | 金属多層配線構造 |
| US5219607A (en) * | 1988-11-29 | 1993-06-15 | Nippon Cmk Corp. | Method of manufacturing printed circuit board |
| GB2233157B (en) * | 1989-06-13 | 1992-10-21 | British Aerospace | Printed circuit board |
| JPH03158002A (ja) * | 1989-11-15 | 1991-07-08 | Nec Corp | 半導体装置 |
| JPH03257992A (ja) * | 1990-03-08 | 1991-11-18 | Mitsubishi Electric Corp | 曲面形多層プリント配線板の製造方法 |
| JP2688446B2 (ja) * | 1990-03-26 | 1997-12-10 | 株式会社日立製作所 | 多層配線基板およびその製造方法 |
-
1993
- 1993-02-04 JP JP1751793A patent/JPH065593A/ja active Pending
- 1993-04-16 DE DE69300615T patent/DE69300615T2/de not_active Expired - Fee Related
- 1993-04-16 EP EP19930106238 patent/EP0567016B1/en not_active Expired - Lifetime
- 1993-04-16 EP EP19940103803 patent/EP0605399A3/en not_active Withdrawn
- 1993-04-19 US US08/047,492 patent/US5348792A/en not_active Expired - Fee Related
- 1993-07-19 US US08/092,883 patent/US5353499A/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016100600A (ja) * | 2014-11-26 | 2016-05-30 | インテル コーポレイション | 電子パッケージ用の電気インターコネクト |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0567016B1 (en) | 1995-10-11 |
| US5353499A (en) | 1994-10-11 |
| DE69300615D1 (de) | 1995-11-16 |
| US5348792A (en) | 1994-09-20 |
| DE69300615T2 (de) | 1996-07-25 |
| EP0567016A3 (enExample) | 1994-03-23 |
| EP0605399A3 (en) | 1995-04-19 |
| EP0567016A2 (en) | 1993-10-27 |
| EP0605399A2 (en) | 1994-07-06 |
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