JPH0135495B2 - - Google Patents

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Publication number
JPH0135495B2
JPH0135495B2 JP54154003A JP15400379A JPH0135495B2 JP H0135495 B2 JPH0135495 B2 JP H0135495B2 JP 54154003 A JP54154003 A JP 54154003A JP 15400379 A JP15400379 A JP 15400379A JP H0135495 B2 JPH0135495 B2 JP H0135495B2
Authority
JP
Japan
Prior art keywords
film
etching
etched
pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54154003A
Other languages
English (en)
Other versions
JPS5690525A (en
Inventor
Kenji Sugishima
Chuichi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=15574782&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH0135495(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15400379A priority Critical patent/JPS5690525A/ja
Priority to US06208391 priority patent/US4352724B1/en
Priority to EP80304232A priority patent/EP0030116B2/en
Priority to DE8080304232T priority patent/DE3072013D1/de
Priority to IE2457/80A priority patent/IE52972B1/en
Priority to CA000365656A priority patent/CA1155973A/en
Publication of JPS5690525A publication Critical patent/JPS5690525A/ja
Publication of JPH0135495B2 publication Critical patent/JPH0135495B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は、半導体装置の製造方法に係り、特に
基板上に形成した絶縁膜に電極窓及びビア・ホー
ルを形成する方法に関するものである。
最近半導体装置の微細化の研究が進められてい
る。その微細化の一つに、基板上の絶縁膜に形成
する電極窓及びビア・ホールの微細化がある。
一般のウエツト・エツチングやバレル型プラズ
マ・エツチヤーによる等方性エツチングにより電
極窓及びビア・ホール（以後ビア・ホールについ
て説明する）を形成すると、サイドエツチングの
発生により、第１図に示すようにエツチングマス
クとなる薄膜５のパターンに対して、絶縁膜４に
形成されるビア・ホール６の形状が大きくなる。
なお１は半導体基板でその上に絶縁膜（例えば
SiO2）２を介して例えばAlよりなる配線パター
ン３が形成されている。これでは精度良く微細な
ビア・ホール６を形成することができない。そこ
でサイドエツチングのない方法として知られてい
るプレーナ型プラズマ・エツチヤーを用いる。こ
の方法によれば、一方の電極の上に基板１を配置
してプラズマ・エツチングを行なうため、エツチ
ングの方向が基板表面に対して垂直方向になる。
これは一種の異方性エツチングである。このため
この方法によれば第２図に示すように絶縁膜４が
基板１の表面に対し垂直にエツチングされ、薄膜
５のパターンと同形のビア・ホール６を形成でき
る。しかし次の工程で薄膜５を除去した後、配線
パターン（例えばAl７を被着すると、ビア・ホ
ール６の形状が鋭いため、第２図中の８に示すよ
うに配線パターン７の膜厚が薄くなつたり断線し
たりして不良の原因となる。
本発明は上記従来の欠点を除去し、半導体装置
の基板表面に形成された絶縁膜に微細な電極窓及
びビア・ホールを精度良く形成し、しかも電極窓
及びビア・ホールの形状にテーパーを持たせるエ
ツチングの方法を提供するものである。
この目的は本発明によれば、基板上に形成した
被エツチング被膜上に所定の薄膜パターンを形成
する工程、 該薄膜パターンをマスクにして該被エツチング
被膜に、途中まで等方性エツチングを施こし続い
て膜厚方向への異方性エツチングを施こして、テ
ーパー形状の側面をもつた該被エツチング被膜の
パターンを形成する工程を有することを特徴とす
る半導体装置の製造方法を提供することにより達
成され、さらには前記の等方性エツチングをバレ
ル型プラズマ・エツチヤーにより行ない、異方性
エツチングをプレーナ型プラズマ・エツチヤーに
より行なうことにより、より十分目的を達成する
ことができる。
以下本発明の一実施例を図面に従つて詳細に説
明する。
第４図乃至第６図は本発明の一実施例を説明す
るための断面図である。本実施例では、シリコン
よりなる基板１上に絶縁膜（例えばSiO2）２を
介してAlよりなる配線パターン３が形成され、
さらにその上に被エツチング被膜である絶縁膜４
としてPSG（Phospho−Silicate Glass）を膜厚
約1.0μに形成し、その上にエツチング・マスクと
なる薄膜５としてポジ・フオトレジストを膜厚約
1.5μ形成して、周知のフオトリソグラフイ技術に
よりポジ・フオトレジスト５を窓開きする。そし
てこの薄膜パターンであるポジ・フオトレジスト
５をマスクにして、先ずバレル型プラズマ・エツ
チヤーにより、PSG４に例えば約6000Åの等方
性エツチングを施こす。そのプラズマ・エツチン
グの条件は例えばパワーが300W、雰囲気がCF4、
O2（５％）のガス0.8Torrで、約５〜８分間行な
う。この等方性エツチングにより、サイドエツチ
ングが行なわれるため第４図に示すようにエツチ
ングの形状W2はポジ・フオトレジスト５の窓開
きの形状W1に比べて少々大きくなつている。
次にポジ・フオトレジスト５をマスクにしてプ
レーナ型プラズマ・エツチヤーによりPSG４の
残りの部分をエツチングする。そのプラズマ・エ
ツチングの条件は例えばパワーが1250W、雰囲気
がCHF3のガス0.2Torrで、約７分間行なうもの
である。
このプレーナ型プラズマ・エツチヤーによれば
前述した様にPSG４が基板１の表面に垂直な方
向に異方性エツチングされるため、エツチングの
形状W3はポジ・フオトレジスト３の窓開きの形
状W1とほぼ同形になる。その結果形成されたビ
ア・ホール６は第５図に示すようにテーパーを有
し、しかもその形状は第１図の従来例に比べて微
細化されている。
そしてポジ・フオトレジスト５を除去した後、
所定膜として例えばAlよりなる配線パターン７
を周知の技術で被着形成する。すると第６図に示
すようにビア・ホール６の形状がテーパーを有し
ているため、図中８に示すようにビア・ホール６
の部分でも配線パターン７の膜厚が薄くなつたり
あるいは断線したりして被着形成されることはな
い。
なお本実施例ではビア・ホールについて述べた
が、電極窓の形成についても同様に実施できる。
また、シリコン基板上に形成された酸化膜
（SiO2）に電極窓を形成する場合、プレーナ型プ
ラズマ・エツチヤーによりエツチングを施こす
時、シリコン（Si）がエツチングされる速度が酸
化膜（SiO2）をエツチングする場合に比べて非
常に遅いため、酸化膜（SiO2）のエツチングの
終了の制御が簡単である。
また他の実施例として、プレーナ型プラズマ・
エツチヤーによるシリコン基板への損傷が懸念さ
れる場合には、絶縁膜を500Å〜1000Å程度残し
ておいて、次に緩衝HF溶液によるウエツト・エ
ツチングにより残存の絶縁膜をエツチングすれば
よい。このウエツト・エツチングは電極窓又はビ
ア・ホール等の形状の精度を多少損うがこの程度
は無視できる範囲にある。
以上説明した様に本発明によれば、テーパーを
有する微細な電極窓及びビア・ホール等の孔部を
形成することができるため、配線パターンを前記
の孔部を通じて基板等に接続する場合、配線パタ
ーンの膜厚が薄くなつたり断線したりして不良と
なるのを防ぐことができるという効果がある。ま
た本発明によればテーパーを有する微細な配線パ
ターンをも形成できるので、その上に絶縁膜を介
して交差する配線パターンの断線も防止すること
ができる。
【図面の簡単な説明】
第１図は等方性エツチングにより孔部を形成し
た場合の断面図、第２図、第３図は異方性エツチ
ングにより孔部を形成した場合の断面図、第４
図、第５図、第６図は本発明の一実施例を説明す
るための断面図。 図中、１は基板、２は絶縁膜、３は配線パター
ン、４はエツチングされる絶縁膜（被エツチング
被膜）、５は薄膜パターン（エツチングマスク）、
６は孔部（電極窓、ビア・ホール等）、７は配線
パターンである。

Claims (1)

  1. 【特許請求の範囲】 １ 基板上に形成した被エツチング被膜上に所定
    の薄膜パターンを形成する工程、 該薄膜パターンをマスクにして被エツチング被
    膜に、途中まで等方性プラズマエツチングを施こ
    し、続いて該薄膜パターンをマスクにして膜厚方
    向への異方性プラズマエツチングを施こして、側
    面の上部がテーパー形状で下部がほぼ垂直形状を
    もつた該被エツチング被膜のパターンを形成する
    工程、 該薄膜パターン除去後、該被エツチング被膜上
    に所定膜を形成する工程を有することを特徴とす
    る半導体装置の製造方法。
JP15400379A 1979-11-28 1979-11-28 Manufacture of semiconductor device Granted JPS5690525A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP15400379A JPS5690525A (en) 1979-11-28 1979-11-28 Manufacture of semiconductor device
US06208391 US4352724B1 (en) 1979-11-28 1980-11-19 Method of manufacturing a semiconductor device
EP80304232A EP0030116B2 (en) 1979-11-28 1980-11-26 Method of manufacturing a semiconductor device having a patterned multi-layer structure
DE8080304232T DE3072013D1 (en) 1979-11-28 1980-11-26 Method of manufacturing a semiconductor device having a patterned multi-layer structure
IE2457/80A IE52972B1 (en) 1979-11-28 1980-11-26 Method of manufacturing a semiconductor device having a patterned multi-layer structure
CA000365656A CA1155973A (en) 1979-11-28 1980-11-27 Method of etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15400379A JPS5690525A (en) 1979-11-28 1979-11-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5690525A JPS5690525A (en) 1981-07-22
JPH0135495B2 true JPH0135495B2 (ja) 1989-07-25

Family

ID=15574782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15400379A Granted JPS5690525A (en) 1979-11-28 1979-11-28 Manufacture of semiconductor device

Country Status (6)

Country Link
US (1) US4352724B1 (ja)
EP (1) EP0030116B2 (ja)
JP (1) JPS5690525A (ja)
CA (1) CA1155973A (ja)
DE (1) DE3072013D1 (ja)
IE (1) IE52972B1 (ja)

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Also Published As

Publication number Publication date
EP0030116A2 (en) 1981-06-10
EP0030116B2 (en) 1992-04-22
US4352724A (en) 1982-10-05
IE52972B1 (en) 1988-04-27
IE802457L (en) 1981-05-28
CA1155973A (en) 1983-10-25
DE3072013D1 (en) 1987-09-24
JPS5690525A (en) 1981-07-22
EP0030116B1 (en) 1987-08-19
EP0030116A3 (en) 1985-05-15
US4352724B1 (en) 1997-06-10

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