JP7513385B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7513385B2
JP7513385B2 JP2019218961A JP2019218961A JP7513385B2 JP 7513385 B2 JP7513385 B2 JP 7513385B2 JP 2019218961 A JP2019218961 A JP 2019218961A JP 2019218961 A JP2019218961 A JP 2019218961A JP 7513385 B2 JP7513385 B2 JP 7513385B2
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conductive layer
disposed
layer
memory cell
pad
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JP2020102613A5 (https=
JP2020102613A (ja
Inventor
宏治 金森
玄 睦 朴
容 錫 金
ギョン 奐 李
濬 熙 林
智 勳 韓
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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    • H10W80/331—Bonding techniques, e.g. hybrid bonding characterised by the application of energy for connecting
    • H10W80/333—Compression bonding
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    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/721—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having structure or size changed during the connecting
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    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2019218961A 2018-12-21 2019-12-03 半導体装置 Active JP7513385B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0167170 2018-12-21
KR1020180167170A KR102658194B1 (ko) 2018-12-21 2018-12-21 반도체 장치

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JP2020102613A JP2020102613A (ja) 2020-07-02
JP2020102613A5 JP2020102613A5 (https=) 2022-12-07
JP7513385B2 true JP7513385B2 (ja) 2024-07-09

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US (2) US10998301B2 (https=)
JP (1) JP7513385B2 (https=)
KR (1) KR102658194B1 (https=)
DE (1) DE102019122665B4 (https=)

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KR20220020720A (ko) * 2020-08-12 2022-02-21 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
JP7467278B2 (ja) * 2020-08-17 2024-04-15 キオクシア株式会社 半導体記憶装置
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JP2022035130A (ja) * 2020-08-20 2022-03-04 キオクシア株式会社 半導体記憶装置
JP2022035158A (ja) * 2020-08-20 2022-03-04 キオクシア株式会社 半導体記憶装置
JP2022037612A (ja) * 2020-08-25 2022-03-09 キオクシア株式会社 半導体記憶装置
KR20220027550A (ko) * 2020-08-27 2022-03-08 삼성전자주식회사 온도 보상을 수행하는 메모리 장치 및 그 동작방법
KR20250021390A (ko) * 2020-09-02 2025-02-12 양쯔 메모리 테크놀로지스 씨오., 엘티디. Xtacking 아키텍처의 패드 아웃 구조
JP7583561B2 (ja) * 2020-09-08 2024-11-14 キオクシア株式会社 半導体装置およびその製造方法
KR20220034273A (ko) * 2020-09-10 2022-03-18 삼성전자주식회사 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템
KR102845805B1 (ko) * 2020-10-15 2025-08-14 에스케이하이닉스 주식회사 메모리셀 및 그를 구비한 반도체 장치
KR102938306B1 (ko) * 2020-10-28 2026-03-12 삼성전자주식회사 기판의 양면에 배치된 주변 회로 영역들을 갖는 반도체 소자 및 이를 포함하는 데이터 저장 시스템
KR102899036B1 (ko) * 2020-10-30 2025-12-11 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
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