KR102658194B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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KR102658194B1
KR102658194B1 KR1020180167170A KR20180167170A KR102658194B1 KR 102658194 B1 KR102658194 B1 KR 102658194B1 KR 1020180167170 A KR1020180167170 A KR 1020180167170A KR 20180167170 A KR20180167170 A KR 20180167170A KR 102658194 B1 KR102658194 B1 KR 102658194B1
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disposed
memory cell
layer
conductive layer
gate electrodes
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KR20200078752A (ko
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코지 카나모리
박현목
김용석
이경환
임준희
한지훈
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삼성전자주식회사
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Priority to KR1020180167170A priority Critical patent/KR102658194B1/ko
Priority to US16/531,778 priority patent/US10998301B2/en
Priority to DE102019122665.1A priority patent/DE102019122665B4/de
Priority to JP2019218961A priority patent/JP7513385B2/ja
Publication of KR20200078752A publication Critical patent/KR20200078752A/ko
Priority to US17/245,299 priority patent/US11721684B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/874—On different surfaces
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/331—Bonding techniques, e.g. hybrid bonding characterised by the application of energy for connecting
    • H10W80/333—Compression bonding
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/721—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having structure or size changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/743—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having disposition changed during the connecting
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020180167170A 2018-12-21 2018-12-21 반도체 장치 Active KR102658194B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020180167170A KR102658194B1 (ko) 2018-12-21 2018-12-21 반도체 장치
US16/531,778 US10998301B2 (en) 2018-12-21 2019-08-05 Semiconductor device
DE102019122665.1A DE102019122665B4 (de) 2018-12-21 2019-08-22 Halbleitervorrichtung
JP2019218961A JP7513385B2 (ja) 2018-12-21 2019-12-03 半導体装置
US17/245,299 US11721684B2 (en) 2018-12-21 2021-04-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180167170A KR102658194B1 (ko) 2018-12-21 2018-12-21 반도체 장치

Publications (2)

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KR20200078752A KR20200078752A (ko) 2020-07-02
KR102658194B1 true KR102658194B1 (ko) 2024-04-18

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US (2) US10998301B2 (https=)
JP (1) JP7513385B2 (https=)
KR (1) KR102658194B1 (https=)
DE (1) DE102019122665B4 (https=)

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892269B2 (en) * 2014-09-12 2021-01-12 Toshiba Memory Corporation Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit
JP6203152B2 (ja) 2014-09-12 2017-09-27 東芝メモリ株式会社 半導体記憶装置の製造方法
KR102801216B1 (ko) * 2018-12-19 2025-04-30 삼성전자주식회사 수직형 메모리 장치
KR102658194B1 (ko) * 2018-12-21 2024-04-18 삼성전자주식회사 반도체 장치
KR102612197B1 (ko) * 2019-01-11 2023-12-12 삼성전자주식회사 반도체 장치
JP2020141100A (ja) * 2019-03-01 2020-09-03 キオクシア株式会社 半導体装置およびその製造方法
JP2020145231A (ja) * 2019-03-04 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
JP7331119B2 (ja) 2019-04-15 2023-08-22 長江存儲科技有限責任公司 複数の機能性チップを伴う三次元ｎａｎｄメモリデバイスの集積
US11424169B2 (en) * 2019-08-08 2022-08-23 Micron Technology, Inc. Memory device including circuitry under bond pads
JP2021048249A (ja) * 2019-09-18 2021-03-25 キオクシア株式会社 半導体装置およびその製造方法
US11239238B2 (en) 2019-10-29 2022-02-01 Intel Corporation Thin film transistor based memory cells on both sides of a layer of logic devices
KR102650428B1 (ko) * 2019-11-06 2024-03-25 에스케이하이닉스 주식회사 반도체 메모리 장치
KR102673730B1 (ko) * 2019-11-07 2024-06-10 삼성전자주식회사 반도체 소자 및 이를 구비한 반도체 패키지
JP2021089972A (ja) * 2019-12-04 2021-06-10 キオクシア株式会社 半導体記憶装置
KR20210088810A (ko) * 2020-01-06 2021-07-15 에스케이하이닉스 주식회사 3차원 반도체 메모리 장치
US11251182B2 (en) * 2020-03-17 2022-02-15 International Business Machines Corporation Staggered stacked vertical crystalline semiconducting channels
CN112352315B (zh) 2020-04-14 2022-10-11 长江存储科技有限责任公司 具有背面互连结构的三维存储器件
KR20210141175A (ko) * 2020-05-15 2021-11-23 에스케이하이닉스 주식회사 반도체 장치 및 그의 제조 방법
US11158622B1 (en) 2020-05-27 2021-10-26 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices
WO2021237883A1 (en) 2020-05-27 2021-12-02 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices
US11877448B2 (en) 2020-05-27 2024-01-16 Yangtze Memory Technologies Co., Ltd. Methods for forming three-dimensional memory devices
US12048151B2 (en) 2020-05-27 2024-07-23 Yangtze Memory Technologies Co., Ltd. Methods for forming three-dimensional memory devices with backside source contacts
US11963349B2 (en) 2020-05-27 2024-04-16 Yangtze Memory Technologies Co., Ltd. Methods for forming three-dimensional memory devices with backside source contacts
US11653500B2 (en) 2020-06-25 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array contact structures
US11985825B2 (en) 2020-06-25 2024-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. 3D memory array contact structures
US11532343B2 (en) 2020-06-26 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array including dummy regions
US11600520B2 (en) 2020-06-26 2023-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Air gaps in memory array structures
US11640974B2 (en) 2020-06-30 2023-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array isolation structures
TWI756781B (zh) * 2020-07-07 2022-03-01 大陸商長江存儲科技有限責任公司 用於形成立體記憶元件的方法
US11647634B2 (en) 2020-07-16 2023-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11355516B2 (en) 2020-07-16 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11495618B2 (en) 2020-07-30 2022-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
EP4694614A3 (en) 2020-07-31 2026-04-08 Yangtze Memory Technologies Co., Ltd. Methods for forming contact structures and semiconductor devices thereof
KR102776460B1 (ko) * 2020-08-07 2025-03-10 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR102876507B1 (ko) * 2020-08-10 2025-10-23 삼성전자주식회사 페이지 버퍼 회로 및 이를 포함하는 메모리 장치
KR20220020720A (ko) * 2020-08-12 2022-02-21 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
JP7467278B2 (ja) * 2020-08-17 2024-04-15 キオクシア株式会社 半導体記憶装置
KR102937011B1 (ko) * 2020-08-19 2026-03-09 삼성전자주식회사 반도체 장치, 이를 포함하는 비휘발성 메모리 장치, 이를 포함하는 전자 시스템 및 이의 제조 방법
JP2022035130A (ja) * 2020-08-20 2022-03-04 キオクシア株式会社 半導体記憶装置
JP2022035158A (ja) * 2020-08-20 2022-03-04 キオクシア株式会社 半導体記憶装置
JP2022037612A (ja) * 2020-08-25 2022-03-09 キオクシア株式会社 半導体記憶装置
KR20220027550A (ko) * 2020-08-27 2022-03-08 삼성전자주식회사 온도 보상을 수행하는 메모리 장치 및 그 동작방법
KR20250021390A (ko) * 2020-09-02 2025-02-12 양쯔 메모리 테크놀로지스 씨오., 엘티디. Xtacking 아키텍처의 패드 아웃 구조
JP7583561B2 (ja) * 2020-09-08 2024-11-14 キオクシア株式会社 半導体装置およびその製造方法
KR20220034273A (ko) * 2020-09-10 2022-03-18 삼성전자주식회사 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템
KR102845805B1 (ko) * 2020-10-15 2025-08-14 에스케이하이닉스 주식회사 메모리셀 및 그를 구비한 반도체 장치
KR102938306B1 (ko) * 2020-10-28 2026-03-12 삼성전자주식회사 기판의 양면에 배치된 주변 회로 영역들을 갖는 반도체 소자 및 이를 포함하는 데이터 저장 시스템
KR102899036B1 (ko) * 2020-10-30 2025-12-11 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
KR102878005B1 (ko) * 2020-10-30 2025-10-29 삼성전자주식회사 댐 구조체를 갖는 반도체 소자
KR102891551B1 (ko) * 2020-11-04 2025-11-25 삼성전자 주식회사 반도체 장치 및 이를 포함하는 전자 시스템
US12381193B2 (en) 2020-12-01 2025-08-05 Intel Corporation Integrated circuit assemblies
TWI885204B (zh) * 2020-12-08 2025-06-01 美商英特爾股份有限公司 積體電路裝置及組件的混合製造
US11817442B2 (en) 2020-12-08 2023-11-14 Intel Corporation Hybrid manufacturing for integrated circuit devices and assemblies
US11756886B2 (en) 2020-12-08 2023-09-12 Intel Corporation Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures
KR102901363B1 (ko) * 2020-12-14 2025-12-18 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN112740404B (zh) 2020-12-18 2023-05-26 长江存储科技有限责任公司 存储器件及其制造方法
KR102773068B1 (ko) * 2020-12-24 2025-02-24 양쯔 메모리 테크놀로지스 씨오., 엘티디. 3차원 메모리 디바이스의 접촉 패드 및 그 제조 방법
WO2022168197A1 (ja) 2021-02-03 2022-08-11 キオクシア株式会社 半導体記憶装置
KR102924461B1 (ko) * 2021-02-15 2026-02-09 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
JP2022131445A (ja) * 2021-02-26 2022-09-07 キオクシア株式会社 半導体装置及びその製造方法
US11716856B2 (en) 2021-03-05 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
JP2022135584A (ja) * 2021-03-05 2022-09-15 キオクシア株式会社 半導体装置
KR102896521B1 (ko) 2021-03-24 2025-12-09 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
US12015010B2 (en) * 2021-03-31 2024-06-18 Taiwan Semiconductor Manufacturing Company Limited Vertically stacked semiconductor device including a hybrid bond contact junction circuit and methods of forming the same
US12412835B2 (en) 2021-04-27 2025-09-09 Intel Corporation Back-side power delivery with glass support at the front
KR102832410B1 (ko) * 2021-05-17 2025-07-10 에스케이하이닉스 주식회사 메모리 장치
KR102918712B1 (ko) * 2021-06-10 2026-01-26 삼성전자주식회사 반도체 메모리 장치 및 이의 제조 방법
US12400997B2 (en) 2021-06-11 2025-08-26 Intel Corporation Hybrid manufacturing with modified via-last process
JP2022191630A (ja) 2021-06-16 2022-12-28 キオクシア株式会社 半導体記憶装置
US12526985B2 (en) * 2021-06-23 2026-01-13 Intel Corporation Back-side reveal for power delivery to backend memory with frontend transistors and backend memroy cells
KR102901389B1 (ko) 2021-07-06 2025-12-17 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 제조 방법
CN113488392B (zh) * 2021-07-13 2022-08-02 武汉新芯集成电路制造有限公司 集成电路器件制造方法
CN113555369B (zh) * 2021-07-13 2025-01-28 维沃移动通信有限公司 存储装置、制备方法及电子设备
US12171096B2 (en) 2021-08-13 2024-12-17 Micron Technology, Inc. Microelectronic devices, and related memory devices and electronic systems
CN113906560A (zh) * 2021-08-31 2022-01-07 长江存储科技有限责任公司 半导体设备的焊盘结构
US12520495B2 (en) * 2021-09-08 2026-01-06 Intel NDTM US LLC 3D NAND with IO contacts in isolation trench
JP2023043671A (ja) 2021-09-16 2023-03-29 キオクシア株式会社 半導体記憶装置及びその設計方法
JP2023044255A (ja) * 2021-09-17 2023-03-30 キオクシア株式会社 半導体記憶装置およびその製造方法
JP7739147B2 (ja) 2021-11-15 2025-09-16 キオクシア株式会社 半導体記憶装置
KR102909722B1 (ko) * 2021-12-07 2026-01-07 삼성전자주식회사 반도체 장치, 상기 반도체 장치의 제조용 장치 및 이를 이용한 상기 반도체 장치의 제조 방법
JP2023137581A (ja) * 2022-03-18 2023-09-29 キオクシア株式会社 半導体装置、半導体装置の製造方法
KR20230167794A (ko) * 2022-06-02 2023-12-12 삼성전자주식회사 반도체 장치 및 제조 방법
JP2023177973A (ja) 2022-06-03 2023-12-14 キオクシア株式会社 半導体記憶装置
JP2023177814A (ja) * 2022-06-03 2023-12-14 キオクシア株式会社 半導体記憶装置
EP4548723A1 (en) 2022-06-29 2025-05-07 Intel Corporation Memory arrays with backside components and angled transistors
KR20240011373A (ko) 2022-07-19 2024-01-26 삼성전자주식회사 반도체 장치
KR20240016714A (ko) 2022-07-29 2024-02-06 삼성전자주식회사 3차원 반도체 메모리 장치, 이를 포함하는 전자 시스템
JP2024046343A (ja) 2022-09-22 2024-04-03 キオクシア株式会社 半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016062901A (ja) * 2014-09-12 2016-04-25 株式会社東芝 半導体記憶装置及びその製造方法
WO2018161838A1 (en) 2017-03-07 2018-09-13 Yangtze Memory Technologies Co., Ltd. Composite substrate of three-dimensional memory devices
JP2018148071A (ja) 2017-03-07 2018-09-20 東芝メモリ株式会社 記憶装置
JP2018152419A (ja) * 2017-03-10 2018-09-27 東芝メモリ株式会社 半導体記憶装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537552B1 (ko) 2000-07-31 2005-12-16 매그나칩 반도체 유한회사 반도체 소자 및 그의 제조 방법
KR100400047B1 (ko) * 2001-11-19 2003-09-29 삼성전자주식회사 반도체 소자의 본딩패드 구조 및 그 형성방법
KR20100052597A (ko) * 2008-11-11 2010-05-20 삼성전자주식회사 수직형 반도체 장치
JP2011187794A (ja) * 2010-03-10 2011-09-22 Toshiba Corp 半導体記憶装置及びその製造方法
JP2011204829A (ja) 2010-03-25 2011-10-13 Toshiba Corp 半導体記憶装置
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
US9502471B1 (en) * 2015-08-25 2016-11-22 Sandisk Technologies Llc Multi tier three-dimensional memory devices including vertically shared bit lines
KR102495000B1 (ko) 2016-03-18 2023-02-02 삼성전자주식회사 반도체 소자 및 이의 제조방법
KR102589301B1 (ko) * 2016-04-29 2023-10-13 삼성전자주식회사 비휘발성 메모리 장치
KR102537248B1 (ko) 2016-07-06 2023-05-30 삼성전자주식회사 3차원 반도체 메모리 장치
US9876031B1 (en) 2016-11-30 2018-01-23 Sandisk Technologies Llc Three-dimensional memory device having passive devices at a buried source line level and method of making thereof
JP2018163970A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置及びその製造方法
CN107658315B (zh) * 2017-08-21 2019-05-14 长江存储科技有限责任公司 半导体装置及其制备方法
KR102658194B1 (ko) * 2018-12-21 2024-04-18 삼성전자주식회사 반도체 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016062901A (ja) * 2014-09-12 2016-04-25 株式会社東芝 半導体記憶装置及びその製造方法
WO2018161838A1 (en) 2017-03-07 2018-09-13 Yangtze Memory Technologies Co., Ltd. Composite substrate of three-dimensional memory devices
JP2018148071A (ja) 2017-03-07 2018-09-20 東芝メモリ株式会社 記憶装置
JP2018152419A (ja) * 2017-03-10 2018-09-27 東芝メモリ株式会社 半導体記憶装置

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