JP7354464B2 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
JP7354464B2
JP7354464B2 JP2022557331A JP2022557331A JP7354464B2 JP 7354464 B2 JP7354464 B2 JP 7354464B2 JP 2022557331 A JP2022557331 A JP 2022557331A JP 2022557331 A JP2022557331 A JP 2022557331A JP 7354464 B2 JP7354464 B2 JP 7354464B2
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Japan
Prior art keywords
conductive
semiconductor
semiconductor elements
input terminal
conductive member
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English (en)
Japanese (ja)
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JPWO2022080122A1 (https=
Inventor
健二 林
昂平 谷川
諒介 福田
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Rohm Co Ltd
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Rohm Co Ltd
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Publication of JPWO2022080122A1 publication Critical patent/JPWO2022080122A1/ja
Priority to JP2023127195A priority Critical patent/JP7354475B1/ja
Priority to JP2023152332A priority patent/JP7382534B1/ja
Application granted granted Critical
Publication of JP7354464B2 publication Critical patent/JP7354464B2/ja
Priority to JP2023189566A priority patent/JP7645340B2/ja
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    • HELECTRICITY
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    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
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    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
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    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W40/25Arrangements for cooling characterised by their materials
    • H10W40/255Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
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    • H10W72/323Multilayered die-attach connectors, e.g. a coating on a top surface of a core characterised by the structures of the outermost layers, e.g. multilayered coatings
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  • Inverter Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2022557331A 2020-10-14 2021-09-27 半導体モジュール Active JP7354464B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2023127195A JP7354475B1 (ja) 2020-10-14 2023-08-03 半導体モジュール
JP2023152332A JP7382534B1 (ja) 2020-10-14 2023-09-20 半導体モジュール
JP2023189566A JP7645340B2 (ja) 2020-10-14 2023-11-06 半導体モジュール

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Application Number Priority Date Filing Date Title
JP2020173339 2020-10-14
JP2020173339 2020-10-14
PCT/JP2021/035261 WO2022080122A1 (ja) 2020-10-14 2021-09-27 半導体モジュール

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JPWO2022080122A1 JPWO2022080122A1 (https=) 2022-04-21
JP7354464B2 true JP7354464B2 (ja) 2023-10-02

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JP2023127195A Active JP7354475B1 (ja) 2020-10-14 2023-08-03 半導体モジュール
JP2023152332A Active JP7382534B1 (ja) 2020-10-14 2023-09-20 半導体モジュール
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