JP7232628B2 - 不揮発性メモリ装置、不揮発性メモリ装置の動作方法、及び貯蔵装置 - Google Patents
不揮発性メモリ装置、不揮発性メモリ装置の動作方法、及び貯蔵装置 Download PDFInfo
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- JP7232628B2 JP7232628B2 JP2018226638A JP2018226638A JP7232628B2 JP 7232628 B2 JP7232628 B2 JP 7232628B2 JP 2018226638 A JP2018226638 A JP 2018226638A JP 2018226638 A JP2018226638 A JP 2018226638A JP 7232628 B2 JP7232628 B2 JP 7232628B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- G—PHYSICS
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
- G06F3/0649—Lifecycle management
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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- G—PHYSICS
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
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- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170177848A KR102469539B1 (ko) | 2017-12-22 | 2017-12-22 | 비휘발성 메모리 장치, 비휘발성 메모리 장치의 동작 방법 및 저장 장치 |
KR10-2017-0177848 | 2017-12-22 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2019114320A JP2019114320A (ja) | 2019-07-11 |
JP2019114320A5 JP2019114320A5 (ko) | 2022-01-11 |
JP7232628B2 true JP7232628B2 (ja) | 2023-03-03 |
Family
ID=66767971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2018226638A Active JP7232628B2 (ja) | 2017-12-22 | 2018-12-03 | 不揮発性メモリ装置、不揮発性メモリ装置の動作方法、及び貯蔵装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US10712954B2 (ko) |
JP (1) | JP7232628B2 (ko) |
KR (1) | KR102469539B1 (ko) |
CN (1) | CN109961819A (ko) |
DE (1) | DE102018125128B4 (ko) |
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KR102460526B1 (ko) * | 2018-01-04 | 2022-11-01 | 삼성전자주식회사 | 불휘발성 메모리 장치를 포함하는 스토리지 장치, 불휘발성 메모리 장치, 그리고 스토리지 장치의 동작 방법 |
KR102596407B1 (ko) * | 2018-03-13 | 2023-11-01 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
KR20200132495A (ko) * | 2019-05-17 | 2020-11-25 | 에스케이하이닉스 주식회사 | 메모리 시스템, 컨트롤러 및 컨트롤러의 동작 방법 |
KR20200141304A (ko) * | 2019-06-10 | 2020-12-18 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치의 동작 방법 |
KR20210034274A (ko) | 2019-09-20 | 2021-03-30 | 삼성전자주식회사 | 비휘발성 메모리 장치의 구동 방법 및 이를 수행하는 비휘발성 메모리 장치 |
KR20210043241A (ko) * | 2019-10-11 | 2021-04-21 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 제조 방법 |
US11487454B2 (en) * | 2019-12-05 | 2022-11-01 | Sandisk Technologies Llc | Systems and methods for defining memory sub-blocks |
KR20210100880A (ko) * | 2020-02-07 | 2021-08-18 | 에스케이하이닉스 주식회사 | 복수의 메모리 칩들을 갖는 반도체 메모리 장치 |
CN113299333A (zh) * | 2020-02-21 | 2021-08-24 | 硅存储技术股份有限公司 | 由闪存单元构成的eeprom仿真器中的损耗均衡 |
KR20210123528A (ko) | 2020-04-03 | 2021-10-14 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 이를 포함하는 저장장치 및 그 동작 방법 |
CN111564174A (zh) * | 2020-04-23 | 2020-08-21 | 上海华虹宏力半导体制造有限公司 | 一种支持块擦除的数字冗余电路及其操作方法 |
US11455244B2 (en) | 2020-09-04 | 2022-09-27 | Western Digital Technologies, Inc. | Zoned namespace limitation mitigation using sub block mode |
JP2022048489A (ja) | 2020-09-15 | 2022-03-28 | キオクシア株式会社 | 半導体記憶装置 |
TWI766559B (zh) * | 2021-01-26 | 2022-06-01 | 旺宏電子股份有限公司 | 記憶體裝置的操作方法 |
CN115810379A (zh) * | 2021-09-13 | 2023-03-17 | 长鑫存储技术有限公司 | 存储电路及存储器 |
US11875842B2 (en) * | 2021-11-09 | 2024-01-16 | Sandisk Technologies Llc | Systems and methods for staggering read operation of sub-blocks |
US11798639B2 (en) * | 2021-11-22 | 2023-10-24 | Macronix International Co., Ltd. | Memory device and operation method thereof |
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US10712954B2 (en) | 2020-07-14 |
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US20200293204A1 (en) | 2020-09-17 |
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