JP7232628B2 - 不揮発性メモリ装置、不揮発性メモリ装置の動作方法、及び貯蔵装置 - Google Patents

不揮発性メモリ装置、不揮発性メモリ装置の動作方法、及び貯蔵装置 Download PDF

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JP7232628B2
JP7232628B2 JP2018226638A JP2018226638A JP7232628B2 JP 7232628 B2 JP7232628 B2 JP 7232628B2 JP 2018226638 A JP2018226638 A JP 2018226638A JP 2018226638 A JP2018226638 A JP 2018226638A JP 7232628 B2 JP7232628 B2 JP 7232628B2
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block
sub
memory
erase
bad
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JP2019114320A (ja
JP2019114320A5 (ko
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承範 金
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
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    • G11C2029/1206Location of test circuitry on chip or wafer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2018226638A 2017-12-22 2018-12-03 不揮発性メモリ装置、不揮発性メモリ装置の動作方法、及び貯蔵装置 Active JP7232628B2 (ja)

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Application Number Priority Date Filing Date Title
KR1020170177848A KR102469539B1 (ko) 2017-12-22 2017-12-22 비휘발성 메모리 장치, 비휘발성 메모리 장치의 동작 방법 및 저장 장치
KR10-2017-0177848 2017-12-22

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JP2019114320A JP2019114320A (ja) 2019-07-11
JP2019114320A5 JP2019114320A5 (ko) 2022-01-11
JP7232628B2 true JP7232628B2 (ja) 2023-03-03

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US (2) US10712954B2 (ko)
JP (1) JP7232628B2 (ko)
KR (1) KR102469539B1 (ko)
CN (1) CN109961819A (ko)
DE (1) DE102018125128B4 (ko)

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KR20210034274A (ko) 2019-09-20 2021-03-30 삼성전자주식회사 비휘발성 메모리 장치의 구동 방법 및 이를 수행하는 비휘발성 메모리 장치
KR20210043241A (ko) * 2019-10-11 2021-04-21 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 제조 방법
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CN111564174A (zh) * 2020-04-23 2020-08-21 上海华虹宏力半导体制造有限公司 一种支持块擦除的数字冗余电路及其操作方法
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JP2022048489A (ja) 2020-09-15 2022-03-28 キオクシア株式会社 半導体記憶装置
TWI766559B (zh) * 2021-01-26 2022-06-01 旺宏電子股份有限公司 記憶體裝置的操作方法
CN115810379A (zh) * 2021-09-13 2023-03-17 长鑫存储技术有限公司 存储电路及存储器
US11875842B2 (en) * 2021-11-09 2024-01-16 Sandisk Technologies Llc Systems and methods for staggering read operation of sub-blocks
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