JP6955566B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6955566B2 JP6955566B2 JP2019535133A JP2019535133A JP6955566B2 JP 6955566 B2 JP6955566 B2 JP 6955566B2 JP 2019535133 A JP2019535133 A JP 2019535133A JP 2019535133 A JP2019535133 A JP 2019535133A JP 6955566 B2 JP6955566 B2 JP 6955566B2
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- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Description
、サリサイドプロセスを適用した場合、ゲート電極108及びその側壁に形成されたサイドウォール絶縁膜を形成していない領域の素子領域100上は、シリサイド膜によって覆われる。そのため、ソース領域102あるいはドレイン領域104と、ボディコンタクト領域106とを分離するように、ゲート電極108を形成しなければ、これら領域がシリサイド膜を介して電気的に接続されるからである。このように、ゲート電極を延在することにより、ソース領域あるいはドレイン領域からボディコンタクト領域を分離することができる。
図1〜図4は、本開示の第1の実施形態における半導体装置の構成を模式的に示した図で、図1は平面図、図2〜図4は、それぞれ、図1のA−A’線、B−B’線、C−C’線に沿った断面図である。なお、本実施形態では、SOI基板を用いた例で説明するが、これに限定されるものではない。
図5は、第1の実施形態の変形例1における半導体装置の構成を模式的に示した平面図である。
図6は、第1の実施形態の変形例2における半導体装置の構成を模式的に示した平面図である。
図7は、第1の実施形態の応用例1における半導体装置の構成を模式的に示した平面図である。
図8は、第1の実施形態の応用例2における半導体装置の構成を模式的に示した平面図である。
図9は、第1の実施形態の応用例3における半導体装置の構成を模式的に示した平面図である。
図10は、本開示の第2の実施形態における半導体装置の構成を模式的に示した平面図である。
図11は、第2の実施形態の応用例における半導体装置の構成を模式的に示した平面図である。
図12〜図14は、本開示の第3の実施形態における半導体装置の構成を模式的に示した図で、図12は平面図、図13、14は、それぞれ、図12のA−A’線、B−B’線に沿った断面図である。
図15は、第3の実施形態の変形例における半導体装置の構成を模式的に示した平面図である。
図16は、第3の実施形態の応用例1における半導体装置の構成を模式的に示した平面図である。
図17は、第3の実施形態の応用例2における半導体装置の構成を模式的に示した平面図である。
図18、19は、本開示の第4の実施形態における半導体装置の構成を模式的に示した図で、図18は平面図、図19は、図18のB−B’線に沿った断面図である。
図20、21は、第4の実施形態の変形例における半導体装置の構成を模式的に示した図で、図20は平面図、図21は、図20のB−B’線に沿った断面図である。
図22、23は、本開示の第5の実施形態における半導体装置の構成を模式的に示した平面図である。
図24は、本開示の第6の実施形態における半導体装置の構成を模式的に示した平面図である。
図25は、本開示の第7の実施形態における半導体装置の構成を模式的に示した平面図である。
アンテナへの信号を分離するスイッチ回路では、高電圧が印加される場合があり、これに対応するために、複数のトランジスタを直列に接続する構成がとられる。ただし、これらのスイッチ回路においても、各所の容量を低減し高速特性を確保することが求められている。
第8の実施形態では、4つのトランジスタを直列に接続した1つのトランジスタ群を示しているが、本実施形態では、図28に示すように、これらを複数群配置した構成をなす。
本実施形態では、図32に示すように、上記第9の実施形態に対して、Source0とDrain3間の配線容量を低減した構成をなす。図33は、図32の左上の拡大図である。この図面におけるA−A’線に沿った断面図を図34に示す。この断面図からわかるように、まず、トランジスタのゲート電極G0A,G1A,G2A,G3A,G0B,G1B,G2B,G3Bがあり、その上層に第1の配線層(図面に記号なし)があり、さらに上層に第2の配線層が形成されているが、A−A’断面においては、断面図の左からSource0(M2A),Source0(M2C)のみとなっており、Drain3は存在しない。このためSource0とDrain3間の配線容量は大幅に低減された構成であり、動作速度の改善にもつながる構成である。
本実施形態では、図35に示すように、1つのトランジスタ群にある直列に接続された4つのトランジスタの中間ノードについて、それぞれのトランジスタ群間のノードを接続した構成をなす。図中のN1,N2,N3と示されたところが、それぞれのノードを接続した配線である。本実施形態の等価回路は図36に示すようになる。本構成により、各トランジスタ群において、トランジスタの特性や容量ばらつきにより印加電位などが異なるなどの状況が発生した場合でも、それぞれのトランジスタ群間のノードが接続された構成であるため、その影響度が抑制されるという効果がある。
本実施形態では、図37に示すように、上記第11の実施形態に対して、第3の配線層を形成することにより、第2の配線層で形成されたsource0およびDrain3のそれぞれを強化し抵抗を低減した構成をなす。図38は、図37の左上の拡大図である。この図面におけるA−A’線に沿った断面図を図39に示す。この断面図からわかるように、Source0(M2A)とSource0(M2C)が、第3配線層で接続された構成である。図示されていないが、図38の図面の下方での断面では、第2の配線層で形成されたDrain3が、第3の配線層で接続された構成である。第3の配線層で形成されたSource0とDrain3は、平面的にスペースをもって形成されているので、容量も少ない構成であり、動作速度の改善にもつながる構成である。
本実施形態では、図40に示すように、上記第12の実施形態を2つ接続することにより、全体として8個のトランジスタを直列に接続した構成をなす。本実施形態の等価回路は、図41に示すようになる。
10 ボディ領域
11 第1のトランジスタ
12、22 チャネル領域
13、23 ゲート絶縁膜
14、24 ゲート電極
15、25 ソース領域
16、26 ドレイン領域
17、27、37 引き出し部
18、28、38 接続部
21 第2のトランジスタ
31 第3のトランジスタ
301 シリコン基板
302 絶縁層
303 素子分離膜
304 サイドウォール絶縁膜
305 シリサイド層
306 コンタクト部
307 配線層
Claims (16)
- 第1のトランジスタと第2のトランジスタとが、素子分離領域によって画定された同一の活性領域内に形成された半導体装置であって、
前記活性領域は、前記第1のトランジスタ及び前記第2のトランジスタを形成するボディ領域と、該ボディ領域の電位を接続する接続部と、前記ボディ領域と前記接続部とを接続する引き出し部とを有し、
前記ボディ領域に形成された前記第1のトランジスタ及び前記第2のトランジスタは、それぞれ、チャネル領域と、該チャネル領域上にゲート絶縁膜を介して形成されたゲート電極と、前記チャネル領域を挟むように形成されたソース領域及びドレイン領域とを有し、
前記第1のトランジスタ及び前記第2のトランジスタのソース領域またはドレイン領域は、共通領域に形成されて、同電位になっており、
前記引き出し部は、前記第1のトランジスタ及び前記第2のトランジスタの各チャネル領域から、チャネル方向と直交する方向に、それぞれ分離して延出しており、かつ、前記引き出し部の上には、前記ゲート電極が延出しており、
前記引き出し部の幅は、前記第1のトランジスタ及び前記第2のトランジスタのソース領域及びドレイン領域のコンタクト部間の距離よりも狭く、
前記接続部の幅は、前記引き出し部上に延出した前記ゲート電極のゲート幅以下である、半導体装置。 - 前記引き出し部上に延出した前記ゲート電極のゲート幅は、前記引き出し部に対して、前記ゲート電極のマスクずれ幅を拡大した幅以下である、請求項1に記載の半導体装置。
- 前記接続部の幅は、前記引き出し部の幅と同じ大きさである、請求項1に記載の半導体装置。
- 前記第1のトランジスタ及び前記第2のトランジスタの各引き出し部は、各チャネル領域から、同一方向に延出している、請求項1に記載の半導体装置。
- 前記活性領域は、基板上に形成された絶縁層上の半導体層からなる、請求項1に記載の半導体装置。
- 前記第1のトランジスタ及び前記第2のトランジスタは、同チャネル型のトランジスタで構成されている、請求項1に記載の半導体装置。
- 前記チャネル領域上に形成されたゲート電極の幅と、前記引き出し部上に延出したゲート電極の幅とは、同一である、請求項1に記載の半導体装置。
- 前記活性領域は、第3のトランジスタを形成する第2のボディ領域と、該第2のボディ領域の電位を接続する第2の接続部と、前記第2のボディ領域と前記第2の接続部とを接続する第2の引き出し部とをさらに有し、
前記第2の引き出し部は、前記第3のトランジスタのチャネル領域から、前記第1のトランジスタまたは前記第2のトランジスタの引き出し部と反対方向に延出されており、
前記第2の接続部は、前記第1のトランジスタまたは前記第2のトランジスタの接続部と、共通領域に形成されて、同電位になっている、請求項1に記載の半導体装置。 - 前記第1のトランジスタ及び前記第2のトランジスタの各チャネル領域において、前記引き出し部が延出した側と反対側から、第3の引き出し部が延出しており、
前記引き出し部の上に延出した前記ゲート電極と、前記第3の引き出し部の上に延出した前記ゲート電極とは、同一形状をなしている、請求項1に記載の半導体装置。 - 前記第3の引き出し部には、前記ボディ領域の電位を接続する第3の接続部がさらに接続されている、請求項9に記載の半導体装置。
- 前記チャネル領域上に形成されたゲート電極の幅と、前記引き出し部上に延出したゲート電極の幅とが異なり、かつ、前記チャネル領域上に形成されたゲート電極と、前記引き出し部上に延出したゲート電極との境界が、前記第1のトランジスタ及び前記第2のトランジスタが形成されたボディ領域の境界より外側に位置している場合、前記チャネル領域上に形成されたゲート電極は、前記ボディ領域の境界と直交している、請求項1に記載の半導体装置。
- 前記チャネル領域上に形成されたゲート電極の幅と、前記引き出し部上に延出したゲート電極の幅とが異なり、かつ、前記チャネル領域上に形成されたゲート電極と、前記引き出し部上に延出したゲート電極との境界が、前記第1のトランジスタ及び前記第2のトランジスタが形成されたボディ領域の境界より内側に位置している場合、前記チャネル領域上に形成されたゲート電極と、前記引き出し部上に延出したゲート電極との境界が、135度以上の角度をなしている、請求項1に記載の半導体装置。
- 前記活性領域内に形成された第1のトランジスタ群は、ソース領域とドレイン領域を有し、前記ソース領域とドレイン領域の間にある第1のゲートに接続された第1のトランジスタおよび第2のゲートに接続された第2のトランジスタとを含むトランジスタがソース領域側から直列に接続された構成である、請求項1に記載の半導体装置。
- 前記活性領域内に形成された第1のトランジスタ群はソース領域とドレイン領域を有し、前記ソース領域とドレイン領域の間に第1のゲートに接続された第1のトランジスタおよび第2のゲートに接続された第2のトランジスタとを含むトランジスタがソース領域側から直列に接続され、
前記活性領域内に形成された第2のトランジスタ群は、前記ソース領域と同ノードのソース領域と前記ドレイン領域と同ノードのドレイン領域を有し、前記ソース領域とドレイン領域の間に前記第1のゲートに接続された第3のトランジスタおよび前記第2のゲートに接続された第4のトランジスタとを含むトランジスタがソース領域側から直列に接続された構成である、請求項1に記載の半導体装置。 - 活性領域内に形成された第1のトランジスタ群はソース領域とドレイン領域を有し、前記ソース領域とドレイン領域の間に第1のゲートに接続された第1のトランジスタおよび第2のゲートに接続された第2のトランジスタとを含むトランジスタがソース領域側から直列に接続された構成であって、前記第1のトランジスタおよび前記第2のトランジスタのそれぞれのチャネル電位は、前記ゲートの下層の活性領域からそれぞれの電位を引き出した構成とし、
前記活性領域は、それぞれの前記トランジスタの各チャネル領域から、チャネル方向と直交する方向に、それぞれ分離して延出する引き出し部を備え、
前記引き出し部を含む前記活性領域と、前記第1ゲート及び前記第2ゲートとの間には、ゲート絶縁膜のみを介している、半導体装置。 - 活性領域内に形成された第1のトランジスタ群はソース領域とドレイン領域を有し、前記ソース領域とドレイン領域の間に第1のゲートに接続された第1のトランジスタおよび第2のゲートに接続された第2のトランジスタとを含むトランジスタがソース領域側から直列に接続され、
前記活性領域内に形成された第2のトランジスタ群は、前記ソース領域と同ノードのソース領域と前記ドレイン領域と同ノードのドレイン領域を有し、前記ソース領域とドレイン領域の間に前記第1のゲートに接続された第3のトランジスタおよび前記第2のゲートに接続された第4のトランジスタとを含むトランジスタがソース領域側から直列に接続された構成であって、前記第1のトランジスタおよび前記第2のトランジスタのそれぞれのチャネル電位は前記ゲートの下層の活性領域からそれぞれの電位を引き出した構成とし、
前記活性領域は、それぞれの前記トランジスタの各チャネル領域から、チャネル方向と直交する方向に、それぞれ分離して延出する引き出し部を備え、
前記引き出し部を含む前記活性領域と、前記第1ゲート及び前記第2ゲートとの間には、ゲート絶縁膜のみを介している、半導体装置。
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-
2018
- 2018-07-31 EP EP18843904.6A patent/EP3654385A4/en not_active Withdrawn
- 2018-07-31 WO PCT/JP2018/028741 patent/WO2019031316A1/ja unknown
- 2018-07-31 CN CN201880050013.6A patent/CN110998862A/zh active Pending
- 2018-07-31 JP JP2019535133A patent/JP6955566B2/ja active Active
- 2018-07-31 KR KR1020207004864A patent/KR20200035420A/ko not_active Application Discontinuation
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2020
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JPWO2019031316A1 (ja) | 2020-07-09 |
EP3654385A1 (en) | 2020-05-20 |
EP3654385A4 (en) | 2020-11-18 |
WO2019031316A1 (ja) | 2019-02-14 |
CN110998862A (zh) | 2020-04-10 |
US11217604B2 (en) | 2022-01-04 |
US20200176476A1 (en) | 2020-06-04 |
KR20200035420A (ko) | 2020-04-03 |
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