JP6912194B2 - 電子部品パッケージ及びその製造方法 - Google Patents
電子部品パッケージ及びその製造方法 Download PDFInfo
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- JP6912194B2 JP6912194B2 JP2016251220A JP2016251220A JP6912194B2 JP 6912194 B2 JP6912194 B2 JP 6912194B2 JP 2016251220 A JP2016251220 A JP 2016251220A JP 2016251220 A JP2016251220 A JP 2016251220A JP 6912194 B2 JP6912194 B2 JP 6912194B2
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- electronic component
- wiring portion
- conductive pattern
- frame
- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Description
図1は電子機器システムの例を概略的に示すブロック図である。図面を参照すると、電子機器1000はメインボード1010を収容する。メインボード1010には、チップ関連部品1020、ネットワーク関連部品1030、及びその他の部品1040などが物理的及び/または電気的に連結される。これらは、後述する他の部品とも結合して様々な信号ライン1090を形成する。
図3は電子部品パッケージの一例を概略的に示す断面図である。本実施形態による電子部品パッケージ100は、第1配線部110、フレーム120、電子部品130、及び第2配線部140を主な構成要素として含む。
110、110'、210 第1配線部
111、141、211 絶縁層
112、121、142、212 導電性パターン
113、143、213 導電性ビア
122、222 導電性連結部
123 接着層
120、220 フレーム
130、180 電子部品
131 電極パッド
132 接着性電気連結部
133 接着部
134 封止材
140 第2配線部
150 外部層
151 接続端子
160、161、260、265 サポート
261、266 離型層
262、267 金属薄膜
263 マスク層
264 エッチング阻止層
H 貫通孔
Claims (14)
- 第1絶縁層、前記第1絶縁層に形成された第1導電性パターン、及び前記第1絶縁層を貫通して前記第1導電性パターンと連結された第1導電性ビアを含む第1配線部と、
前記第1配線部上に配置され、第2絶縁層、前記第2絶縁層に形成された第2導電性パターン及び前記第2絶縁層を貫通して前記第2導電性パターンと連結された第2導電性ビアを含む第2配線部と、
前記第1及び第2配線部の間に配置され、一つ以上の貫通孔と前記第1及び第2配線部を電気的に連結する導電性連結部を有するフレームと、
前記貫通孔に囲まれるように配置され、電極パッドを含む電子部品と、
前記第1配線部と前記電子部品の間に配置され、前記電子部品の前記電極パッドと前記第1配線部の前記第1導電性パターンのうち前記電子部品側に形成された導電性パターンを連結する電気連結部と、を含み、
前記第1配線部の前記第1導電性パターンのうち前記電子部品及び前記フレーム側に形成された導電性パターンは、前記第1配線部の前記第1絶縁層に埋め込まれた形態であり、
前記電子部品及び前記フレーム側に形成された前記第1導電性パターンの上面は、前記第1配線部の前記第1絶縁層の最上面と同一平面にあり、
前記第1配線部と前記フレームの間で前記貫通孔の周辺領域に形成されたエッチング阻止層をさらに含む、電子部品パッケージ。 - 前記貫通孔に充填された封止材をさらに含む、請求項1に記載の電子部品パッケージ。
- 前記第1配線部において前記第1絶縁層に埋め込まれた前記第1導電性パターンは、前記電子部品及び前記フレームとは反対側で前記第1絶縁層から露出する導電性パターンよりもピッチが小さい、請求項1または請求項2に記載の電子部品パッケージ。
- 前記電子部品は、これに備えられた前記電極パッドが前記第1配線部に対向するように配置される、請求項1から請求項3の何れか一項に記載の電子部品パッケージ。
- 前記フレームはプリプレグからなり、前記第1及び第2配線部は光硬化性物質を含む、請求項1から請求項4の何れか一項に記載の電子部品パッケージ。
- 前記第1配線部は前記第2配線部よりも厚い、請求項1から請求項5の何れか一項に記載の電子部品パッケージ。
- 前記第1配線部と前記フレームとの間に介在した接着層をさらに含む、請求項1から請求項6の何れか一項に記載の電子部品パッケージ。
- 前記接着層はプリプレグまたは半田レジストである、請求項7に記載の電子部品パッケージ。
- 前記導電性連結部は、前記フレームを貫通するように形成され、前記フレームの上部表面と下部表面から内部に行くほど幅が狭くなる形状を有する、請求項7または請求項8に記載の電子部品パッケージ。
- 前記エッチング阻止層は、金属からなり、前記電子部品と電気的に分離される、請求項1乃至9のいずれか1項に記載の電子部品パッケージ。
- 前記フレームは多層構造を有する、請求項1乃至10のいずれか1項に記載の電子部品パッケージ。
- 前記導電性連結部は、前記多層構造のフレームの各層をそれぞれ貫通するように形成され、前記各層の導電性連結部は、上部から下部に行くほど幅が狭くなる形状を有する、請求項11に記載の電子部品パッケージ。
- 前記第1配線部内に埋め込まれた追加の電子部品をさらに含む、請求項1から請求項12の何れか一項に記載の電子部品パッケージ。
- 前記電子部品は能動素子であり、前記追加の電子部品は受動素子である、請求項13に記載の電子部品パッケージ。
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US20180269156A1 (en) | 2018-09-20 |
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US20190229060A1 (en) | 2019-07-25 |
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US10297553B2 (en) | 2019-05-21 |
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