JP2019080030A - ファン−アウト半導体パッケージ - Google Patents
ファン−アウト半導体パッケージ Download PDFInfo
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- JP2019080030A JP2019080030A JP2018060678A JP2018060678A JP2019080030A JP 2019080030 A JP2019080030 A JP 2019080030A JP 2018060678 A JP2018060678 A JP 2018060678A JP 2018060678 A JP2018060678 A JP 2018060678A JP 2019080030 A JP2019080030 A JP 2019080030A
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- wiring pattern
- semiconductor package
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- sealing material
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Classifications
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Abstract
Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップは、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割を果たすことはできず、外部の物理的または化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3はファン−イン半導体パッケージのパッケージング前後を概略的に示した断面図であり、図4はファン−イン半導体パッケージのパッケージング過程を概略的に示した断面図である。
図7はファン−アウト半導体パッケージの概略的な形態を示した断面図である。
Claims (22)
- キャビティを有し、互いに反対方向に位置する第1面及び第2面を連結する配線構造を含む支持部材と、
前記支持部材の第2面に配置され、前記配線構造と連結された第1再配線層を含む連結部材と、
前記キャビティ内で前記連結部材上に配置され、前記第1再配線層に連結された接続パッドを有する半導体チップと、
前記キャビティに位置する前記半導体チップを封止し、且つ前記支持部材の第1面を覆う封止材と、
前記封止材に埋め込まれ、表面が露出した配線パターン、及び前記封止材を貫通して前記配線構造と前記配線パターンを連結する連結用ビアを有する第2再配線層と、を含む、半導体パッケージ。 - 前記連結用ビアは、前記配線パターンを貫通して形成される、請求項1に記載の半導体パッケージ。
- 前記配線パターンはオープン領域を有し、前記連結用ビアは前記配線パターンの前記オープン領域に位置する、請求項2に記載の半導体パッケージ。
- 前記連結用ビアは、中央部がリセスした上面を有する、請求項2または3に記載の半導体パッケージ。
- 前記連結用ビアは、前記配線構造に接する領域の幅に比べて前記配線パターンに接する領域の幅が大きい、請求項3または4に記載の半導体パッケージ。
- 前記第2再配線層の露出した表面は、前記封止材の表面と実質的に共平面を有する、請求項1から5のいずれか一項に記載の半導体パッケージ。
- 互いに反対方向に位置する第1面及び第2面を有し、前記第2面が前記封止材に接する絶縁層をさらに含み、
前記第2再配線層は、前記絶縁層の第1面に埋め込まれた第1配線パターンと、前記絶縁層の第2面に配置され、前記封止材に埋め込まれた第2配線パターンと、を含む、請求項1から6のいずれか一項に記載の半導体パッケージ。 - 前記第2再配線層は、前記絶縁層と前記封止材を貫通し、前記第1及び第2配線パターンと前記配線構造に連結される第1連結用ビアを含む、請求項7に記載の半導体パッケージ。
- 前記第2再配線層は、前記絶縁層と前記封止材を貫通し、前記第2配線パターンと前記配線構造に連結される第2連結用ビアを含み、
前記第2連結用ビアは、前記第1配線パターンと直接接触しない、請求項7または8に記載の半導体パッケージ。 - 前記第2再配線層は、前記絶縁層を貫通して前記第1配線パターンと前記第2配線パターンを連結する層間ビアを含む、請求項7から9のいずれか一項に記載の半導体パッケージ。
- 前記層間ビアは、前記第2配線パターンに接する部分の幅が、前記第1配線パターンに接する部分の幅に比べて大きい、請求項10に記載の半導体パッケージ。
- 前記層間ビアは、前記第2配線パターンと一体化された構造を有する、請求項11に記載の半導体パッケージ。
- 前記第1再配線層は複数の第1パッド領域を有し、
前記複数の第1パッド領域を露出する開口を有する第1パッシベーション層が前記封止材の表面にさらに配置される、請求項1から6のいずれか一項に記載の半導体パッケージ。 - 前記複数の第1パッド領域の一部が、前記半導体チップと重なる領域に延びる、請求項13に記載の半導体パッケージ。
- 前記第2再配線層は複数の第2パッド領域を有し、
前記複数の第2パッド領域を露出する開口を有する第2パッシベーション層が前記連結部材の下面にさらに配置される、請求項1から14のいずれか一項に記載の半導体パッケージ。 - キャビティを有し、互いに反対方向に位置する第1面及び第2面を連結する配線構造を含む支持部材と、
前記支持部材の第2面に配置され、前記配線構造と連結された第1再配線層を含む連結部材と、
前記キャビティ内で前記連結部材上に配置され、前記第1再配線層に連結された接続パッドを有する半導体チップと、
前記キャビティに位置する前記半導体チップを封止し、且つ前記支持部材の第1面を覆う封止材と、
互いに反対方向に位置する第1面及び第2面を有し、前記第2面が前記封止材に接する絶縁層、前記絶縁層の第1面に埋め込まれた第1配線パターン、前記絶縁層の第2面に配置され、前記封止材に埋め込まれた第2配線パターン、及び前記絶縁層と前記封止材を貫通し、前記第1及び第2配線パターンの少なくとも一つと前記配線構造を連結する連結用ビアを有する第2再配線層と、を含む、半導体パッケージ。 - 前記連結用ビアは、
前記絶縁層と前記封止材を貫通し、前記第1及び第2配線パターンと前記配線構造に連結される第1連結用ビアと、
前記絶縁層と前記封止材を貫通し、前記第2配線パターンと前記配線構造に連結され、前記第1配線パターンと直接接触しない第2連結用ビアと、を含む、請求項16に記載の半導体パッケージ。 - 前記第2再配線層は、前記絶縁層を貫通して前記第1配線パターンと第2配線パターンを連結し、前記第2配線パターンと一体化された層間ビアをさらに含み、
前記層間ビアは、前記第2配線パターンに接する部分の幅が、前記第1配線パターンに接する部分の幅に比べて大きい、請求項16または17に記載の半導体パッケージ。 - 上面と下面を連結する配線構造を含む支持部材にキャビティを形成する段階と、
前記支持部材の前記キャビティに半導体チップを配置する段階と、
前記支持部材及び前記半導体チップ上に、且つ前記キャビティ内に封止材を形成する段階と、
前記封止材に上部配線パターンを埋め込む段階と、
前記封止材に、前記上部配線パターンを前記支持部材の上面と連結する一つ以上の孔を形成する段階と、
前記封止材における前記一つ以上の孔に導電性ビアを形成する段階と、を含む、半導体パッケージの製造方法。 - 前記封止材を硬化させる前に、前記上部配線パターンを前記封止材の上面に積層する段階を行うことにより、前記上部配線パターンが前記封止材に埋め込まれるようにする、請求項19に記載の半導体パッケージの製造方法。
- 前記積層する段階は、
仮支持体の離型層(release layer)上に配線パターンを形成する段階と、
前記配線パターンが前記封止材に相対して転写されるように、前記封止材の上面に前記仮支持体を積層する段階と、
前記仮支持体を除去する段階と、を含む、請求項20に記載の半導体パッケージの製造方法。 - 前記配線パターンを形成する段階は、
前記仮支持体の離型層上に第1配線層を形成する段階と、
前記第1配線層上に絶縁層を形成する段階と、
前記絶縁層上に第2配線層を形成する段階と、を含み、
前記第1及び第2配線層は、ビアにより前記絶縁層を介して連結され、少なくとも前記第2配線層は前記封止材に埋め込まれるようにする、請求項21に記載の半導体パッケージの製造方法。
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KR101922884B1 (ko) | 2018-11-28 |
CN109712952B (zh) | 2023-06-13 |
US10916495B2 (en) | 2021-02-09 |
US20190131224A1 (en) | 2019-05-02 |
CN109712952A (zh) | 2019-05-03 |
US20210151370A1 (en) | 2021-05-20 |
US11699643B2 (en) | 2023-07-11 |
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JP6668403B2 (ja) | 2020-03-18 |
TW201917858A (zh) | 2019-05-01 |
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