JP6669330B2 - 電子部品内蔵型印刷回路基板及びその製造方法 - Google Patents
電子部品内蔵型印刷回路基板及びその製造方法 Download PDFInfo
- Publication number
- JP6669330B2 JP6669330B2 JP2015252477A JP2015252477A JP6669330B2 JP 6669330 B2 JP6669330 B2 JP 6669330B2 JP 2015252477 A JP2015252477 A JP 2015252477A JP 2015252477 A JP2015252477 A JP 2015252477A JP 6669330 B2 JP6669330 B2 JP 6669330B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- circuit board
- printed circuit
- layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010410 layer Substances 0.000 claims description 135
- 238000000034 method Methods 0.000 claims description 30
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000002335 surface treatment layer Substances 0.000 claims description 11
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000004593 Epoxy Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229920001187 thermosetting polymer Polymers 0.000 claims description 5
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 claims description 4
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000003365 glass fiber Substances 0.000 claims description 4
- 229910003471 inorganic composite material Inorganic materials 0.000 claims description 4
- 229920003192 poly(bis maleimide) Polymers 0.000 claims description 4
- 239000002861 polymer material Substances 0.000 claims description 4
- 229920001169 thermoplastic Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 3
- 239000000126 substance Substances 0.000 claims 2
- 230000008569 process Effects 0.000 description 19
- 238000007747 plating Methods 0.000 description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229920003002 synthetic resin Polymers 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002952 polymeric resin Substances 0.000 description 2
- BWHMMNNQKKPAPP-UHFFFAOYSA-L potassium carbonate Chemical compound [K+].[K+].[O-]C([O-])=O BWHMMNNQKKPAPP-UHFFFAOYSA-L 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 102000004528 Mannose-Binding Protein-Associated Serine Proteases Human genes 0.000 description 1
- 108010042484 Mannose-Binding Protein-Associated Serine Proteases Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910000027 potassium carbonate Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
Description
先ず、本発明の一実施例に係る部品内蔵型印刷回路基板について、図面を参照して具体的に説明する。この際、参照される図面に記載されていない図面符号は、同一の構成を示す他の図面での図面符号であり得る。
図5aから図5hは、本発明の第1実施例に係る電子部品内蔵型印刷回路基板の製造方法における工程図である。
111、311…シード層
120、320、420、520、620…回路層
130、330、430、530、630…電子部品
131、331、431、531、631…接続端子
140、340,440,540…第1絶縁層
150…第2絶縁層
160、345…第2ドライフィルム
170、360、460…外部回路層
180、370、470、570…ソルダレジスト層
190、380…表面処理層
195、390、490、590、695…金属バンプ
491、591…第1素子
495、595…第2素子
Claims (18)
- 絶縁層の一面に接続端子が露出するように埋め込まれた電子部品と、
前記絶縁層の一面に、前記電子部品の露出した接続端子に形成された金属バンプと、
前記絶縁層の両側に形成されたソルダレジスト層と、
前記電子部品と前記ソルダレジスト層との間に介在された接着層と、
を含む電子部品内蔵型印刷回路基板。 - 前記絶縁層の一面に埋め込まれて形成された回路層をさらに含む請求項1に記載の電子部品内蔵型印刷回路基板。
- 前記回路層は、前記電子部品の接続端子が露出した前記絶縁層の同一面上に埋め込まれて形成される請求項2に記載の電子部品内蔵型印刷回路基板。
- 前記ソルダレジスト層には、前記電子部品の接続端子が露出するように開口部が形成された請求項1から請求項3のいずれか1項に記載の電子部品内蔵型印刷回路基板。
- 前記電子部品の露出された前記接続端子上に、表面処理層が形成された請求項4に記載の電子部品内蔵型印刷回路基板。
- 前記絶縁層は、熱硬化性または熱可塑性高分子物質、セラミック、有機無機複合素材、ガラス繊維含浸(prepreg)、FR−4、BT(Bismaleimide Triazine)、ABF(Ajinomoto Build up Film)エポキシ系絶縁樹脂のうちのいずれか1種により形成された請求項1から請求項5のいずれか1項に記載の電子部品内蔵型印刷回路基板。
- 前記絶縁層の他面に積層されたビルドアップ層をさらに含む請求項1から請求項6のいずれか1項に記載の電子部品内蔵型印刷回路基板。
- 印刷回路基板及び第1素子を含み、
前記印刷回路基板は、
絶縁層の一面に接続端子が露出するように埋め込まれた電子部品と、
前記絶縁層の一面に前記電子部品の露出した接続端子に形成された金属バンプと、
前記絶縁層の両側に形成されたソルダレジスト層と、
前記電子部品と前記ソルダレジスト層との間に介在された接着層と、を含み、
前記第1素子は、
前記印刷回路基板の前記金属バンプに接続して実装される、半導体パッケージ。 - 前記第1素子上に形成される第2素子をさらに含み、前記第2素子は、前記印刷回路基板の回路層とワイヤボンディングにより接続する請求項8に記載の半導体パッケージ。
- (A)キャリア部材上に埋め込み用回路パターンを形成するステップと、
(B)前記回路パターンが形成された素子実装領域に電子部品を実装するステップと、
(C)前記電子部品が埋め込まれるように絶縁層を形成するステップと、
(D)前記キャリア部材を除去するステップと、
(E)前記キャリア部材を除去した積層体の両面に回路層を形成し、電子部品の一側の接続端子を露出させるステップと、
(F)前記電子部品の露出した接続端子上に金属バンプ形成するステップと、
を含む電子部品内蔵型印刷回路基板の製造方法。 - 前記ステップ(A)は、
(A−1)前記キャリア部材上に第1ドライフィルムを所定パターンにエッチングした後に、ラミネーションするステップと、
(A−2)前記エッチングされた所定パターンに金属物質を塗布するステップと、
(A−3)第1ドライフィルムを除去した後、電子部品の実装される領域に接着層を形成するステップと、を含む請求項10に記載の電子部品内蔵型印刷回路基板の製造方法。 - 前記ステップ(C)は、
前記電子部品の側面を囲むように前記キャリア部材上に第1絶縁層を形成するステップと、
前記第1絶縁層上に第2絶縁層を形成するステップと、を含む請求項10又は請求項11に記載の電子部品内蔵型印刷回路基板の製造方法。 - 前記絶縁層は、熱硬化性または熱可塑性高分子物質、セラミック、有機無機複合素材、ガラス繊維含浸(prepreg)、FR−4、BT(Bismaleimide Triazine)、ABF(Ajinomoto Build up Film)エポキシ系絶縁樹脂のうちのいずれか1種により形成される請求項10又は請求項11に記載の電子部品内蔵型印刷回路基板の製造方法。
- 前記ステップ(E)は、
(E−1)前記キャリア部材を除去した後、前記絶縁層に電子部品の接続端子が露出するようにマイクロビアホールを含むビアホールを加工するステップと、
(E−2)前記絶縁層の一面及び他面に第2ドライフィルムを形成し、前記ビアホールが露出するようにパターニングした後にラミネーションするステップと、
(E−3)前記露出したビアホールに金属物質を充填するステップと、を含む請求項10から請求項13のいずれか1項に記載の電子部品内蔵型印刷回路基板の製造方法。 - 前記露出した電子部品の接続端子上に、表面処理層を形成するステップをさらに含む請求項10から請求項14のいずれか1項に記載の電子部品内蔵型印刷回路基板の製造方法。
- 前記絶縁層の他面にビルドアップ層を積層するステップをさらに含む請求項10又は請求項11に記載の電子部品内蔵型印刷回路基板の製造方法。
- 印刷回路基板を形成するステップと、
前記印刷回路基板に第1素子を実装するステップと、を含み、
前記印刷回路基板を形成するステップは、
キャリア部材上に埋め込み用回路パターンを形成するステップと、
前記回路パターンが形成された素子実装領域に電子部品を実装するステップと、
前記電子部品が埋め込まれるように絶縁層を形成するステップと、
前記キャリア部材を除去するステップと、
前記キャリア部材を除去した積層体の両面に回路層を形成し、電子部品の一側の接続端子を露出させるステップと、
前記電子部品の露出した接続端子上に金属バンプを形成するステップと、を含み、
前記第1素子が、前記印刷回路基板の前記金属バンプに接続される、半導体パッケージの製造方法。 - 前記第1素子上に第2素子を形成するステップをさらに含み、前記第2素子は、前記印刷回路基板の回路層とワイヤボンディングにより接続する請求項17に記載の半導体パッケージの製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2015-0010658 | 2015-01-22 | ||
KR1020150010658A KR102356810B1 (ko) | 2015-01-22 | 2015-01-22 | 전자부품내장형 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016134621A JP2016134621A (ja) | 2016-07-25 |
JP6669330B2 true JP6669330B2 (ja) | 2020-03-18 |
Family
ID=56434362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015252477A Active JP6669330B2 (ja) | 2015-01-22 | 2015-12-24 | 電子部品内蔵型印刷回路基板及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10779414B2 (ja) |
JP (1) | JP6669330B2 (ja) |
KR (1) | KR102356810B1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017152536A (ja) * | 2016-02-24 | 2017-08-31 | イビデン株式会社 | プリント配線板及びその製造方法 |
KR102163059B1 (ko) | 2018-09-07 | 2020-10-08 | 삼성전기주식회사 | 연결구조체 내장기판 |
WO2020121813A1 (ja) * | 2018-12-13 | 2020-06-18 | 株式会社村田製作所 | 樹脂基板、電子機器、および樹脂基板の製造方法 |
KR102170904B1 (ko) * | 2018-12-21 | 2020-10-29 | 주식회사 심텍 | 수동 소자를 구비하는 인쇄회로기판 및 그 제조 방법 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3375555B2 (ja) * | 1997-11-25 | 2003-02-10 | 松下電器産業株式会社 | 回路部品内蔵モジュールおよびその製造方法 |
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP3792445B2 (ja) | 1999-03-30 | 2006-07-05 | 日本特殊陶業株式会社 | コンデンサ付属配線基板 |
CN101232775B (zh) * | 1999-09-02 | 2010-06-09 | 伊比登株式会社 | 印刷布线板及其制造方法 |
JP4034107B2 (ja) * | 2002-04-17 | 2008-01-16 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2005303260A (ja) * | 2004-03-19 | 2005-10-27 | Alps Electric Co Ltd | 転写配線の製造方法 |
JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP2006019441A (ja) * | 2004-06-30 | 2006-01-19 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
TWI340450B (en) * | 2007-08-28 | 2011-04-11 | Unimicron Technology Corp | Packaging substrate structure with capacitor embedded therein and method for fabricating the same |
US7911040B2 (en) * | 2007-12-27 | 2011-03-22 | Stats Chippac Ltd. | Integrated circuit package with improved connections |
JP5395360B2 (ja) * | 2008-02-25 | 2014-01-22 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
JP5262188B2 (ja) * | 2008-02-29 | 2013-08-14 | 富士通株式会社 | 基板 |
JP2009224616A (ja) * | 2008-03-17 | 2009-10-01 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板及びその製造方法、及び半導体装置 |
KR100997199B1 (ko) * | 2008-07-21 | 2010-11-29 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 제조방법 |
JPWO2010024233A1 (ja) * | 2008-08-27 | 2012-01-26 | 日本電気株式会社 | 機能素子を内蔵可能な配線基板及びその製造方法 |
JP2010171413A (ja) * | 2008-12-26 | 2010-08-05 | Ngk Spark Plug Co Ltd | 部品内蔵配線基板の製造方法 |
US9093391B2 (en) * | 2009-09-17 | 2015-07-28 | Stats Chippac Ltd. | Integrated circuit packaging system with fan-in package and method of manufacture thereof |
US8796561B1 (en) * | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
JP2011159695A (ja) * | 2010-01-29 | 2011-08-18 | Hitachi Chem Co Ltd | 半導体素子搭載用パッケージ基板及びその製造方法 |
US8314480B2 (en) | 2010-02-08 | 2012-11-20 | Fairchild Semiconductor Corporation | Stackable semiconductor package with embedded die in pre-molded carrier frame |
WO2011114774A1 (ja) * | 2010-03-18 | 2011-09-22 | 日本電気株式会社 | 半導体素子内蔵基板およびその製造方法 |
JP5001395B2 (ja) * | 2010-03-31 | 2012-08-15 | イビデン株式会社 | 配線板及び配線板の製造方法 |
KR101095161B1 (ko) * | 2010-10-07 | 2011-12-16 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 |
KR101283821B1 (ko) * | 2011-05-03 | 2013-07-08 | 엘지이노텍 주식회사 | 인쇄회로기판의 제조 방법 |
JP6009228B2 (ja) * | 2012-05-30 | 2016-10-19 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
JP6029342B2 (ja) | 2012-06-15 | 2016-11-24 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP6166878B2 (ja) * | 2012-08-30 | 2017-07-19 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
KR101420514B1 (ko) * | 2012-10-23 | 2014-07-17 | 삼성전기주식회사 | 전자부품들이 구비된 기판구조 및 전자부품들이 구비된 기판구조의 제조방법 |
KR101483825B1 (ko) * | 2012-12-04 | 2015-01-16 | 삼성전기주식회사 | 전자부품 내장기판 및 그 제조방법 |
KR101420537B1 (ko) * | 2012-12-14 | 2014-07-16 | 삼성전기주식회사 | 전자부품 내장기판 및 전자부품 내장기판의 제조방법 |
JP2014232812A (ja) * | 2013-05-29 | 2014-12-11 | イビデン株式会社 | プリント配線板およびその製造方法 |
JP2015106610A (ja) * | 2013-11-29 | 2015-06-08 | イビデン株式会社 | 電子部品内蔵基板、電子部品内蔵基板の製造方法 |
JP6242231B2 (ja) * | 2014-02-12 | 2017-12-06 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP6334962B2 (ja) * | 2014-03-05 | 2018-05-30 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
-
2015
- 2015-01-22 KR KR1020150010658A patent/KR102356810B1/ko active IP Right Grant
- 2015-12-24 JP JP2015252477A patent/JP6669330B2/ja active Active
-
2016
- 2016-01-21 US US15/003,400 patent/US10779414B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR20160090626A (ko) | 2016-08-01 |
KR102356810B1 (ko) | 2022-01-28 |
US20160219710A1 (en) | 2016-07-28 |
JP2016134621A (ja) | 2016-07-25 |
US10779414B2 (en) | 2020-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100965339B1 (ko) | 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
WO2010007704A1 (ja) | フレックスリジッド配線板及び電子デバイス | |
JP6711509B2 (ja) | プリント回路基板、半導体パッケージ及びその製造方法 | |
US10098243B2 (en) | Printed wiring board and semiconductor package | |
US20180237934A1 (en) | Printed wiring board, semiconductor package and method for manufacturing printed wiring board | |
JP2011258772A (ja) | 配線基板及びその製造方法並びに半導体装置 | |
JP2012109621A (ja) | 電子部品内装型プリント基板 | |
KR20150092881A (ko) | 인쇄회로기판, 패키지 기판 및 이의 제조 방법 | |
KR20100123399A (ko) | 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
JPWO2009101723A1 (ja) | 電子部品内蔵基板の製造方法 | |
JP6880429B2 (ja) | 素子内蔵型印刷回路基板及びその製造方法 | |
JP6669330B2 (ja) | 電子部品内蔵型印刷回路基板及びその製造方法 | |
JP2018026437A (ja) | 配線基板及びその製造方法 | |
JP2008124247A (ja) | 部品内蔵基板及びその製造方法 | |
JP2003188314A (ja) | 素子内蔵基板の製造方法および素子内蔵基板 | |
JP2014150091A (ja) | 配線基板およびその製造方法 | |
US20150156882A1 (en) | Printed circuit board, manufacturing method thereof, and semiconductor package | |
KR101109287B1 (ko) | 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
JP4899409B2 (ja) | 多層プリント配線基板及びその製造方法 | |
KR100704911B1 (ko) | 전자소자 내장형 인쇄회로기판 및 그 제조방법 | |
KR101580472B1 (ko) | 회로기판 제조방법 | |
KR102281458B1 (ko) | 소자 내장형 인쇄회로기판, 반도체 패키지 및 그 제조방법 | |
JP4451238B2 (ja) | 部品内蔵基板の製造方法及び部品内蔵基板 | |
KR101119306B1 (ko) | 회로기판의 제조방법 | |
KR101543031B1 (ko) | 인쇄회로기판 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180829 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20190822 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190903 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191108 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200128 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200212 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6669330 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |