JP6632302B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP6632302B2
JP6632302B2 JP2015197091A JP2015197091A JP6632302B2 JP 6632302 B2 JP6632302 B2 JP 6632302B2 JP 2015197091 A JP2015197091 A JP 2015197091A JP 2015197091 A JP2015197091 A JP 2015197091A JP 6632302 B2 JP6632302 B2 JP 6632302B2
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Japan
Prior art keywords
layer
wiring
wiring layer
insulating layer
semiconductor chip
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Active
Application number
JP2015197091A
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English (en)
Japanese (ja)
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JP2017069524A5 (enExample
JP2017069524A (ja
Inventor
豊明 酒井
豊明 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015197091A priority Critical patent/JP6632302B2/ja
Priority to US15/244,197 priority patent/US9911695B2/en
Publication of JP2017069524A publication Critical patent/JP2017069524A/ja
Publication of JP2017069524A5 publication Critical patent/JP2017069524A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H10W70/6525—Cross-sectional shapes for securing the interconnections to the substrate, e.g. to prevent peeling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
JP2015197091A 2015-10-02 2015-10-02 配線基板及びその製造方法 Active JP6632302B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015197091A JP6632302B2 (ja) 2015-10-02 2015-10-02 配線基板及びその製造方法
US15/244,197 US9911695B2 (en) 2015-10-02 2016-08-23 Wiring board including multiple wiring layers that are different in surface roughness

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015197091A JP6632302B2 (ja) 2015-10-02 2015-10-02 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2017069524A JP2017069524A (ja) 2017-04-06
JP2017069524A5 JP2017069524A5 (enExample) 2018-10-04
JP6632302B2 true JP6632302B2 (ja) 2020-01-22

Family

ID=58448046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015197091A Active JP6632302B2 (ja) 2015-10-02 2015-10-02 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US9911695B2 (enExample)
JP (1) JP6632302B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2573137T3 (es) * 2012-09-14 2016-06-06 Atotech Deutschland Gmbh Método de metalización de sustratos de célula solar
JP2018006391A (ja) * 2016-06-28 2018-01-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP7137292B2 (ja) * 2019-03-15 2022-09-14 京セラ株式会社 配線基板およびその製造方法
JP2022119418A (ja) * 2021-02-04 2022-08-17 イビデン株式会社 配線基板及び配線基板の製造方法
KR20220154555A (ko) * 2021-05-13 2022-11-22 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
FR3133266A1 (fr) * 2022-03-04 2023-09-08 Jet Metal Technologies Composant a motif(s) electro-conducteur(s) pour dispositif electrique, radioelectrique ou electronique, et dispositif comprenant un tel composant
JP2024098871A (ja) * 2023-01-11 2024-07-24 イビデン株式会社 配線基板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4108643B2 (ja) * 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ
JP2008091638A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
JP5203108B2 (ja) * 2008-09-12 2013-06-05 新光電気工業株式会社 配線基板及びその製造方法
JP5580374B2 (ja) * 2012-08-23 2014-08-27 新光電気工業株式会社 配線基板及びその製造方法
JP2014229698A (ja) * 2013-05-21 2014-12-08 イビデン株式会社 配線板及び配線板の製造方法
JP6266907B2 (ja) * 2013-07-03 2018-01-24 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP6131135B2 (ja) 2013-07-11 2017-05-17 新光電気工業株式会社 配線基板及びその製造方法
JP6220799B2 (ja) * 2015-02-03 2017-10-25 新光電気工業株式会社 配線基板及びその製造方法

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Publication number Publication date
US20170098600A1 (en) 2017-04-06
JP2017069524A (ja) 2017-04-06
US9911695B2 (en) 2018-03-06

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