JP6577240B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP6577240B2 JP6577240B2 JP2015102567A JP2015102567A JP6577240B2 JP 6577240 B2 JP6577240 B2 JP 6577240B2 JP 2015102567 A JP2015102567 A JP 2015102567A JP 2015102567 A JP2015102567 A JP 2015102567A JP 6577240 B2 JP6577240 B2 JP 6577240B2
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- oxide semiconductor
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- transistor
- insulating film
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- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/772—Field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
酸素欠損が含まれている酸化物半導体膜を用いたトランジスタは、しきい値電圧がマイナス方向に変動しやすく、ノーマリーオン特性となりやすい。これは、酸化物半導体膜に含まれる酸素欠損に起因して電荷が生じてしまい、低抵抗化するためである。また、酸化物半導体膜に酸素欠損が含まれると、経時変化やストレス試験(代表的には、光ゲートBT(Bias−Temperature)ストレス試験等)により、トランジスタの電気特性、代表的にはしきい値電圧が変動してしまうという問題がある。そこで、本実施の形態では、しきい値電圧の変動が少なく、信頼性の高い半導体装置およびその作製方法について説明する。また、電気特性の優れた半導体装置およびその作製方法について説明する。
本実施の形態では、トップゲート構造のトランジスタの作製方法について説明する。
次に、半導体装置の作製方法について、図3および図4を用いて説明する。
ここで、バンド構造について説明する。バンド構造は、理解を容易にするためゲート絶縁膜105、酸化物半導体膜107、酸化物半導体膜111、酸化物半導体膜115およびゲート絶縁膜117の伝導帯下端のエネルギー(Ec)を示す。
図1に示すトランジスタ100に含まれる酸化物半導体膜115およびゲート絶縁膜117の形状の異なるトランジスタについて、図6を用いて説明する。
図1に示すトランジスタ100に含まれる一対の電極113a、113bの形状の異なるトランジスタについて、図7を用いて説明する。
図1に示すトランジスタ100に含まれる酸化物半導体膜111の形状の異なるトランジスタについて、図10を用いて説明する。
図1に示すトランジスタ100に含まれるゲート電極の形状の異なるトランジスタについて、図11を用いて説明する。
図1に示すトランジスタ100の変形例について、図43を用いて説明する。
トランジスタに含まれる一対の電極の変形例について、図44を用いて説明する。ここでは、図1(B)において、破線で囲まれた領域の拡大図を図44に示す。
本実施の形態では、実施の形態1と異なる方法で、酸化物半導体膜に含まれる酸素欠損を低減する方法について、説明する。ここでは、一対の電極113a、113b上の酸化物半導体膜に酸素を添加する点が実施の形態1と異なる。
実施の形態2と異なる方法で酸化物半導体膜114に酸素を添加する方法について、図14を用いて説明する。
図1に示すトランジスタ100と比較して、酸化物半導体膜の積層構造の異なるトランジスタについて、図15を用いて説明する。
本実施の形態では、トランジスタに含まれる酸化物半導体膜、及び該酸化物半導体膜に接する酸化物絶縁膜に含まれる欠陥と、トランジスタ特性の劣化について説明する。
<1. はじめに、酸化物半導体膜に接する酸化物絶縁膜に含まれる窒素酸化物(以下、NOxと表記する(x=0以上2以下、好ましくは1以上2以下))について説明する。
はじめに、固体中の点欠陥の遷移レベルを用いて説明する。遷移レベルとは、ギャップ内に準位を形成する不純物あるいは欠陥(以下、欠陥Dと記す。)の荷電状態を説明する概念であり、欠陥の形成エネルギーから算出される。すなわち、遷移レベルは、ドナー準位やアクセプター準位と類似の概念である。
上記遷移レベルの計算結果を受け、以下ではNO2分子のESRシグナルを計算にて求めた。また、ここではSiO2内のO原子にN原子が置換したモデルについても同様の検証を行った。
以下では、上記の結果をもとに、プラスゲートBTストレス試験(+GBT)を行ったときの、トランジスタのしきい値電圧がプラスシフトする現象について、そのメカニズムを考察する。
<酸化物半導体の構造>
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
本実施の形態では、本発明の一態様であるトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を、図面を用いて説明する。
データの書き込みは、トランジスタ200をオンとした際に、ビット線である配線BLの電位をデータに応じたものにすることでおこなわれる。基本的にはDRAMへのデータの書き込み方法と同様である。トランジスタ200は、トランジスタ750やトランジスタ770とはしきい値等が異なるので、ここでは、トランジスタ200をオンとするときには、そのゲートの電位(配線WWLの電位)をVOS_H、トランジスタ200をオフとするときには、そのゲートの電位をVOS_L、とする、なお、VOS_L=GND(<VDD)でもよい。
データの保持の際には、トランジスタ200をオフとする。図27の時間T3から時間T4が、電源が遮断された状態でのデータを保持している期間(スタンバイ期間)を示す。なお、スタンバイ期間では、すべての配線の電位が同一(ここでは、GND)となる。ここで、ノードFNの電位がGNDより高かった場合には、ノードFNの電位は徐々に低下する。
データを読み出す動作は、配線BLと配線SLの電位を異なるものとし、その後、トランジスタ770をオンとすることで、トランジスタ750のソースとドレイン間に電流が流れるか否かで判断する。ノードFNの電位により、トランジスタ750の導通状態が異なることで、書き込まれていたデータを判断できる。
本実施の形態では、本発明の一態様の表示装置の構成例について説明する。
図28(A)は、本発明の一態様の表示装置の上面図であり、図28(B)は、本発明の一態様の表示装置の画素に液晶素子を適用する場合に用いることができる画素回路を説明するための回路図である。また、図28(C)は、本発明の一態様の表示装置の画素に有機EL素子を適用する場合に用いることができる画素回路を説明するための回路図である。
また、画素の回路構成の一例を図28(B)に示す。ここでは、VA型液晶表示装置の画素に適用することができる画素回路を示す。
画素の回路構成の他の一例を図28(C)に示す。ここでは、有機EL素子を用いた表示装置の画素構造を示す。
本実施の形態では、本発明の一態様の半導体装置を適用した表示モジュールについて、図29を用いて説明を行う。
本実施の形態では、本発明の一態様に係る半導体装置を用いた電子機器の一例について説明する。
本実施例では、試料A1および試料A2をそれぞれ作製した。
図33(A)乃至図33(D)を用いて、試料A1の作製方法を説明する。
図33(E)乃至図33(I)を用いて、試料A2の作製方法を説明する。なお、試料A2は、試料A1と比較して、基板の材料が異なる。また、酸化シリコン膜の成膜温度が異なる。また、酸素原子イオンを酸化シリコン膜に添加することが異なる。
試料A1及び試料A2についてESR測定を行った。ここでは、下記の条件でESR測定を行った。試料A1は測定温度を10Kとし、9.45GHzの高周波電力を0.05mWとし、磁場の向きは作製した試料の膜表面と平行とした。試料A2は測定温度を100Kとし、9.15GHzの高周波電力を4mWとし、磁場の向きは作製した試料の膜表面と平行とした。なお、測定温度が100Kの際のNOxに起因するシグナルのスピン密度の検出下限は1.0×1017spins/cm3であった。スピン数が小さいほど膜中欠損が少ないといえる。
図35(A)及び図35(B)を用いて、試料A3の作製方法を説明する。
試料A4は、試料A3と成膜温度が異なる条件を用いて、酸化シリコン膜323を形成した。
図35(C)乃至図35(F)を用いて、試料A5の作製方法を説明する。試料A5は、試料A3と比較して、第1のIGZO膜に酸素原子イオンを添加する点が異なる。
試料A6は、試料A5と成膜温度が異なる条件を用いて、酸化シリコン膜323を形成した。
試料A3乃至試料A6についてESR測定を行った。ここでは、下記の条件でESR測定を行った。測定温度を10Kとし、9.55GHzの高周波電力を0.1mWとし、磁場の向きは作製した試料の膜表面と平行とした。なお、測定温度が10Kの際のNOxに起因するシグナルのスピン密度の検出下限は8.7×1015spins/cm3であった。
本実施例では、試料B1乃至試料B5をそれぞれ作製した。
シリコンウェハを加熱してシリコンウェハの表面に厚さ100nmの酸化シリコン膜を形成した。次に、酸化シリコン膜上に、厚さ100nmの酸化シリコン膜を形成した。
試料B2は、試料B1の酸化シリコン膜の成膜温度を400℃とする条件を用いて、作製した。
試料B3は、試料B1の酸化シリコン膜の成膜温度を450℃とする条件を用いて、作製した。
試料B4は、試料B1の酸化シリコン膜の成膜温度を500℃とする条件を用いて、作製した。
試料B5は、試料B1の酸化シリコン膜の成膜温度を550℃とする条件を用いて、作製した。
次に、試料B1乃至試料B5についてTDS分析を行った。
次に、試料B1乃至試料B5に含まれる酸化シリコン膜について、SIMS分析を行った。なお、ここでは、シリコンウェハを加熱して酸化シリコン膜を形成することをせず、試料B1乃至試料B5のいずれかの条件を用いて、シリコンウェハ上に厚さ100nmの酸化シリコン膜を形成した。試料B1、試料B2、試料B3、試料B4、試料B5の条件を用いて酸化シリコン膜を形成した試料を、それぞれ試料B1a、試料B2a、試料B3a、試料B4a、試料B5aとする。なお、各試料において、シリコンウェハ(Si)から、酸化シリコン膜(SiON)へ向かって、窒素の濃度を測定した。試料B1a乃至試料B5aの測定結果を図39に示す。
はじめに、トランジスタを含む試料C1の作製工程について説明する。本実施例では、図3、図6、および図7を参照して、トランジスタの作製方法を説明する。
試料C2は、試料C1の酸化物半導体膜109を形成した後の加熱処理温度を550℃とする条件を用いて、トランジスタを作製した。即ち、試料C2においては、絶縁膜104の成膜温度より高い温度で加熱処理を行った。
次に、トランジスタの電気特性を測定した。はじめに、ストレス試験を行う前の電気特性(以下、初期特性と示す。)を測定した。ここでは、ソース−ドレイン間電圧(以下、ドレイン電圧という。)を0.1Vまたは1.8Vとし、ソース−ゲート間電圧(以下、ゲート電圧という。)を−3Vから+3Vまで変化させたときのソース−ドレイン間電流(以下、ドレイン電流という。)の変化特性、すなわちVg−Id特性を測定した。
Claims (9)
- 基板上に第1のゲート電極を形成し、
前記第1のゲート電極と接する領域を有する、第1の絶縁膜を、前記基板の温度が450℃以上前記基板の歪み点未満となるように加熱しながら形成し、
前記第1の絶縁膜と接する領域を有する、第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜に酸素を添加し、
前記酸素が添加された第1の酸化物半導体膜と接する領域を有する、第2の酸化物半導体膜を形成した後第1の加熱処理を行い、
前記第1の絶縁膜、前記酸素が添加された第1の酸化物半導体膜、および前記第2の酸化物半導体膜のそれぞれをエッチングして、凸部を有する第1の絶縁膜、エッチングされた第1の酸化物半導体膜、およびエッチングされた第2の酸化物半導体膜を形成し、
前記エッチングされた第2の酸化物半導体膜と電気的に接続された、ソース電極およびドレイン電極を形成し、
前記エッチングされた第2の酸化物半導体膜、前記ソース電極および前記ドレイン電極と接する領域を有する、第3の酸化物半導体膜を形成し、
前記第3の酸化物半導体膜と接する領域を有する、第2の絶縁膜を形成し、
前記第2の絶縁膜と接する領域を有する、第2のゲート電極を形成することを特徴とする半導体装置の作製方法。 - 基板上に第1のゲート電極を形成し、
前記第1のゲート電極と接する領域を有する、第1の絶縁膜を、前記基板の温度が450℃以上前記基板の歪み点未満となるように加熱しながら形成し、
前記第1の絶縁膜と接する領域を有する、第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜に酸素を添加し、
前記酸素が添加された第1の酸化物半導体膜と接する領域を有する、第2の酸化物半導体膜を形成し、第1の加熱処理を行った後、前記第2の酸化物半導体膜上に導電膜を形成し、
前記第1の絶縁膜、前記酸素が添加された第1の酸化物半導体膜、前記第2の酸化物半導体膜、および前記導電膜のそれぞれをエッチングして、凸部を有する第1の絶縁膜、エッチングされた第1の酸化物半導体膜、エッチングされた第2の酸化物半導体膜、およびエッチングされた導電膜を形成し、
前記エッチングされた導電膜をエッチングして、ソース電極およびドレイン電極を形成し、
前記エッチングされた第2の酸化物半導体膜、前記ソース電極、および前記ドレイン電極と接する領域を有する、第3の酸化物半導体膜を形成し、
前記第3の酸化物半導体膜と接する領域を有する、第2の絶縁膜を形成し、
前記第2の絶縁膜と接する領域を有する、第2のゲート電極を形成することを特徴とする半導体装置の作製方法。 - 基板上に第1のゲート電極を形成し、
前記第1のゲート電極と接する領域を有する、第1の絶縁膜を、前記基板を加熱しながら形成し、
前記第1の絶縁膜と接する領域を有する、第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜に酸素を添加し、
前記酸素が添加された第1の酸化物半導体膜と接する領域を有する、第2の酸化物半導体膜を形成した後第1の加熱処理を行い、
前記第1の絶縁膜、前記酸素が添加された第1の酸化物半導体膜、および前記第2の酸化物半導体膜のそれぞれをエッチングして、凸部を有する第1の絶縁膜、エッチングされた第1の酸化物半導体膜、およびエッチングされた第2の酸化物半導体膜を形成し、
前記エッチングされた第2の酸化物半導体膜と電気的に接続された、ソース電極およびドレイン電極を形成し、
前記エッチングされた第2の酸化物半導体膜、前記ソース電極および前記ドレイン電極と接する領域を有する、第3の酸化物半導体膜を形成し、
前記第3の酸化物半導体膜と接する領域を有する、第2の絶縁膜を形成し、
前記第2の絶縁膜と接する領域を有する、第2のゲート電極を形成する半導体装置の作製方法であって、
前記第1の絶縁膜を形成するときの前記基板の温度は、前記第1の加熱処理の温度より高いことを特徴とする半導体装置の作製方法。 - 基板上に第1のゲート電極を形成し、
前記第1のゲート電極と接する領域を有する、第1の絶縁膜を、前記基板を加熱しながら形成し、
前記第1の絶縁膜と接する領域を有する、第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜に酸素を添加し、
前記酸素が添加された第1の酸化物半導体膜と接する領域を有する、第2の酸化物半導体膜を形成し、第1の加熱処理を行った後、前記第2の酸化物半導体膜上に導電膜を形成し、
前記第1の絶縁膜、前記酸素が添加された第1の酸化物半導体膜、前記第2の酸化物半導体膜、および前記導電膜のそれぞれをエッチングして、凸部を有する第1の絶縁膜、エッチングされた第1の酸化物半導体膜、エッチングされた第2の酸化物半導体膜、およびエッチングされた導電膜を形成し、
前記エッチングされた導電膜をエッチングして、ソース電極およびドレイン電極を形成し、
前記エッチングされた第2の酸化物半導体膜、前記ソース電極、および前記ドレイン電極と接する領域を有する、第3の酸化物半導体膜を形成し、
前記第3の酸化物半導体膜と接する領域を有する、第2の絶縁膜を形成し、
前記第2の絶縁膜と接する領域を有する、第2のゲート電極を形成する半導体装置の作製方法であって、
前記第1の絶縁膜を形成するときの前記基板の温度は、前記第1の加熱処理の温度より高いことを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項4のいずれか一において、
前記第1の酸化物半導体膜に、イオン注入法、イオンドーピング法、またはプラズマ処理により前記酸素を添加することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一において、
前記第3の酸化物半導体膜を形成した後、前記第3の酸化物半導体膜に酸素を添加し、第2の加熱処理を行い、
前記加熱された第3の酸化物半導体膜と接する領域を有する、前記第2の絶縁膜を形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項6のいずれか一において、
前記第1の酸化物半導体膜乃至前記第3の酸化物半導体膜はそれぞれ、InまたはGaを含むことを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項7のいずれか一において、
前記第1の酸化物半導体膜および前記第3の酸化物半導体膜の伝導帯の下端はそれぞれ、前記第2の酸化物半導体膜の伝導帯の下端よりも真空準位に近いことを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項8のいずれか一において、
前記第1の酸化物半導体膜および前記第3の酸化物半導体膜の伝導帯の下端のエネルギーと、前記第2の酸化物半導体膜の伝導帯の下端のエネルギーとの差は0.05eV以上2eV以下であることを特徴とする半導体装置の作製方法。
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US20170125553A1 (en) | 2017-05-04 |
JP2016001736A (ja) | 2016-01-07 |
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US20150340505A1 (en) | 2015-11-26 |
TWI672804B (zh) | 2019-09-21 |
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JP6775654B2 (ja) | 2020-10-28 |
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US9831326B2 (en) | 2017-11-28 |
WO2015177685A1 (en) | 2015-11-26 |
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