JP6353763B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6353763B2
JP6353763B2 JP2014201766A JP2014201766A JP6353763B2 JP 6353763 B2 JP6353763 B2 JP 6353763B2 JP 2014201766 A JP2014201766 A JP 2014201766A JP 2014201766 A JP2014201766 A JP 2014201766A JP 6353763 B2 JP6353763 B2 JP 6353763B2
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Prior art keywords
magnetic shield
shield material
lower magnetic
semiconductor chip
semiconductor device
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JP2014201766A
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English (en)
Japanese (ja)
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JP2016072493A (ja
JP2016072493A5 (https=
Inventor
直 荒井
直 荒井
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2014201766A priority Critical patent/JP6353763B2/ja
Priority to US14/870,084 priority patent/US9466784B2/en
Publication of JP2016072493A publication Critical patent/JP2016072493A/ja
Publication of JP2016072493A5 publication Critical patent/JP2016072493A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Mram Or Spin Memory Techniques (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Hall/Mr Elements (AREA)
JP2014201766A 2014-09-30 2014-09-30 半導体装置及びその製造方法 Active JP6353763B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014201766A JP6353763B2 (ja) 2014-09-30 2014-09-30 半導体装置及びその製造方法
US14/870,084 US9466784B2 (en) 2014-09-30 2015-09-30 Semiconductor device having multiple magnetic shield members

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014201766A JP6353763B2 (ja) 2014-09-30 2014-09-30 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2016072493A JP2016072493A (ja) 2016-05-09
JP2016072493A5 JP2016072493A5 (https=) 2017-06-08
JP6353763B2 true JP6353763B2 (ja) 2018-07-04

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JP2014201766A Active JP6353763B2 (ja) 2014-09-30 2014-09-30 半導体装置及びその製造方法

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US (1) US9466784B2 (https=)
JP (1) JP6353763B2 (https=)

Cited By (1)

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JP2016070848A (ja) * 2014-09-30 2016-05-09 株式会社東芝 磁気シールドパッケージ

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US10475985B2 (en) * 2015-03-26 2019-11-12 Globalfoundries Singapore Pte. Ltd. MRAM magnetic shielding with fan-out wafer level packaging
US10510946B2 (en) 2015-07-23 2019-12-17 Globalfoundries Singapore Pte. Ltd. MRAM chip magnetic shielding
KR102354370B1 (ko) * 2015-04-29 2022-01-21 삼성전자주식회사 쉴딩 구조물을 포함하는 자기 저항 칩 패키지
JP2017183629A (ja) * 2016-03-31 2017-10-05 東芝メモリ株式会社 半導体置及びその製造方法
KR101858952B1 (ko) 2016-05-13 2018-05-18 주식회사 네패스 반도체 패키지 및 이의 제조 방법
CN210223996U (zh) * 2017-02-28 2020-03-31 株式会社村田制作所 带薄膜屏蔽层的电子部件
CN107195600A (zh) * 2017-06-20 2017-09-22 广东美的制冷设备有限公司 芯片封装结构
JP6921691B2 (ja) * 2017-09-13 2021-08-18 株式会社東芝 半導体装置
US10775197B2 (en) * 2018-03-14 2020-09-15 Kabushiki Kaisha Toshiba Sensor
US10559536B2 (en) * 2018-06-26 2020-02-11 Abb Schweiz Ag Multi-layer conductors for noise reduction in power electronics
US10818609B2 (en) * 2018-07-13 2020-10-27 Taiwan Semiconductor Manufacturing Company Ltd. Package structure and method for fabricating the same
JP6905493B2 (ja) * 2018-08-24 2021-07-21 株式会社東芝 電子装置
EP3890612A4 (en) * 2018-12-06 2022-10-05 Analog Devices, Inc. SHIELDED INTEGRATED DEVICE HOUSINGS
CN113228272B (zh) 2018-12-06 2025-02-28 美国亚德诺半导体公司 具有无源器件组件的集成器件封装
US12438098B2 (en) * 2019-07-26 2025-10-07 Nantong Tongfu Microelectronics Co., Ltd. Packaging structure and fabrication method thereof
US11664340B2 (en) 2020-07-13 2023-05-30 Analog Devices, Inc. Negative fillet for mounting an integrated device die to a carrier
KR20230052080A (ko) 2021-10-12 2023-04-19 삼성전자주식회사 반도체 패키지

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JP2016070848A (ja) * 2014-09-30 2016-05-09 株式会社東芝 磁気シールドパッケージ

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JP2016072493A (ja) 2016-05-09
US20160093796A1 (en) 2016-03-31
US9466784B2 (en) 2016-10-11

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