CN202633305U - 具有半导体部件的层叠装置的组件 - Google Patents

具有半导体部件的层叠装置的组件 Download PDF

Info

Publication number
CN202633305U
CN202633305U CN2012201486314U CN201220148631U CN202633305U CN 202633305 U CN202633305 U CN 202633305U CN 2012201486314 U CN2012201486314 U CN 2012201486314U CN 201220148631 U CN201220148631 U CN 201220148631U CN 202633305 U CN202633305 U CN 202633305U
Authority
CN
China
Prior art keywords
ball
resin
assembly
chip
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2012201486314U
Other languages
English (en)
Inventor
J·维蒂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Application granted granted Critical
Publication of CN202633305U publication Critical patent/CN202633305U/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1052Wire or wire-like electrical connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076Shape of the containers
    • H01L2225/1082Shape of the containers for improving alignment between containers, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本实用新型涉及一种具有半导体部件的层叠装置的组件,所述组件包括层叠在彼此之上的、具有半导体部件的第一装置和第二装置,所述半导体部件包括相对的导电球,所述组件包括在所述第一装置上的至少一个树脂图形,所述树脂图形具有框架或者框架的一部分的形状,所述树脂图形以小于或等于所述球的直径的一半的非零距离靠近至少一些所述导电球,并且所述树脂图形的高度大于所述球的高度。

Description

具有半导体部件的层叠装置的组件
技术领域
本实用新型涉及一种组件,该组件包括相互层叠的、具有半导体部件的第一装置和第二装置,该半导体部件包含相对的导电球。
背景技术
图1是示意性地显示了组件的截面图,组件包括层叠的、具有半导体部件的第一装置和第二装置,分别为装置1(下层装置)和装置2(上层装置)。装置1和装置2每个均包括密封在封装体中的半导体芯片,分别为半导体芯片3和半导体芯片4。芯片3和芯片4的每个均由例如由硅制成的半导体衬底形成。通常减薄这些衬底以使得芯片厚度不超过100μm至200μm之间。在本领域中,这些组件在本领域中通常命名为PoP,“封装体上封装体”。作为示例,下层芯片3包括微处理器,而上层芯片4包括微处理器可以访问的存储器组件。
装置1的封装体包括支撑晶片5,芯片3组装在支撑芯片5的上表面上。晶片5在顶视图中具有比芯片3大的多的表面积。晶片5旨在支撑允许将芯片3连接至上层装置2的导电球。晶片5通常由有机材料制成,并且可以包括(例如由铜制成的)各种金属化层。上层包括接触区域(具体地,旨在接收导电球)。在晶片5的上表面上附接有旨在提供至上层装置2的连接的球7。在顶视图中,球7布置在围绕芯片3的环中。在该示例中,球9进一步附接至晶片5的下表面,并且旨在提供至外部装置(未示出)的连接,外部装置例如为印刷电路板。芯片3借由例如由金制成的接触导线11而连接至晶片5的接触区域。芯片3的上表面和侧表面、以及接触导线11埋设在形成装置1的封装体的上层部分的保护树脂13中。树脂13与芯片3一起形成在导电球7之间的位于晶片5的中心部分上的岛。
上层装置2的封装体类似于装置1的封装体。上层装置2的封装体包括,在下部中的支撑晶片15以及在上部中的保护树脂17,芯片4组装在支撑晶片15的上表面上,芯片4的上表面和侧表面以及提供芯片4至晶片15的连接的接触导线埋设在保护树脂17中。在晶片15的下表面侧,晶片15包括金属接触区域,金属接触区域旨在连接至提供至装置1的连接的导电球7。
应当注意到,仅可以在球7的高度Hb大于由树脂13和芯片3形成的中心岛的高度Hr时,才可以实现这种组件。当期望增加单位表面积的球7的数目(以增加装置1和装置2之间的连接的数目,而不增加支撑晶片5和支撑晶片15的表面积)时,这成为了这种类型的组件的限制。确实,为了增加单位表面积的球的数目,必需减小球直径,并且相应地减小高度Hb。单位表面积的球7的数目因此受限于中心岛的高度Hr。
可以通过在芯片3和晶片5之间提供表面组件(倒装芯片)来稍微减小高度Hr。在这种情况中,不是通过导电线而是通过布置在芯片3之下的球或接触焊垫来将芯片3连接至晶片5。因此可以去掉保护树脂13(在图1的示例中必须要用保护树脂13来保护导线11),并且因此减小高度Hr。
然而,实际上,包含芯片3的中心岛的高度Hr至少为250μm至300μm。鉴于在组装期间球7部分地变形的事实,不可以使用直径低于从350μm至450μm的球,对应于球间步长(从中心至中心)为650μm左右。
图2A至图2F是示意性地显示了被提供以允许使用较小直径的导电球的组装方法的示例的步骤的截面图。
图2A图示了装置1,其对应于图1的下层装置1。如前所述,装置1包括密封在封装体中的半导体芯片3。装置1的封装体包括,在其下部中的支撑晶片5以及在其上部中的保护树脂13,支撑晶片5具有组装在其上表面上的芯片3,芯片3的上表面和侧表面以及提供芯片3至晶片5的连接的导线11埋设在保护树脂13中。在该组装方法的开始步骤中,将导电球7附接至晶片5的上表面的接触区域,该接触区域环绕由芯片3和树脂13形成的中心岛。
图2B图示了在其期间装置1的整个上表面上形成高度大于球7的高度的树脂层21的步骤。在该步骤结束时,球7嵌入在层21中,并且因此不再可从装置1的上表面连通。
图2C图示了在其期间通过激光刻蚀在球7的前面的树脂层21中形成开口以清扫至球7的上部的通路的步骤。
图2D图示了在其期间将对应于图1的上层装置2的装置2键合至装置1的步骤。如前所述,装置2包括密封在封装体中的半导体芯片4。装置2的封装体包括,在其下部中的支撑晶片15以及在其上部中的保护树脂17,支撑晶片15具有组装在其上表面上的芯片4,芯片4的上表面和侧表面以及提供芯片4至晶片15的连接的导线埋设在保护树脂17中。在将装置2键合至装置1之前,将导电球7’附接至晶片15的下表面,并且导电球7’旨在与下层装置1的球7接触。在步骤2C处形成在树脂层21中的空腔允许在键合期间相对于球7适当地引导并且对准球7’。
图2E图示了在将装置2键合至装置1之后并且在组件被加热以将球7’焊接至球7之后的最终组件。应当注意到,球9可以附接至装置1的晶片5的下表面,以提供至例如为印刷电路板的外部装置(未示出)的连接。
在图2A至图2E中所示的方法,相对于关于图1描述的类型的组件,可以增加装置1和装置2之间的单位表面积的连接数目。在图2E的组件中,装置1和装置2包括相互焊接的相对的导电球。因此,对于给定的球直径而言,支撑晶片5的上表面与支撑晶片15的下表面之间的可用的高度Hb近似为关于图1描述的类型组件的两倍。因此,对于给定的包含芯片3的中心岛的高度Hr而言,可以减小球直径,并且因此相对于关于图1描述的类型的组件减小球间步长。作为示例,关于图2A至图2E描述的组装方法允许中心岛高度Hr近似从250μm至300μm范围使用具有直径从200μm至250μm的球、而球间步长近似从400μm至500μm范围内。
然而,该方法的缺点在于,需要通过树脂层21的激光刻蚀在导电球7的前面形成开口的漫长且昂贵的步骤(图2C)。此外,在已形成这些开口之后,需要提供清洁步骤,以避免树脂21的残留物阻止在球7和7’之间的接触的形成。尽管利用这些清洁步骤,仍然可能凑巧未移除树脂残留物,这不利地影响了球7和7’之间的电接触的质量。
实用新型内容
因此,一个实施例的目的在于提供一种组件,该组件包括层叠在彼此之上的、具有半导体部件的第一装置和第二装置,该半导体部件包括相对的导电球,该组件克服了现有解决方案的至少某些缺点。
一个实施例的目的在于提供一种组件,其包括层叠在彼此之上的具有半导体部件的第一装置和第二装置。
一个实施例提供了一种组件,其包括层叠在彼此之上的、具有半导体部件的第一装置和第二装置,该半导体部件包括相对的导电球,该组件包括在第一装置上的具有框架或者框架一部分的形状的至少一个树脂图形,该树脂图形以小于或等于球直径的一半的非零距离靠近至少一些导电球,并且该树脂图形的高度大于球高度。
依照一个实施例,所述至少一个图形具有围绕第一装置的所有球的框架的形状。
将结合附图,在特定实施例的以下非限制性描述中详细讨论前述以及其他目的、特征和优点。
附图说明
如前所述,图1是示意性地显示了组件的截面图,该组件包括层叠在彼此之上的、具有半导体部件的第一装置和第二装置;
如前所述,图2A至图2E是示意性地显示了用于形成组件的方法的步骤的截面图,该组件包括层叠在彼此之上的、具有半导体部件的第一装置和第二装置,该半导体部件包含相对的导电球;
图3A至图3D是示意性地显示了用于形成组件的方法的一个实施例的步骤的截面图,该组件包括层叠在彼此之上的、具有半导体部件的第一装置和第二装置,半导体部件包含相对的导电球;
图4A至图4F是显示了在关于图3A至图3D描述的方法中使用的下层装置的实施例的简化顶视图。
具体实施方式
为了清晰起见,在不同的附图中,相同的元件标注为相同的附图标记,并且此外,如在集成电路的表示中常见的,各个附图未按比例绘制。
图3A至图3D是示意性地显示了用于形成组件的方法的一个实施例的步骤的截面图,相互层叠的第一装置和第二装置,该半导体部件包含相对的导电球。
图3A图示了下层装置1,其例如对应于图1的下层装置1。如前所述,装置1包括密封在封装体内的半导体芯片3。装置1的封装体包括,在其下部中的支撑晶片5以及在其上部中的保护树脂13,支撑晶片5具有组装在其上表面上的芯片3,芯片3的上表面和侧表面以及提供了芯片3至晶片5的连接的导线11埋设在保护树脂13中。导电球7附接至晶片5的下表面的接触区域。在本示例中,在顶视图中,球7围绕芯片3布置环。
图3B图示了在其期间通过模制在支撑晶片5的上表面上形成高度大于球7的高度的树脂图形31的步骤。在该示例中,在顶视图中,图形31具有围绕球7的组件的框架的形状。作为示例,图形31的高度近似在球7的高度的110%至190%范围内,并且优选地在130%至170%范围内。图形31以小于或等于球7直径的一半的距离d靠近形成了球环7的外部边界的球7。实际上,考虑到制造约束并且特别是模制侧壁的厚度,将距离d选择为尽可能小。将注意到,树脂图形31和球7之间的距离d必然是非零的,这是因为其至少等于模制侧壁的厚度。换言之,装置1的球7均未与树脂图形31接触。与关于图2A至图2E描述的方法形成对比的是,在所提供的方法中,树脂31并未覆盖球7。
图3C图示了在其期间例如对应于图1的上层装置2的装置2键合至装置1的步骤。在该示例中,如前所述,装置2包括密封在封装体内的半导体芯片4。装置2的封装体包括,在其下部中的支撑晶片15以及在其上部中的保护树脂17,支撑晶片15具有组装在其上表面上的芯片4,芯片4的上表面和侧表面以及提供芯片4至晶片15的连接的导线埋设在保护树脂17中。在将装置2键合至装置1之前,将旨在与下层装置1的球7接触的接触球7’附接至晶片15的下表面。在将装置2键合至装置1期间,树脂框架31允许相对于球7合适地引导并对准球7’。球7’能够直接抵靠框架31的内侧壁,因此确保了球的恰当对准,并且尤其是避免了装置2的球7’使装置1的两个球7短路。
图3D图示了在将装置2键合至装置1之后并且在组件被加热以将球7,焊接至球7之后的最终组件。球9可以附接至装置1的晶片5的下表面,以提供至例如是印刷电路板的外部装置(未示出)的连接。
应当注意到,树脂图形31可以采用除了围绕球组件7的框架之外的其它形式。
图4A至图4F是关于图3B描述类型的装置1的简化顶视图,其显示了树脂图形31可以采取的各种形状。
图4A图示了对应于图3B的示例,其中树脂图形31具有围绕球7的框架的形状,其在相对于球环7的外部边缘小于或等于球半径的距离处。
图4B图示了其中树脂图形31具有形成在球环7内的框架的形状的示例,其在相对于球环7的内部边缘小于或等于球半径的距离处。
图4C图示了其中树脂图形31具有平行于球环7的外部角的角的形状的示例,其在相对于球环7的外部角小于或等于球半径的距离处。
图4D图示了其中树脂图形31具有平行于球环7的内部角的内部角的形状的示例,其在相对于球环7小于或等于球半径的距离处。
图4E图示了其中树脂图形31具有平行于球环7的外部和内部角的条带部分的形状的示例,其在相对于球环7的角小于或等于球半径的距离处。
图4F图示了其中树脂图形31具有围绕球7的框架的形状的示例,该框架在其内部边缘具有锯齿状物,突出到将球7与球环7的外部边缘分隔的空间中。
更一般地,以下将在本领域技术人员能力范围内,即提供具有框架或者框架的一部分的形状的任何树脂图形,该树脂图形能够提供球7’相对于球7的合适对准,该图形以小于或等于一半球直径的非零距离靠近至少一些球7。将依照球7的布局特别地选择该图形。还应当注意到,球7和7’可以不以环来设置。
图4A和图4F(外部边缘)以及图4B(内部边缘)所示的类型的连续树脂图形,相对于不连续图形(图4C、图4D和图4E)具有优点在于,在模制期间仅需要形成单个树脂注入点。
此外,图4A和图4F所示的树脂图形(晶片5的边界处的外部框架)具有加固支撑晶片5的优点,这允许当组件被加热以将球7和7’焊接时避免结构的任何翘曲。
所提供方法的优点在于,无需提供在埋设有导电球的树脂层中形成局部开口的昂贵步骤。
此外,所提供的方法确保球7和7’之间的电接触的良好质量,这是由于在相应的球7和7’之间不可能存在由于刻蚀导致的树脂残留物。
已描述了本实用新型的具体实施例。本领域技术人员易于得到各种改变、修改和改进。
具体地,本实用新型不限于具有以上示例中所述类型的半导体部件的唯一装置。装置1和/或装置2的半导体芯片例如可以通过倒装芯片类型的连接(没有导线以及可能没有保护树脂)而连接至各自的图形。此外,装置1和装置2每个可以均包括一个或多个层叠的半导体芯片。更一般地,所提供的方法可以用于组装具有包括相对的导电球的半导体部件的所有类型的装置。
此外,本实用新型不限于本说明书中示例所述的尺度。关于图3A至图3D以及图4A至图4E描述的类型的方法尤其可以用于较小尺度的组装装置,例如包括相对的导电球的两个层叠的半导体芯片。
此外,使用所提供的方法来层叠多于两个的包括半导体部件的装置当然也将在本领域技术人员的能力范围内。
这些改变、修改和改进旨在作为本说明的一部分,并且旨在位于本实用新型的精神和范围之内。因此,前述说明仅为了示例,而并非旨在限制。本实用新型仅由以下权利要求及其等同方式限定。

Claims (2)

1.一种具有半导体部件的层叠装置的组件,其特征在于,该组件包括层叠在彼此之上的、具有所述半导体部件的第一装置(1)和第二装置(2),所述半导体部件包括相对的导电球(7,7’),所述组件包括在所述第一装置(1)上的至少一个树脂图形(31),所述树脂图形具有框架或者框架的一部分的形状,所述树脂图形以小于或等于所述球的直径的一半的非零距离靠近至少一些所述导电球(7),并且所述树脂图形的高度大于所述球的高度。
2.根据权利要求1所述的组件,其特征在于,其中,所述至少一个图形(31)具有围绕所述第一装置(1)的所有球(7)的框架的形状。
CN2012201486314U 2011-04-14 2012-04-06 具有半导体部件的层叠装置的组件 Expired - Fee Related CN202633305U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1153274A FR2974234A1 (fr) 2011-04-14 2011-04-14 Assemblage de dispositifs a composants semiconducteurs empiles
FR1153274 2011-04-14

Publications (1)

Publication Number Publication Date
CN202633305U true CN202633305U (zh) 2012-12-26

Family

ID=44279687

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2012101048935A Pending CN102738086A (zh) 2011-04-14 2012-04-06 具有半导体部件的层叠装置的组件
CN2012201486314U Expired - Fee Related CN202633305U (zh) 2011-04-14 2012-04-06 具有半导体部件的层叠装置的组件

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2012101048935A Pending CN102738086A (zh) 2011-04-14 2012-04-06 具有半导体部件的层叠装置的组件

Country Status (3)

Country Link
US (1) US20120261820A1 (zh)
CN (2) CN102738086A (zh)
FR (1) FR2974234A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8531040B1 (en) * 2012-03-14 2013-09-10 Honeywell International Inc. Controlled area solder bonding for dies
KR102283322B1 (ko) * 2014-11-14 2021-08-02 삼성전자주식회사 반도체 패키지 및 그 제조방법
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
KR102358323B1 (ko) * 2017-07-17 2022-02-04 삼성전자주식회사 반도체 패키지

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
TW434767B (en) * 1998-09-05 2001-05-16 Via Tech Inc Package architecture of ball grid array integrated circuit device
JP2004349495A (ja) * 2003-03-25 2004-12-09 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
JP2005093780A (ja) * 2003-09-18 2005-04-07 Toppan Printing Co Ltd 半導体装置
EP1732127B1 (en) * 2005-06-08 2016-12-14 Imec Method for bonding and device manufactured according to such method
JP4512545B2 (ja) * 2005-10-27 2010-07-28 パナソニック株式会社 積層型半導体モジュール
WO2007083351A1 (ja) * 2006-01-17 2007-07-26 Spansion Llc 半導体装置およびその製造方法
JP5074738B2 (ja) * 2006-10-24 2012-11-14 リンテック株式会社 複合型半導体装置用スペーサーシート、及び複合型半導体装置の製造方法
JP5211493B2 (ja) * 2007-01-30 2013-06-12 富士通セミコンダクター株式会社 配線基板及び半導体装置

Also Published As

Publication number Publication date
US20120261820A1 (en) 2012-10-18
FR2974234A1 (fr) 2012-10-19
CN102738086A (zh) 2012-10-17

Similar Documents

Publication Publication Date Title
JP5840479B2 (ja) 半導体装置およびその製造方法
US8643161B2 (en) Semiconductor device having double side electrode structure
US7435619B2 (en) Method of fabricating a 3-D package stacking system
US7417329B2 (en) System-in-package structure
US9418968B2 (en) Semiconductor device including semiconductor chips mounted over both surfaces of substrate
US20090127682A1 (en) Chip package structure and method of fabricating the same
JP5467959B2 (ja) 半導体装置
US20110156251A1 (en) Semiconductor Package
US9385091B2 (en) Reinforcement structure and method for controlling warpage of chip mounted on substrate
US7489044B2 (en) Semiconductor package and fabrication method thereof
JP2009044110A (ja) 半導体装置及びその製造方法
CN103119711A (zh) 形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构
CN202633305U (zh) 具有半导体部件的层叠装置的组件
US8318548B2 (en) Method for manufacturing semiconductor device
US20090108471A1 (en) Wiring board of semiconductor device, semiconductor device, electronic apparatus, mother board, method of manufacturing wiring board of semiconductor device, method of manufacturing mother board and method of manufacturing electronic apparatus
TW201519391A (zh) 半導體元件及其製造方法
US7479706B2 (en) Chip package structure
KR101099583B1 (ko) 웨이퍼 레벨의 칩 적층형 패키지 및 그 제조 방법
US20100283145A1 (en) Stack structure with copper bumps
CN110993631B (zh) 一种基于背照式图像传感器芯片的封装方法
JP2016063002A (ja) 半導体装置およびその製造方法
US8416576B2 (en) Integrated circuit card
US8058725B2 (en) Package structure and package substrate thereof
JP2007067234A (ja) 半導体装置及びその製造方法
KR20140086417A (ko) 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121226

Termination date: 20150406

EXPY Termination of patent right or utility model