JP6210777B2 - バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法 - Google Patents

バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法 Download PDF

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Publication number
JP6210777B2
JP6210777B2 JP2013155615A JP2013155615A JP6210777B2 JP 6210777 B2 JP6210777 B2 JP 6210777B2 JP 2013155615 A JP2013155615 A JP 2013155615A JP 2013155615 A JP2013155615 A JP 2013155615A JP 6210777 B2 JP6210777 B2 JP 6210777B2
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JP
Japan
Prior art keywords
layer
metal layer
bump structure
solder material
resin layer
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Active
Application number
JP2013155615A
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English (en)
Japanese (ja)
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JP2015026722A (ja
JP2015026722A5 (OSRAM
Inventor
今藤　桂
桂 今藤
克巳 山崎
克巳 山崎
片桐　規貴
規貴 片桐
晃明 千野
晃明 千野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013155615A priority Critical patent/JP6210777B2/ja
Priority to US14/328,765 priority patent/US9485864B2/en
Publication of JP2015026722A publication Critical patent/JP2015026722A/ja
Publication of JP2015026722A5 publication Critical patent/JP2015026722A5/ja
Application granted granted Critical
Publication of JP6210777B2 publication Critical patent/JP6210777B2/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10704—Pin grid array [PGA]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP2013155615A 2013-07-26 2013-07-26 バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法 Active JP6210777B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013155615A JP6210777B2 (ja) 2013-07-26 2013-07-26 バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法
US14/328,765 US9485864B2 (en) 2013-07-26 2014-07-11 Bump structure, wiring substrate, semiconductor apparatus and bump structure manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013155615A JP6210777B2 (ja) 2013-07-26 2013-07-26 バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法

Publications (3)

Publication Number Publication Date
JP2015026722A JP2015026722A (ja) 2015-02-05
JP2015026722A5 JP2015026722A5 (OSRAM) 2016-07-21
JP6210777B2 true JP6210777B2 (ja) 2017-10-11

Family

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Family Applications (1)

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JP2013155615A Active JP6210777B2 (ja) 2013-07-26 2013-07-26 バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法

Country Status (2)

Country Link
US (1) US9485864B2 (OSRAM)
JP (1) JP6210777B2 (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412686B2 (en) * 2014-08-26 2016-08-09 United Microelectronics Corp. Interposer structure and manufacturing method thereof
JP2016076533A (ja) * 2014-10-03 2016-05-12 イビデン株式会社 バンプ付きプリント配線板およびその製造方法
JP2017041500A (ja) * 2015-08-18 2017-02-23 イビデン株式会社 プリント配線板および半導体パッケージ
US10583545B2 (en) 2016-02-25 2020-03-10 Milwaukee Electric Tool Corporation Power tool including an output position sensor
US10184189B2 (en) 2016-07-18 2019-01-22 ECSI Fibrotools, Inc. Apparatus and method of contact electroplating of isolated structures
WO2018138902A1 (ja) * 2017-01-30 2018-08-02 三菱電機株式会社 パワー半導体装置の製造方法およびパワー半導体装置
KR102572367B1 (ko) * 2017-11-28 2023-08-30 소니 세미컨덕터 솔루션즈 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법
JP7154818B2 (ja) * 2018-05-10 2022-10-18 ローム株式会社 半導体装置および半導体装置の製造方法
CN113053833A (zh) * 2019-12-26 2021-06-29 财团法人工业技术研究院 一种半导体装置及其制作方法
US11302537B2 (en) * 2020-04-01 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with conductive adhesive layer and method for forming the same
CN112272452A (zh) * 2020-09-23 2021-01-26 惠州中京电子科技有限公司 一种减小倒装led板pad上幅间距的制备方法
KR102881358B1 (ko) * 2020-11-23 2025-11-04 삼성전기주식회사 인쇄회로기판
WO2025173385A1 (ja) * 2024-02-13 2025-08-21 パナソニックＩｐマネジメント株式会社 インターポーザおよびそれを備えた回路基板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01226160A (ja) 1988-03-07 1989-09-08 Nippon Telegr & Teleph Corp <Ntt> 電子部品接続用の端子装置および端子の製造方法
US6497943B1 (en) * 2000-02-14 2002-12-24 International Business Machines Corporation Surface metal balancing to reduce chip carrier flexing
JP3735547B2 (ja) * 2001-08-29 2006-01-18 株式会社東芝 半導体装置及びその製造方法
US6992379B2 (en) * 2001-09-05 2006-01-31 International Business Machines Corporation Electronic package having a thermal stretching layer
JP4409455B2 (ja) * 2005-01-31 2010-02-03 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4949279B2 (ja) * 2008-01-21 2012-06-06 新光電気工業株式会社 配線基板及びその製造方法
KR20090080623A (ko) 2008-01-22 2009-07-27 삼성전기주식회사 포스트 범프 및 그 형성방법
JP5407269B2 (ja) * 2008-10-21 2014-02-05 富士通セミコンダクター株式会社 半導体装置
JP2010157690A (ja) * 2008-12-29 2010-07-15 Ibiden Co Ltd 電子部品実装用基板及び電子部品実装用基板の製造方法

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Publication number Publication date
US9485864B2 (en) 2016-11-01
US20150029689A1 (en) 2015-01-29
JP2015026722A (ja) 2015-02-05

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