JP6170832B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP6170832B2
JP6170832B2 JP2013264671A JP2013264671A JP6170832B2 JP 6170832 B2 JP6170832 B2 JP 6170832B2 JP 2013264671 A JP2013264671 A JP 2013264671A JP 2013264671 A JP2013264671 A JP 2013264671A JP 6170832 B2 JP6170832 B2 JP 6170832B2
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JP
Japan
Prior art keywords
wiring
layer
insulating layer
insulating
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013264671A
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English (en)
Japanese (ja)
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JP2015122385A5 (enExample
JP2015122385A (ja
Inventor
田中　正人
正人 田中
章司 渡邉
章司 渡邉
清水　規良
規良 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013264671A priority Critical patent/JP6170832B2/ja
Priority to US14/548,568 priority patent/US9591750B2/en
Publication of JP2015122385A publication Critical patent/JP2015122385A/ja
Publication of JP2015122385A5 publication Critical patent/JP2015122385A5/ja
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/029—Woven fibrous reinforcement or textile
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2013264671A 2013-12-20 2013-12-20 配線基板、半導体装置及び配線基板の製造方法 Active JP6170832B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013264671A JP6170832B2 (ja) 2013-12-20 2013-12-20 配線基板、半導体装置及び配線基板の製造方法
US14/548,568 US9591750B2 (en) 2013-12-20 2014-11-20 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013264671A JP6170832B2 (ja) 2013-12-20 2013-12-20 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2015122385A JP2015122385A (ja) 2015-07-02
JP2015122385A5 JP2015122385A5 (enExample) 2016-10-06
JP6170832B2 true JP6170832B2 (ja) 2017-07-26

Family

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Family Applications (1)

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JP2013264671A Active JP6170832B2 (ja) 2013-12-20 2013-12-20 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9591750B2 (enExample)
JP (1) JP6170832B2 (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017037900A (ja) * 2015-08-07 2017-02-16 ローム株式会社 半導体装置およびその製造方法
KR101933408B1 (ko) * 2015-11-10 2018-12-28 삼성전기 주식회사 전자부품 패키지 및 이를 포함하는 전자기기
JP6661232B2 (ja) * 2016-03-01 2020-03-11 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
JP6816964B2 (ja) * 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6594264B2 (ja) * 2016-06-07 2019-10-23 新光電気工業株式会社 配線基板及び半導体装置、並びにそれらの製造方法
US10037949B1 (en) * 2017-03-02 2018-07-31 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US10163842B2 (en) * 2017-04-18 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
JP2019062092A (ja) * 2017-09-27 2019-04-18 イビデン株式会社 プリント配線板
US12176277B2 (en) * 2017-11-13 2024-12-24 Dyi-chung Hu Package substrate and package structure
US11309252B2 (en) * 2017-11-13 2022-04-19 Dyi-chung Hu Package substrate and package structure
US12309943B2 (en) * 2018-06-08 2025-05-20 Unimicron Technology Corp. Circuit carrier and manufacturing method thereof and package structure
CN110858576B (zh) * 2018-08-24 2022-05-06 芯舟科技(厦门)有限公司 覆晶封装基板及其制法
TWI746415B (zh) * 2018-08-30 2021-11-11 恆勁科技股份有限公司 覆晶封裝基板之核心結構及其製法
TWI739027B (zh) * 2018-08-30 2021-09-11 恆勁科技股份有限公司 覆晶封裝基板之核心結構及其製法
KR102145204B1 (ko) * 2018-08-30 2020-08-18 삼성전자주식회사 반도체 패키지
JP7289620B2 (ja) * 2018-09-18 2023-06-12 新光電気工業株式会社 配線基板、積層型配線基板、半導体装置
TWI736100B (zh) * 2019-01-08 2021-08-11 胡迪群 具高密度線路的基板結構及其製法
US12205877B2 (en) * 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
CN115547846A (zh) * 2019-02-21 2022-12-30 奥特斯科技(重庆)有限公司 部件承载件及其制造方法和电气装置
CN113767716B (zh) * 2019-05-06 2024-07-30 3M创新有限公司 图案化导电制品
JP7292114B2 (ja) * 2019-06-07 2023-06-16 イビデン株式会社 配線基板及び配線基板の製造方法
KR102798702B1 (ko) * 2019-07-22 2025-04-23 삼성전자주식회사 반도체 패키지
JP7252871B2 (ja) * 2019-09-26 2023-04-05 京セラ株式会社 基体構造体及び基体構造体を用いた電子デバイス
TWI738069B (zh) * 2019-09-27 2021-09-01 恆勁科技股份有限公司 覆晶封裝基板及其製法
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
US11956898B2 (en) 2020-09-23 2024-04-09 Apple Inc. Three-dimensional (3D) copper in printed circuit boards
JP7529562B2 (ja) * 2020-12-28 2024-08-06 Tdk株式会社 電子部品及びその製造方法
TWI740767B (zh) * 2021-01-07 2021-09-21 欣興電子股份有限公司 線路板及其製作方法
TW202345305A (zh) * 2022-05-11 2023-11-16 大陸商芯愛科技（南京）有限公司 封裝基板及其製法
TWI814582B (zh) * 2022-09-19 2023-09-01 大陸商芯愛科技（南京）有限公司 封裝基板

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964538A (ja) * 1995-08-23 1997-03-07 Toppan Printing Co Ltd プリント配線板の製造方法
JPH11126978A (ja) * 1997-10-24 1999-05-11 Kyocera Corp 多層配線基板
JP2003023252A (ja) 2001-07-10 2003-01-24 Ibiden Co Ltd 多層プリント配線板
JP5191074B2 (ja) 2001-07-10 2013-04-24 イビデン株式会社 多層プリント配線板
JP4119205B2 (ja) * 2002-08-27 2008-07-16 富士通株式会社 多層配線基板
JP5013973B2 (ja) * 2007-05-31 2012-08-29 株式会社メイコー プリント配線板及びその製造方法、並びに、このプリント配線板を用いた電子部品収容基板及びその製造方法
US8097946B2 (en) * 2007-10-31 2012-01-17 Sanyo Electric Co., Ltd. Device mounting board, semiconductor module, and mobile device
JP5284146B2 (ja) * 2008-03-13 2013-09-11 日本特殊陶業株式会社 多層配線基板、及びその製造方法
KR100968278B1 (ko) * 2008-03-28 2010-07-06 삼성전기주식회사 절연시트 및 그 제조방법과 이를 이용한 인쇄회로기판 및그 제조방법
JPWO2011016555A1 (ja) * 2009-08-07 2013-01-17 日本電気株式会社 半導体装置とその製造方法
JP5587139B2 (ja) * 2010-11-04 2014-09-10 日本特殊陶業株式会社 多層配線基板
US8698269B2 (en) * 2011-02-28 2014-04-15 Ibiden Co., Ltd. Wiring board with built-in imaging device and method for manufacturing same
US9113569B2 (en) * 2011-03-25 2015-08-18 Ibiden Co., Ltd. Wiring board and method for manufacturing same
US20150114699A1 (en) * 2013-10-24 2015-04-30 Samsung Electro-Mechanics Co., Ltd. Insulation material, printed circuit board using the same and method of manufacturing the same

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Publication number Publication date
JP2015122385A (ja) 2015-07-02
US20150181703A1 (en) 2015-06-25
US9591750B2 (en) 2017-03-07

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