JP6037318B2 - ソフトウェアで信号に対して1つまたは複数のデジタル・フロントエンド(dfe)機能を実行するための方法およびプロセッサ - Google Patents
ソフトウェアで信号に対して1つまたは複数のデジタル・フロントエンド(dfe)機能を実行するための方法およびプロセッサ Download PDFInfo
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Description
上記のように、チャネル・フィルタおよびデジタル・アップ・コンバージョン段階110は、たとえば、有限のインパルス応答(FIR)フィルタを使用するチャネル・フィルタリングおよびデジタル化されたベースバンド信号を無線周波数(RF)に変換するためのデジタル・アップ・コンバージョンを実行する。以下に記述するように、チャネル・フィルタおよびデジタル・アップ・コンバージョン段階110の1つまたは複数の機能は、ベクトル乗算、ベクトル加算および縮小(reduction)、あるいは、ベクトル畳み込み演算命令を使用して加速された1つまたは複数のベクタ・プロセッサでソフトウェアに実装される。デジタル・アップ・コンバージョンは、たとえば、入力信号に復素指数関数をかけることを必要とし(ベクトル乗算、つまり2つのベクトル、信号およびロテーターのベクトルのコンポーネント・ワイズ(component wise)の積)、本発明の態様は、加速された復素指数関数を用いる。デジタル変調は、(ベクトルとして計算された)復素指数関数に基づいて数値的に制御された発振器(NCO)を使用してオプションとして実行される。
上記のように、波高因子低減段階120は、送信された信号のPARを制限する。以下に記述するように、波高因子低減は、ピーク検出およびピーク・キャンセレーションを必要とする。ピーク検出は、ベクトル比較命令または専門化されたmax()命令を活用することができる。同様に、ピーク・キャンセレーションは、ベクトルの乗算および加算を含み、ハード・クリッピングは、しきい値およびベクタ・プロセッサを使用して加速できる調整(ベクトル・コンポーネント・ワイズに対して1/x)に比較するエンベロープ計算(ベクトルsqrt()およびベクトル(x*conj(x)))を含む。sqrt()および1/xの演算は、加えて、ベクトルx−0.5の演算/命令を使用して、組み合わせて実行することができる。
Pow_vec4(x1,x2,x3,x4,K)
vec_pow(x1,x2・・・x32,K)、ここでK値は、たとえば、0.5、−0.5、−1である。
上記のように、デジタル・プリディストーション段階130は、効率を向上するために電力増幅器を線形化する。以下に記述するように、デジタル・プリディストーションは、ベクトルの非線形関数を計算することを含む。非線形関数は、多項式または他の基底関数でもよい。これは、ルックアップ・テーブルおよびテイラー級数を組み合わせる非線形の命令を使用して加速することができる。
デジタル前置補償器1130は、非線形系のボルテラ級数モデルを使用して、非線形のフィルタとして実装することができる。ボルテラ級数は、テイラー級数と同様に非線形の振る舞いのモデルである。ボルテラ級数は「メモリ」効果をキャプチャするその能力では、テイラー級数と異なる。テイラー級数は、このシステムの出力がその特定の時間の入力に厳密に依存している場合、所与の入力に対して非線形系の応答を近似するために使用することができる(静的な非線形性)。ボルテラ級数では、非線形系の出力は、他のときのシステムへの入力に依存している。したがって、ボルテラ級数では、デバイスの「メモリ」の影響をキャプチャすることが可能になる。
f(ε)=α0+α1・ε+α2・ε2+α3・ε3
ここで、係数αはルックアップ・テーブルから取得される。しかし、この式の複雑性は重要である(乗算および二乗演算を実行する多数の乗算器を用いる)。
f(ε)=((b3・ε+b2)・ε+b1)・ε+b0(3)
等式(3)の複雑性は、たった3つの乗算および3つの加算の演算に減らされた。f(ε)は、ルックアップ・テーブルに格納された値からのオフセットである。
vec_nl(x1,x2・・・x16)、x[k]の範囲は0から1
上記のように、アナログ/デジタル変換器(ADC)からのデジタル信号は、DPDパラメータ推定160のためにオンチップ・メモリ170に格納される。以下に説明するように、DPDパラメータ推定は、x.|y|kなど非線形の項を含む行列を計算することを含む。エンベロープ演算は、ベクタ・プロセッサを使用して加速できるタイプx*conj(x)およびベクトルsqrt()のベクトル演算を含む。行列の乗算は、ベクトルの乗算、加算、および縮小を使用することができる。畳み込み演算は、ベクトル畳み込み演算命令を使用して加速することができる。
C(r,p,q)=E(|y(n−p)|ry*(n−q)・−z(n))
hk,m,lは、電力増幅器1620、1720の逆モデルに対して望まれる係数である。
B(k,r,l,m,p,q)=E(|y(n−p)|r.|y(n−l)|ky*(n−q).y(n−m))
h=B−1C
hは、DPD係数に使用される。
図18は、本明細書に記述されたフィルタリング操作の多くで用いることができるベクトル畳み込み関数1800を示している。一般的に、ベクトル畳み込み関数1800は、Nビット複素数データ(N/2ビット実数およびN/2ビット虚数)および複素対蹠的データ(たとえば係数)の畳み込み演算を計算する。ベクトル畳み込み関数1800は、典型的にはN1+N2−1サンプルの入力ベクトルを受信し、(軸1830に沿った)入力ベクトル1810 N1および係数のN1サンプルの時間シフト版1820を処理し、時間シフト版ごとに(ゼロシフト版を含む各タイムラグ)FIR出力値1825を生成する。出力ベクトル1860は、N2出力値で構成される。
hj,k∈{0,1}およびh”j,k∈{0,1}
上記のように、等化/IQインバランス補正140は、チャネル障害を緩和するために、IQ補正を実行し、RFチャネル等化を用いる。以下に記述するように、RFチャネル等化および/またはI/Qインバランス補正は、ベクトル乗算、加算、および縮小、または、畳み込み演算命令を使用して実装することができる。同様に、ベクトル乗算/加算/縮小、または相関命令を使用して実装することができる。代表的な実施例では、RFチャネル等化およびI/Qインバランス補正は、等化/IQインバランス補正140で組み合わせられる。
たとえば、有限のインパルス応答(FIR)フィルタおよび無線周波数(RF)をデジタル化されたベースバンド信号に変換するデジタル・ダウン・コンバージョンを使用して、受信経路のチャネル・フィルタリングを実行するために、チャネル・フィルタ/チャネル・デジタル・ダウン・コンバージョン(DDC)ブロック180は、図1のチャネル・フィルタおよびデジタル・アップ・コンバージョン段階110と同様に実装することができる。
本明細書に記述した多数の非線形関数および他の関数の詳細な記述については、たとえば、それぞれ参照により本明細書に組み込まれている、2008年11月28日に出願された米国特許出願第12/324,926号「Digital Signal Processor Having Instruction Set with One or More Non−Linear Complex Functions」、2008年11月28日に出願された米国特許出願第12/324,927号「Digital Signal Processor Having Instruction Set With One Or More Non−Linear Functions Using Reduced Look−Up Table」、2008年11月28日に出願された米国特許出願第12/324,934号「Digital Signal Processor With One Or More Non−Linear Functions Using Factorized Polynomial Interpolation」、2009年1月30日に出願された米国特許出願第12/362,874号「Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look−Up Table」、2010年8月3日に出願された米国特許出願第12/849142号「System and Method for Providing Memory Bandwidth Efficient Correlation Acceleration」、および/またはLei Dingら、「Compensation of Frequency−Dependent Gain/Phase Imbalance in Predistortion Linearization Systems」、IEEE Transactions on Circuits and Systems、Vol.55,No.1、390〜97(2008年2月)を参照すること。
本発明の代表的な実施形態について、デジタル論理ブロックおよびデジタル・プロセッサ内のメモリ・テーブルに関して記述してきたが、当業者には明白であろうように、ソフトウェア・プログラムの処理ステップとして、回路素子または状態機械によるハードウェアにおいて、またはソフトウェアとハードウェアの両方の組み合わせにおいて、デジタル領域に様々な機能を実装することができる。そのようなソフトウェアは、たとえば、デジタル信号プロセッサ、特定用途向け集積回路、またはマイクロコントローラに用いることができる。そのようなハードウェアおよびソフトウェアは、集積回路内に実装された回路内に統合することができる。
Claims (6)
- ソフトウェアで信号に対して1つまたは複数のデジタル・フロントエンド(DFE)機能を実行するための方法であって、
前記信号に前記1つまたは複数のデジタル・フロントエンド(DFE)機能を実行するために、プロセッサで1つまたは複数の専門化された命令を実行するステップであって、前記プロセッサは、線形および非線形の命令の1つまたは複数で構成された命令セットを持つステップ
を含み、
前記1つまたは複数のデジタル・フロントエンド(DFE)機能は、デジタル・プリディストーション機能を含み、前記1つまたは複数の専門化された命令は、1つまたは複数のユーザ定義の非線形の命令を含み、前記1つまたは複数のユーザ定義の非線形の命令は、少なくとも1つのユーザに指定されたパラメータを含み、
少なくとも1つのユーザに指定されたパラメータを持つ少なくとも1つの非線形関数に対するソフトウェア命令の少なくとも1つに応じて、
入力値xに前記非線形関数を適用するために前記少なくとも1つのソフトウェア命令を実装する少なくとも1つの機能単位を呼び出すステップと、
前記入力値xの前記非線形関数に対応する出力を生成するステップと
が実行され、
前記ユーザに指定されたパラメータは、有限数の入力値に対する前記非線形関数の値を格納するルックアップ・テーブルを含み、望まれる入力値xが前記ルックアップ・テーブルにない場合、結果を得るためにハードウェアで直線補間が実行される、
方法。 - 前記専門化された命令は、ベクトル畳み込み関数、復素指数関数、およびベクトルxのxk関数の1つまたは複数を含む請求項1に記載の方法。
- 複数のデータ・サンプルで構成されたサンプルのブロックを形成するステップを含み、前記1つまたは複数のデジタル・フロントエンド(DFE)機能は、サンプルの前記ブロックに対して実行される請求項1または2に記載の方法。
- ソフトウェアで信号に対して1つまたは複数のデジタル・フロントエンド(DFE)機能を実行するためのプロセッサであって、
メモリと、
前記1つまたは複数のデジタル・フロントエンド(DFE)機能を前記信号に対して実行するために、1つまたは複数の専門化された命令を実行するように動作し、前記プロセッサは、線形および非線形の命令の1つまたは複数で構成された命令セットを持つ
前記メモリに結合された少なくとも1つのハードウェア・デバイスと
を含み、
前記1つまたは複数のデジタル・フロントエンド(DFE)機能は、デジタル・プリディストーション機能を含み、前記1つまたは複数の専門化された命令は、1つまたは複数のユーザ定義の非線形の命令を含み、前記1つまたは複数のユーザ定義の非線形の命令は、少なくとも1つのユーザに指定されたパラメータを含み、
少なくとも1つのユーザに指定されたパラメータを持つ少なくとも1つの非線形関数に対するソフトウェア命令の少なくとも1つに応じて、
入力値xに前記非線形関数を適用するために、前記少なくとも1つのソフトウェア命令を実装する少なくとも1つの機能単位を呼び出すステップと、
前記入力値xの前記非線形関数に対応する出力を生成するステップと
が実行され、
前記ユーザに指定されたパラメータは、有限数の入力値に対する前記非線形関数の値を格納するルックアップ・テーブルを含み、望まれる入力値xが前記ルックアップ・テーブルにない場合、結果を得るためにハードウェアで直線補間が実行される、
プロセッサ。 - 前記専門化された命令は、ベクトル畳み込み関数、復素指数関数、およびベクトルxのxk関数の1つまたは複数を含む請求項4に記載のプロセッサ。
- 前記少なくとも1つのハードウェア・デバイスは、複数のデータ・サンプルで構成されたサンプルのブロックを形成するようにさらに構成され、前記1つまたは複数のデジタル・フロントエンド(DFE)機能は、サンプルの前記ブロックに対して実行される請求項4または5に記載のプロセッサ。
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