JP5883984B1 - 発振回路とpll回路と信号処理装置 - Google Patents

発振回路とpll回路と信号処理装置 Download PDF

Info

Publication number
JP5883984B1
JP5883984B1 JP2015230181A JP2015230181A JP5883984B1 JP 5883984 B1 JP5883984 B1 JP 5883984B1 JP 2015230181 A JP2015230181 A JP 2015230181A JP 2015230181 A JP2015230181 A JP 2015230181A JP 5883984 B1 JP5883984 B1 JP 5883984B1
Authority
JP
Japan
Prior art keywords
signal
pulse width
comparison
oscillator
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015230181A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017098799A (ja
Inventor
和好 田倉
和好 田倉
Original Assignee
イメージニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by イメージニクス株式会社 filed Critical イメージニクス株式会社
Priority to JP2015230181A priority Critical patent/JP5883984B1/ja
Application granted granted Critical
Publication of JP5883984B1 publication Critical patent/JP5883984B1/ja
Priority to KR1020160081951A priority patent/KR101716411B1/ko
Priority to CN201610833824.6A priority patent/CN106998204A/zh
Publication of JP2017098799A publication Critical patent/JP2017098799A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H03L7/102Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2015230181A 2015-11-26 2015-11-26 発振回路とpll回路と信号処理装置 Active JP5883984B1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015230181A JP5883984B1 (ja) 2015-11-26 2015-11-26 発振回路とpll回路と信号処理装置
KR1020160081951A KR101716411B1 (ko) 2015-11-26 2016-06-29 발진 회로와 pll 회로와 신호 처리 장치
CN201610833824.6A CN106998204A (zh) 2015-11-26 2016-09-20 振荡电路、pll电路及信号处理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015230181A JP5883984B1 (ja) 2015-11-26 2015-11-26 発振回路とpll回路と信号処理装置

Publications (2)

Publication Number Publication Date
JP5883984B1 true JP5883984B1 (ja) 2016-03-15
JP2017098799A JP2017098799A (ja) 2017-06-01

Family

ID=55457001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015230181A Active JP5883984B1 (ja) 2015-11-26 2015-11-26 発振回路とpll回路と信号処理装置

Country Status (3)

Country Link
JP (1) JP5883984B1 (ko)
KR (1) KR101716411B1 (ko)
CN (1) CN106998204A (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107835013A (zh) * 2017-12-08 2018-03-23 成都前锋电子仪器有限责任公司 一种用于脉冲码型发生器的定时电路

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784625A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd Phase synchronizing oscillator
JPS61167222A (ja) * 1985-01-21 1986-07-28 Hitachi Ltd 位相同期回路
JPS6278917A (ja) * 1985-10-02 1987-04-11 Hitachi Ltd 位相同期回路
JPH0235538U (ko) * 1988-08-30 1990-03-07
JPH10256901A (ja) * 1997-03-14 1998-09-25 Toshiba Corp 位相同期回路及び記録再生装置
JP2007088898A (ja) * 2005-09-22 2007-04-05 Rohm Co Ltd クロック生成回路、およびそれを搭載した電子機器
JP2013062574A (ja) * 2011-09-12 2013-04-04 New Japan Radio Co Ltd Pll回路およびそのキャリブレーション方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09284132A (ja) 1996-04-15 1997-10-31 Matsushita Electric Ind Co Ltd Pll回路
JP2009159038A (ja) * 2007-12-25 2009-07-16 Hitachi Ltd Pll回路
JP2012010308A (ja) * 2010-05-24 2012-01-12 Panasonic Corp リファレンスリークの発生や位相ノイズを低減できるpll回路
JP2013197692A (ja) * 2012-03-16 2013-09-30 Yokogawa Electric Corp Pllクロック発生回路
JP5872949B2 (ja) * 2012-04-16 2016-03-01 ラピスセミコンダクタ株式会社 Pll周波数シンセサイザ、半導体集積装置及び無線通信機器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784625A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd Phase synchronizing oscillator
JPS61167222A (ja) * 1985-01-21 1986-07-28 Hitachi Ltd 位相同期回路
JPS6278917A (ja) * 1985-10-02 1987-04-11 Hitachi Ltd 位相同期回路
JPH0235538U (ko) * 1988-08-30 1990-03-07
JPH10256901A (ja) * 1997-03-14 1998-09-25 Toshiba Corp 位相同期回路及び記録再生装置
JP2007088898A (ja) * 2005-09-22 2007-04-05 Rohm Co Ltd クロック生成回路、およびそれを搭載した電子機器
JP2013062574A (ja) * 2011-09-12 2013-04-04 New Japan Radio Co Ltd Pll回路およびそのキャリブレーション方法

Also Published As

Publication number Publication date
JP2017098799A (ja) 2017-06-01
KR101716411B1 (ko) 2017-03-14
CN106998204A (zh) 2017-08-01

Similar Documents

Publication Publication Date Title
JP5305935B2 (ja) デジタルフェーズロックドループ回路
EP2797235B1 (en) Phase-locked loop device with managed transition to random noise operation mode
JP2011205338A (ja) 局部発振器
JP5883984B1 (ja) 発振回路とpll回路と信号処理装置
WO2020012557A1 (ja) 位相同期回路
JP2017108254A (ja) 位相同期回路及び位相同期方法
JP2011244120A5 (ko)
JP2011254218A (ja) 位相差検出回路、定遅延時間周波数分周回路、および位相同期回路
KR101722860B1 (ko) 신호의 상승 에지와 하강 에지를 이용하여 높은 대역폭을 가지는 디지털 위상 동기 루프
JP4805547B2 (ja) 位相同期回路のジッタ検出回路
JP2013165390A (ja) クロック発生回路
JP2013197692A (ja) Pllクロック発生回路
JP2010273185A (ja) デジタルフェーズロックドループ回路
JP5310135B2 (ja) デジタルpll回路
JP5811914B2 (ja) 位相同期回路および位相比較方法
JP6863373B2 (ja) 検出装置および検出方法
CN107872223B (zh) 用于执行相位误差校正的系统和方法
JP2012244290A (ja) 位相比較回路
KR101107722B1 (ko) 광대역 디지털 주파수 합성기
KR100588221B1 (ko) 디지털 피엘엘
CN107710622B (zh) 一种时钟产生电路及产生时钟信号的方法
JP5213264B2 (ja) Pll回路
JP6453541B2 (ja) クロック生成回路
KR100957027B1 (ko) 위상 고정 검출 회로 및 이를 포함한 위상 고정 루프
JP2018074312A (ja) 周波数検出器及びクロックデータリカバリ装置

Legal Events

Date Code Title Description
A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20151217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20151225

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160108

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160208

R150 Certificate of patent or registration of utility model

Ref document number: 5883984

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250