JP5873323B2 - 半導体デバイスパッケージを製作するための方法 - Google Patents

半導体デバイスパッケージを製作するための方法 Download PDF

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Publication number
JP5873323B2
JP5873323B2 JP2011277812A JP2011277812A JP5873323B2 JP 5873323 B2 JP5873323 B2 JP 5873323B2 JP 2011277812 A JP2011277812 A JP 2011277812A JP 2011277812 A JP2011277812 A JP 2011277812A JP 5873323 B2 JP5873323 B2 JP 5873323B2
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Prior art keywords
metal layer
patterned
layer
vias
interconnect
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JP2012134500A5 (enExample
JP2012134500A (ja
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ポール・アラン・マックコネリー
アルン・ヴィルパクシャ・ゴウダ
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General Electric Co
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General Electric Co
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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