JP5743907B2 - スルーシリコンビア（ｔｓｖ）内にチップ−チップ間、チップ−ウェハー間及びウェハー−ウェハー間の銅インターコネクトを電着するプロセス - Google Patents

スルーシリコンビア（ｔｓｖ）内にチップ−チップ間、チップ−ウェハー間及びウェハー−ウェハー間の銅インターコネクトを電着するプロセス Download PDF

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JP5743907B2
JP5743907B2 JP2011549685A JP2011549685A JP5743907B2 JP 5743907 B2 JP5743907 B2 JP 5743907B2 JP 2011549685 A JP2011549685 A JP 2011549685A JP 2011549685 A JP2011549685 A JP 2011549685A JP 5743907 B2 JP5743907 B2 JP 5743907B2
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copper
tsv
wafer
ions
layer
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JP2012518084A5 (https=
JP2012518084A (ja
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ロベルト エフ． プライサー
ロベルト エフ． プライサー
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アトテック ドイチェランド ゲーエムベーハー
アトテック ドイチェランド ゲーエムベーハー
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/16—Regeneration of process solutions
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611—Smooth layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/615—Microstructure of the layers, e.g. mixed structure
    • C25D5/617—Crystalline layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
JP2011549685A 2009-02-17 2009-12-16 スルーシリコンビア（ｔｓｖ）内にチップ−チップ間、チップ−ウェハー間及びウェハー−ウェハー間の銅インターコネクトを電着するプロセス Expired - Fee Related JP5743907B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/372,113 2009-02-17
US12/372,113 US20100206737A1 (en) 2009-02-17 2009-02-17 Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
PCT/IB2009/007793 WO2010094998A1 (en) 2009-02-17 2009-12-16 Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)

Publications (3)

Publication Number Publication Date
JP2012518084A JP2012518084A (ja) 2012-08-09
JP2012518084A5 JP2012518084A5 (https=) 2013-01-31
JP5743907B2 true JP5743907B2 (ja) 2015-07-01

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JP2011549685A Expired - Fee Related JP5743907B2 (ja) 2009-02-17 2009-12-16 スルーシリコンビア（ｔｓｖ）内にチップ−チップ間、チップ−ウェハー間及びウェハー−ウェハー間の銅インターコネクトを電着するプロセス

Country Status (6)

Country Link
US (1) US20100206737A1 (https=)
EP (1) EP2399281B1 (https=)
JP (1) JP5743907B2 (https=)
CN (1) CN102318041B (https=)
TW (1) TW201034120A (https=)
WO (1) WO2010094998A1 (https=)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7816181B1 (en) * 2009-06-30 2010-10-19 Sandisk Corporation Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby
US9714474B2 (en) * 2010-04-06 2017-07-25 Tel Nexx, Inc. Seed layer deposition in microscale features
US20120024713A1 (en) * 2010-07-29 2012-02-02 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte
US20120056331A1 (en) * 2010-09-06 2012-03-08 Electronics And Telecommunications Research Institute Methods of forming semiconductor device and semiconductor devices formed by the same
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
EP2668317B1 (en) 2011-01-26 2017-08-23 MacDermid Enthone Inc. Process for filling vias in the microelectronics
US8970043B2 (en) 2011-02-01 2015-03-03 Maxim Integrated Products, Inc. Bonded stacked wafers and methods of electroplating bonded stacked wafers
JP5754209B2 (ja) * 2011-03-31 2015-07-29 大日本印刷株式会社 半導体装置の製造方法
US8753981B2 (en) 2011-04-22 2014-06-17 Micron Technology, Inc. Microelectronic devices with through-silicon vias and associated methods of manufacturing
EP2518187A1 (en) * 2011-04-26 2012-10-31 Atotech Deutschland GmbH Aqueous acidic bath for electrolytic deposition of copper
US8691691B2 (en) 2011-07-29 2014-04-08 International Business Machines Corporation TSV pillar as an interconnecting structure
US8894868B2 (en) 2011-10-06 2014-11-25 Electro Scientific Industries, Inc. Substrate containing aperture and methods of forming the same
CN102376641B (zh) * 2011-11-24 2013-07-10 上海华力微电子有限公司 铜填充硅通孔的制作方法
US20130140688A1 (en) * 2011-12-02 2013-06-06 Chun-Hung Chen Through Silicon Via and Method of Manufacturing the Same
CN102569251B (zh) * 2012-02-22 2014-07-02 华进半导体封装先导技术研发中心有限公司 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法
US20130249047A1 (en) * 2012-03-26 2013-09-26 Nanya Technology Corporation Through silicon via structure and method for fabricating the same
CN103378057B (zh) * 2012-04-20 2016-06-29 南亚科技股份有限公司 半导体芯片以及其形成方法
CN103378059B (zh) * 2012-04-27 2016-04-27 南亚科技股份有限公司 穿硅通孔与其形成方法
US9006896B2 (en) * 2012-05-07 2015-04-14 Xintec Inc. Chip package and method for forming the same
CN102703938B (zh) * 2012-06-07 2015-04-22 上海交通大学 硫酸铜电镀液的应力消除剂
CN104396009A (zh) * 2012-06-07 2015-03-04 伦塞勒工艺研究所 用以减少三维集成中硅穿孔(tsv)压力的保角涂层弹性垫的使用
WO2014012381A1 (zh) * 2012-07-17 2014-01-23 上海交通大学 铜互连微柱力学性能原位压缩试样及其制备方法
CN103715132B (zh) * 2012-09-29 2017-12-01 中芯国际集成电路制造(上海)有限公司 金属互连结构的形成方法
US8933564B2 (en) * 2012-12-21 2015-01-13 Intel Corporation Landing structure for through-silicon via
CN103060859B (zh) * 2012-12-27 2015-04-22 建滔（连州）铜箔有限公司 用于改善毛箔毛面锋形的添加剂和电解铜箔生产工艺
CN103103585B (zh) * 2012-12-29 2015-09-16 上海新阳半导体材料股份有限公司 一种用于铜互连的高速凸点电镀方法
EP2754732B1 (en) * 2013-01-15 2015-03-11 ATOTECH Deutschland GmbH Aqueous composition for etching of copper and copper alloys
JP6142880B2 (ja) * 2013-01-15 2017-06-07 三菱瓦斯化学株式会社 シリコンエッチング液およびエッチング方法並びに微小電気機械素子
KR20140094061A (ko) * 2013-01-16 2014-07-30 주식회사 잉크테크 연속 도금 장치 및 연속 도금 방법
US8933562B2 (en) * 2013-01-24 2015-01-13 International Business Machines Corporation In-situ thermoelectric cooling
US9470710B2 (en) 2013-02-27 2016-10-18 Texas Instruments Incorporated Capacitive MEMS sensor devices
CN103280427B (zh) * 2013-06-13 2016-08-10 华进半导体封装先导技术研发中心有限公司 一种tsv正面端部互连工艺
CN103290438B (zh) * 2013-06-25 2015-12-02 深圳市创智成功科技有限公司 用于晶圆级封装的电镀铜溶液及电镀方法
US20160225694A1 (en) * 2013-06-27 2016-08-04 Hans-Joachim Barth High conductivity high frequency via for electronic systems
CN103361681B (zh) * 2013-08-08 2016-11-16 上海新阳半导体材料股份有限公司 能改变tsv微孔镀铜填充方式的添加剂c及包含其的电镀液
US20150069609A1 (en) * 2013-09-12 2015-03-12 International Business Machines Corporation 3d chip crackstop
KR20150057148A (ko) * 2013-11-18 2015-05-28 삼성전자주식회사 반도체 장치
CN103668356B (zh) * 2013-12-17 2016-04-13 上海交通大学 在铜互连硫酸铜镀液中添加Fe2+和Fe3+的电镀方法
CN103695973B (zh) * 2013-12-17 2016-07-06 上海交通大学 在铜互连甲基磺酸铜镀液中添加Fe2+和Fe3+的电镀方法
US9373613B2 (en) * 2013-12-31 2016-06-21 Skyworks Solutions, Inc. Amplifier voltage limiting using punch-through effect
CN104465564B (zh) * 2014-01-06 2017-09-15 昆山西钛微电子科技有限公司 晶圆级芯片tsv封装结构及其封装方法
CN103887232B (zh) * 2014-04-04 2016-08-24 华进半导体封装先导技术研发中心有限公司 改善tsv金属填充均匀性的方法
US9515035B2 (en) 2014-12-19 2016-12-06 International Business Machines Corporation Three-dimensional integrated circuit integration
US9971970B1 (en) * 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
US20170145577A1 (en) * 2015-11-19 2017-05-25 Rohm And Haas Electronic Materials Llc Method of electroplating low internal stress copper deposits on thin film substrates to inhibit warping
FR3046878B1 (fr) * 2016-01-19 2018-05-18 Kobus Sas Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat
CN107706146B (zh) * 2016-08-08 2020-07-28 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法
CN106757191B (zh) * 2016-11-23 2019-10-01 苏州昕皓新材料科技有限公司 一种具有高择优取向的铜晶体颗粒及其制备方法
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US10475808B2 (en) 2017-08-30 2019-11-12 Macronix International Co., Ltd. Three dimensional memory device and method for fabricating the same
CN108615704B (zh) * 2018-03-27 2020-05-08 中国科学院上海微系统与信息技术研究所 一种硅通孔互连的制作工艺、由此形成的硅通孔互连结构及其应用
CN108754555B (zh) * 2018-08-29 2020-04-28 广东天承科技有限公司 一种电镀液及其电镀方法
US10867855B2 (en) 2019-05-13 2020-12-15 Honeywell International Inc. Through silicon via fabrication
EP4018790A1 (en) 2019-08-19 2022-06-29 Atotech Deutschland GmbH & Co. KG Manufacturing sequences for high density interconnect printed circuit boards and a high density interconnect printed circuit board
JP2022545091A (ja) 2019-08-19 2022-10-25 アトテック ドイチェランド ゲーエムベーハー ウント コ カーゲー 銅で充填されたマイクロビアを含む高密度相互接続プリント回路基板の製造方法
CN110453255B (zh) * 2019-08-30 2020-10-09 广州皓悦新材料科技有限公司 一种具有高深镀能力的vcp镀铜光亮剂及其制备方法
CN111041535A (zh) * 2019-12-25 2020-04-21 浙江振有电子股份有限公司 一种连续移动式电镀通孔双面板的方法
CN111155152B (zh) * 2019-12-26 2022-11-01 西安泰金工业电化学技术有限公司 一种用于pcb水平电镀工序中降低生产成本的方法
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CN112018078B (zh) * 2020-07-29 2022-10-25 复旦大学 一种铜互连结构及其制作方法
CN112151504B (zh) * 2020-08-17 2022-04-29 复旦大学 一种带有封孔层的铜互连结构及其制备方法
CN113174620B (zh) * 2021-04-22 2022-05-03 浙江集迈科微电子有限公司 一种镀液流速加强型tsv金属柱的电镀方法
FI20215520A1 (en) * 2021-05-04 2022-11-05 Iqm Finland Oy Superconducting vias in the substrate
CN115621193B (zh) * 2021-07-14 2026-03-31 长鑫存储技术有限公司 半导体结构及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4344387C2 (de) * 1993-12-24 1996-09-05 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Kupfer und Anordnung zur Durchführung des Verfahrens
DE19545231A1 (de) * 1995-11-21 1997-05-22 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Metallschichten
DE19653681C2 (de) * 1996-12-13 2000-04-06 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Kupferschichten mit gleichmäßiger Schichtdicke und guten optischen und metallphysikalischen Eigenschaften und Anwendung des Verfahrens
BR0007639A (pt) * 1999-01-21 2001-11-06 Atotech Deutschland Gmbh Processo para formação galvânica de estruturas condutoras de cobre de alta pureza na produção de circuitos integrados
US20040045832A1 (en) * 1999-10-14 2004-03-11 Nicholas Martyak Electrolytic copper plating solutions
JP2001267726A (ja) * 2000-03-22 2001-09-28 Toyota Autom Loom Works Ltd 配線基板の電解メッキ方法及び配線基板の電解メッキ装置
JP2004119606A (ja) * 2002-09-25 2004-04-15 Canon Inc 半導体基板の貫通孔埋め込み方法および半導体基板
DE10311575B4 (de) * 2003-03-10 2007-03-22 Atotech Deutschland Gmbh Verfahren zum elektrolytischen Metallisieren von Werkstücken mit Bohrungen mit einem hohen Aspektverhältnis
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
JP4456027B2 (ja) * 2005-03-25 2010-04-28 Ｏｋｉセミコンダクタ株式会社 貫通導電体の製造方法
JP5073736B2 (ja) * 2006-03-30 2012-11-14 アトテック・ドイチュラント・ゲーエムベーハー 孔及びキャビティの金属による電解充填法
KR100945504B1 (ko) * 2007-06-26 2010-03-09 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7825517B2 (en) * 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
KR101185886B1 (ko) * 2007-07-23 2012-09-25 삼성전자주식회사 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US7902069B2 (en) * 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
TWI341554B (en) * 2007-08-02 2011-05-01 Enthone Copper metallization of through silicon via
US7776741B2 (en) * 2008-08-18 2010-08-17 Novellus Systems, Inc. Process for through silicon via filing

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JP2012518084A (ja) 2012-08-09
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