BR0007639A - Processo para formação galvânica de estruturas condutoras de cobre de alta pureza na produção de circuitos integrados - Google Patents

Processo para formação galvânica de estruturas condutoras de cobre de alta pureza na produção de circuitos integrados

Info

Publication number
BR0007639A
BR0007639A BR0007639-2A BR0007639A BR0007639A BR 0007639 A BR0007639 A BR 0007639A BR 0007639 A BR0007639 A BR 0007639A BR 0007639 A BR0007639 A BR 0007639A
Authority
BR
Brazil
Prior art keywords
copper
semiconductor substrates
integrated circuits
electrolytic
production
Prior art date
Application number
BR0007639-2A
Other languages
English (en)
Inventor
Heinrich Meyer
Andreas Thies
Original Assignee
Atotech Deutschland Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19915146A external-priority patent/DE19915146C1/de
Application filed by Atotech Deutschland Gmbh filed Critical Atotech Deutschland Gmbh
Publication of BR0007639A publication Critical patent/BR0007639A/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electroplating And Plating Baths Therefor (AREA)

Abstract

Patente de Invenção: "PROCESSO PARA FORMAçãO GALVâNICA DE ESTRUTURAS CONDUTORAS DE COBRE DE ALTA PUREZA NA PRODUçãO DE CIRCUITOS INTEGRADOS". A invenção refere-se a um processo para a formação galvânica de estruturas condutoras de cobre de alta pureza sobre superfícies de substratos semicondutores (wafers) 1, dotadas de cavidades 2, na produção de circuitos integrados. O processo compreende os seguintes passos de processo: a. revestimento das superfícies dos substratos semicondutores 1, dotadas de cavidades 2, com uma camada metálica básica de superfície total, para obter uma condutibilidade suficiente para a precipitação galvânica; b. precipitação em superfície total de camadas de cobre 3 com espessura de camada uniforme sobre a camada metálica básica com um processo de precipitação metálica, por contato dos substratos semicondutores com um banho de precipitação de cobre, sendo que o banho de precipitação de cobre contém pelo menos uma fonte de íons de cobre, pelo menos um composto de aditivo, para controle das propriedades físico-mecânicas das camadas de cobre, bem como compostos de Fe(II) e/ou Fe(III) e sendo que entre os substratos semicondutores e os contra-eletrodos de dimensões estáveis, insolúveis no banho, e postos em contato com o mesmo, é aplicada uma tensão elétrica, de modo que entre os substratos semicondutores 1 e os contra-eletrodos corre uma corrente elétrica; c) estruturação da camada de cobre 3.
BR0007639-2A 1999-01-21 2000-01-11 Processo para formação galvânica de estruturas condutoras de cobre de alta pureza na produção de circuitos integrados BR0007639A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19903178 1999-01-21
DE19915146A DE19915146C1 (de) 1999-01-21 1999-03-26 Verfahren zum galvanischen Bilden von Leiterstrukturen aus hochreinem Kupfer bei der Herstellung von integrierten Schaltungen
PCT/DE2000/000133 WO2000044042A1 (de) 1999-01-21 2000-01-11 Verfahren zum galvanischen bilden von leiterstrukturen aus hochreinem kupfer bei der herstellung von integrierten schaltungen

Publications (1)

Publication Number Publication Date
BR0007639A true BR0007639A (pt) 2001-11-06

Family

ID=26051508

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0007639-2A BR0007639A (pt) 1999-01-21 2000-01-11 Processo para formação galvânica de estruturas condutoras de cobre de alta pureza na produção de circuitos integrados

Country Status (11)

Country Link
US (1) US6793795B1 (pt)
EP (1) EP1153430B1 (pt)
JP (1) JP3374130B2 (pt)
CN (1) CN1137511C (pt)
AT (1) ATE282248T1 (pt)
AU (1) AU3143500A (pt)
BR (1) BR0007639A (pt)
CA (1) CA2359473A1 (pt)
HK (1) HK1039683B (pt)
TW (1) TW464989B (pt)
WO (1) WO2000044042A1 (pt)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605204B1 (en) * 1999-10-14 2003-08-12 Atofina Chemicals, Inc. Electroplating of copper from alkanesulfonate electrolytes
WO2002031228A1 (en) * 2000-10-10 2002-04-18 Learonal Japan Inc. Copper electroplating using insoluble anode
US6736954B2 (en) * 2001-10-02 2004-05-18 Shipley Company, L.L.C. Plating bath and method for depositing a metal layer on a substrate
DE10232612B4 (de) * 2002-07-12 2006-05-18 Atotech Deutschland Gmbh Vorrichtung und Verfahren zur Überwachung eines elektrolytischen Prozesses
EP1475463B2 (en) * 2002-12-20 2017-03-01 Shipley Company, L.L.C. Reverse pulse plating method
US20050082172A1 (en) * 2003-10-21 2005-04-21 Applied Materials, Inc. Copper replenishment for copper plating with insoluble anode
JP4973829B2 (ja) * 2004-07-23 2012-07-11 上村工業株式会社 電気銅めっき浴及び電気銅めっき方法
DE102004045451B4 (de) 2004-09-20 2007-05-03 Atotech Deutschland Gmbh Galvanisches Verfahren zum Füllen von Durchgangslöchern mit Metallen, insbesondere von Leiterplatten mit Kupfer
JP4799887B2 (ja) * 2005-03-24 2011-10-26 石原薬品株式会社 電気銅メッキ浴、並びに銅メッキ方法
US20070238265A1 (en) * 2005-04-05 2007-10-11 Keiichi Kurashina Plating apparatus and plating method
CN100431106C (zh) * 2005-09-26 2008-11-05 财团法人工业技术研究院 形成纳米碳管与金属复合材料的电镀互连导线的方法
EP2000013B1 (de) * 2006-03-30 2010-10-13 ATOTECH Deutschland GmbH Elektrolytisches verfahren zum füllen von löchern und vertiefungen mit metallen
TWI341554B (en) * 2007-08-02 2011-05-01 Enthone Copper metallization of through silicon via
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
US20110056838A1 (en) * 2009-09-04 2011-03-10 Ibiden, Co., Ltd. Method of manufacturing printed wiring board
EP2392694A1 (en) 2010-06-02 2011-12-07 ATOTECH Deutschland GmbH Method for etching of copper and copper alloys
US8973538B2 (en) * 2010-06-18 2015-03-10 Caterpillar Inc. Inline engine having side-mounted heat exchangers
US20120024713A1 (en) * 2010-07-29 2012-02-02 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte
CN103492617B (zh) 2011-01-26 2017-04-19 恩索恩公司 填充微电子器件中的孔的方法
US8970043B2 (en) * 2011-02-01 2015-03-03 Maxim Integrated Products, Inc. Bonded stacked wafers and methods of electroplating bonded stacked wafers
CN103179806B (zh) * 2011-12-21 2019-05-28 奥特斯有限公司 组合的通孔镀覆和孔填充的方法
CN103290438B (zh) * 2013-06-25 2015-12-02 深圳市创智成功科技有限公司 用于晶圆级封装的电镀铜溶液及电镀方法
CN103668356B (zh) * 2013-12-17 2016-04-13 上海交通大学 在铜互连硫酸铜镀液中添加Fe2+和Fe3+的电镀方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666567A (en) * 1981-07-31 1987-05-19 The Boeing Company Automated alternating polarity pulse electrolytic processing of electrically conductive substances
GB8801827D0 (en) * 1988-01-27 1988-02-24 Jct Controls Ltd Improvements in electrochemical processes
DE4344387C2 (de) * 1993-12-24 1996-09-05 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Kupfer und Anordnung zur Durchführung des Verfahrens
DE19545231A1 (de) * 1995-11-21 1997-05-22 Atotech Deutschland Gmbh Verfahren zur elektrolytischen Abscheidung von Metallschichten
US5893966A (en) * 1997-07-28 1999-04-13 Micron Technology, Inc. Method and apparatus for continuous processing of semiconductor wafers
EP1019954B1 (en) * 1998-02-04 2013-05-15 Applied Materials, Inc. Method and apparatus for low-temperature annealing of electroplated copper micro-structures in the production of a microelectronic device
KR100616198B1 (ko) * 1998-04-21 2006-08-25 어플라이드 머티어리얼스, 인코포레이티드 기판상에 전기도금하는 전기화학적 증착 시스템 및 방법
US6596148B1 (en) * 1999-08-04 2003-07-22 Mykrolis Corporation Regeneration of plating baths and system therefore

Also Published As

Publication number Publication date
CN1137511C (zh) 2004-02-04
HK1039683A1 (en) 2002-05-03
EP1153430A1 (de) 2001-11-14
JP3374130B2 (ja) 2003-02-04
CN1337064A (zh) 2002-02-20
AU3143500A (en) 2000-08-07
ATE282248T1 (de) 2004-11-15
EP1153430B1 (de) 2004-11-10
HK1039683B (zh) 2005-05-06
WO2000044042A1 (de) 2000-07-27
CA2359473A1 (en) 2000-07-27
TW464989B (en) 2001-11-21
JP2002535494A (ja) 2002-10-22
US6793795B1 (en) 2004-09-21

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 3A, 4A, 5A, 6A, 7A E 8A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1925 DE 27/11/2007.