JP5675105B2 - 改良形書込み動作を行う２ポートｓｒａｍ - Google Patents

改良形書込み動作を行う２ポートｓｒａｍ Download PDF

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Publication number
JP5675105B2
JP5675105B2 JP2009537251A JP2009537251A JP5675105B2 JP 5675105 B2 JP5675105 B2 JP 5675105B2 JP 2009537251 A JP2009537251 A JP 2009537251A JP 2009537251 A JP2009537251 A JP 2009537251A JP 5675105 B2 JP5675105 B2 JP 5675105B2
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power supply
coupled
voltage
storage node
word line
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Japanese (ja)
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JP2010510615A5 (enExample
JP2010510615A (ja
Inventor
シー． アベルン、グレン
シー． アベルン、グレン
ディー． バーネット、ジェームズ
ディー． バーネット、ジェームズ
エヌ． ハー、ローレンス
エヌ． ハー、ローレンス
エム． ヒグマン、ジャック
エム． ヒグマン、ジャック
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP2009537251A 2006-11-17 2007-09-27 改良形書込み動作を行う２ポートｓｒａｍ Expired - Fee Related JP5675105B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/561,206 2006-11-17
US11/561,206 US7440313B2 (en) 2006-11-17 2006-11-17 Two-port SRAM having improved write operation
PCT/US2007/079709 WO2008063741A2 (en) 2006-11-17 2007-09-27 Two-port sram having improved write operation

Related Child Applications (1)

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JP2013203039A Division JP2013257937A (ja) 2006-11-17 2013-09-30 改良形書込み動作を行う２ポートｓｒａｍとその動作方法

Publications (3)

Publication Number Publication Date
JP2010510615A JP2010510615A (ja) 2010-04-02
JP2010510615A5 JP2010510615A5 (enExample) 2010-11-11
JP5675105B2 true JP5675105B2 (ja) 2015-02-25

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JP2009537251A Expired - Fee Related JP5675105B2 (ja) 2006-11-17 2007-09-27 改良形書込み動作を行う２ポートｓｒａｍ
JP2013203039A Pending JP2013257937A (ja) 2006-11-17 2013-09-30 改良形書込み動作を行う２ポートｓｒａｍとその動作方法

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JP2013203039A Pending JP2013257937A (ja) 2006-11-17 2013-09-30 改良形書込み動作を行う２ポートｓｒａｍとその動作方法

Country Status (5)

Country Link
US (1) US7440313B2 (enExample)
JP (2) JP5675105B2 (enExample)
CN (1) CN101529521B (enExample)
TW (1) TW200823901A (enExample)
WO (1) WO2008063741A2 (enExample)

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US7864600B2 (en) * 2008-06-19 2011-01-04 Texas Instruments Incorporated Memory cell employing reduced voltage
JP5260180B2 (ja) * 2008-08-20 2013-08-14 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7835175B2 (en) * 2008-10-13 2010-11-16 Mediatek Inc. Static random access memories and access methods thereof
US7852661B2 (en) * 2008-10-22 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Write-assist SRAM cell
JP4857367B2 (ja) * 2009-07-06 2012-01-18 株式会社沖データ 駆動回路及び画像形成装置
US8432724B2 (en) * 2010-04-02 2013-04-30 Altera Corporation Memory elements with soft error upset immunity
CN101877243B (zh) * 2010-04-22 2015-09-30 上海华虹宏力半导体制造有限公司 静态随机存取存储器
CN101819815B (zh) * 2010-04-29 2015-05-20 上海华虹宏力半导体制造有限公司 一种消除读取干扰的静态随机存储器
TWI464745B (zh) * 2010-07-06 2014-12-11 Faraday Tech Corp 具有由資料控制之電源供應的靜態隨機存取記憶體
US8824230B2 (en) * 2011-09-30 2014-09-02 Qualcomm Incorporated Method and apparatus of reducing leakage power in multiple port SRAM memory cell
TWI480871B (zh) * 2012-02-22 2015-04-11 Nat Univ Chung Hsing Static random access memory
US9111600B2 (en) * 2012-03-30 2015-08-18 Intel Corporation Memory cell with improved write margin
US9153304B2 (en) * 2012-06-28 2015-10-06 Jaydeep P. Kulkarni Apparatus for reducing write minimum supply voltage for memory
US8817528B2 (en) * 2012-08-17 2014-08-26 Globalfoundries Inc. Device comprising a plurality of static random access memory cells and method of operation thereof
US8804437B2 (en) * 2012-09-25 2014-08-12 Nvidia Corporation Column select multiplexer and method for static random-access memory and computer memory subsystem employing the same
US8913456B2 (en) 2012-10-26 2014-12-16 Freescale Semiconductor, Inc. SRAM with improved write operation
US9224453B2 (en) * 2013-03-13 2015-12-29 Qualcomm Incorporated Write-assisted memory with enhanced speed
CN105340018B (zh) * 2013-07-02 2018-05-08 株式会社索思未来 半导体存储装置
US9281056B2 (en) * 2014-06-18 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Static random access memory and method of using the same
US9336864B2 (en) * 2014-08-29 2016-05-10 Qualcomm Incorporated Silicon germanium read port for a static random access memory register file
US9230637B1 (en) 2014-09-09 2016-01-05 Globalfoundries Inc. SRAM circuit with increased write margin
US9484084B2 (en) * 2015-02-13 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Pulling devices for driving data lines
US10026456B2 (en) 2015-02-23 2018-07-17 Qualcomm Incorporated Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor (PFET) write port(s), and related systems and methods
US9741452B2 (en) 2015-02-23 2017-08-22 Qualcomm Incorporated Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods
CN106445831A (zh) * 2015-08-11 2017-02-22 深圳市中兴微电子技术有限公司 一种存储单元和处理系统
US11170844B1 (en) * 2020-07-07 2021-11-09 Aril Computer Corporation Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines

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US6118689A (en) * 1999-10-27 2000-09-12 Kuo; James B. Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
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Also Published As

Publication number Publication date
US7440313B2 (en) 2008-10-21
JP2013257937A (ja) 2013-12-26
TW200823901A (en) 2008-06-01
WO2008063741A2 (en) 2008-05-29
US20080117665A1 (en) 2008-05-22
JP2010510615A (ja) 2010-04-02
WO2008063741A3 (en) 2008-07-24
CN101529521B (zh) 2012-05-23
CN101529521A (zh) 2009-09-09

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