Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/419—Read-write [R-W] circuits

Definitions

• the present invention relates generally to memories, and more particularly, to a static random access (SRAM) memory having an improved write operation.
• SRAM static random access
• Static random access memories are generally used in applications requiring high speed, such as memory in a data processing system.
• Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters.
• the SRAM cell is only stable in one of two possible voltage levels.
• the logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input.
• the stability of a SRAM cell is an important issue.
• the SRAM cell must be stable against transients, process variations, soft errors, and power supply fluctuations which may cause the cell to inadvertently change logic states.
• the SRAM cell should ideally provide good stability during read operations without harming speed or the ability to write to the cell.
• a two-port SRAM cell has a write word line and a read word line.
• a read port of the SRAM cell may include a pair of series-connected MOS (metal-oxide semiconductor) transistors coupled between a power supply terminal and a read bit line.
• MOS metal-oxide semiconductor
• a gate of one transistor is coupled to a storage node of the cell and the gate of the other transistor is connected to the read word line.
• Low voltage operation is becoming more common for SRAM in portable applications.
• power supply voltages for an active memory cycle may be in the range of one volt or less.
• Providing a low voltage SRAM with adequate write margins and with good cell stability may be difficult and usually comes at the expense of lower read and write performance.
• FIG. 1 illustrates, in block diagram form, a two-port integrated circuit memory in accordance with an embodiment of the present invention
• FIG. 2 illustrates, in schematic diagram form, one embodiment of a memory cell of the memory of FIG. 1;
• FIG. 3 illustrates a timing diagram of various signals of the memory cell of FIG. 2;
• FIG. 4 illustrates, in schematic diagram form, another embodiment of a memory cell of the memory of FIG. 1;
• FIG. 5 illustrates a timing diagram of various signals of the memory cell of FIG. 4.
• bus is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status.
• the conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa.
• plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.
• the present invention provides, in one form, a two-port SRAM memory cell having faster write operations without harming cell stability.
• the two-port memory cell includes a pair of cross-coupled inverters coupled to storage nodes.
• An access transistor is coupled between each storage node and a write bit line and controlled by a write word line.
• the write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters.
• the write word line is asserted and transitions from a logic low voltage (ground) to a logic high voltage.
• a voltage at the power supply terminal of the cross-coupled inverters is raised with the write word line voltage, thus making it easier for the stored logic state at the storage node to change, if necessary.
• the write word line voltage is reduced to ground potential allowing the cross-coupled inverters to function normally and hold the logic state of the storage node.
• the illustrated embodiment provides a two-port memory with the advantage of faster write operations at a lower power supply voltage than the write operations of a standard memory cell, where the standard memory cell has power supply voltage terminals coupled to receive a continuous power supply voltage. Also, the illustrated embodiment provides a two- port memory having the advantage of faster write operations without reducing cell stability.
• a memory cell is coupled to a word line.
• the memory cell comprises a pair of cross-coupled inverters having a first power supply terminal for receiving a first power supply voltage and a second power supply terminal for receiving a second power supply voltage.
• the second power supply terminal is connected to the word line.
• a memory cell is coupled to a word line, the memory cell comprising: a first access transistor coupled to a first storage node and a second access transistor coupled to a second storage node; at least one read port coupled to at least one of the first storage node and the second storage node; a pair of cross-coupled inverters having a first power supply terminal for receiving a first power supply voltage and a second power supply terminal for receiving a second power supply voltage.
• the second power supply terminal is connected to the word line.
• the pair of cross-coupled inverters comprise: a first inverter having an input terminal coupled to the first storage node and an output terminal, and a second inverter having an input terminal coupled to the output terminal of the first inverter and an output terminal coupled to the input terminal of the first inverter at the first storage node.
• a method for accessing a memory comprises at least one memory cell coupled to a word line.
• the at least one memory cell comprises a pair of cross-coupled inverters having a first power supply terminal for receiving a first power supply voltage and a second power supply terminal for receiving a second power supply voltage.
• the method comprises enabling a receipt of a signal on the word line to write a bit for storage into the at least one memory cell, wherein the word line is directly connected to the second power supply terminal.
• FIG. 1 illustrates, in block diagram form, a two-port integrated circuit memory 10 in accordance with an embodiment of the present invention.
• memory 10 includes a plurality of memory cells 12, a row decoder 14, and column logic 16.
• the plurality of memory cells 12 includes representative memory cells 20, 22, 24, 26, 28, 30, 32, 34, and 36. As illustrated in FIG. 1, each of the memory cells is coupled to one of a plurality of write word lines labeled "WWLO" to "WWLN", to one pair of a plurality of pairs of write bit lines labeled "WBL0/WBLB0" to "WBLN/WBLBN", to one of a plurality of read word lines labeled "RWLO” - “RWLN”, and to one of a plurality of read bit lines labeled "RBLO” to "RBLN”.
• the plurality of memory cells 12 are implemented in rows and columns. For example, memory cells 20, 22, and 24 and the word line WWLO form one row of memory cells. Likewise, memory cells 20, 26, and 32 form one column of memory cells.
• the row decoder 14 has an input for receiving a row address labeled "ROW ADDRESS”, and a plurality of output terminals coupled to the plurality of write word lines WWLO to WWLN.
• the read word lines RWLO - RWLN are coupled to row decoder 14.
• the column logic 16 has an input terminal for receiving a column address labeled "COLUMN ADDRESS", a first plurality of terminals coupled to write bit line pairs WBL0/WBLB0 - WBLN/WBLBN, a second plurality of terminals coupled to read bit line pairs RBLO - RBLN, and a plurality of input/ output (I/O) terminals for receiving or providing data signals labeled "DATA”. As illustrated in FIG.
• Column logic 16 includes, for example, column decoders, sense amplifiers, bit line equalization and precharge circuits, and buffer circuits. Note that in the illustrated embodiment, the sense amplifiers for a read operation are single- ended. In another embodiment not illustrated in FIG. 1, the sense amplifiers may be differential.
• memory 10 is implemented as a cache memory in an integrated circuit data processor. In another embodiment, memory 10 may be a stand-alone integrated circuit memory.
• the column decoders of column logic 16 select which of the memory cells are to receive or provide data. Note that during a write access to the memory 10, all of the memory cells coupled to a selected one of write word lines WWLO to WWLN are enabled to receive data signals from the bit lines. This is because asserting a write word line in the illustrated embodiment disturbs the stored states of all of the memory cells coupled to the write word line. Therefore, an entire row is written during each write operation. In a memory used to store instructions and/or data for use by a processor, it is common for the memory to be organized such that the number of columns is equal to a "cache line". A number of bits equal to the cache line width are accessed during each memory operation. In the illustrated embodiment, the address signals COLUMN ADDRESS determines which memory cells of a row are selected to provide data during a read operation.
• FIG. 2 illustrates, in schematic diagram form, an 8-transistor (8-T) memory cell 20 of the memory of FIG. 1.
• Memory cell 20 is implemented on an integrated circuit using CMOS (complementary metal-oxide semiconductor) transistors.
• Memory cell 20 includes a pair of cross-coupled inverters 40, a read port 42, and access transistors 52 and 54.
• Cross-coupled inverters 40 includes one inverter having P-channel transistor 44 and N-channel transistor 46, and another inverter having P-channel transistor 48 and N-channel transistor 50.
• Read port 42 includes N-channel transistors 56 and 58.
• P-channel transistor 44 has a source (current electrode) connected to a power supply conductor labeled "VDD" at a power supply node 47, a drain (current electrode) connected to a storage node labeled "SNB", and a gate (control electrode) connected to a storage node labeled "SN".
• Power supply conductor VDD is routed over the plurality of memory cells 12 to supply power to the cells.
• N-channel transistor 46 has a drain connected to the drain of P-channel transistor 44, a source connected to a write word line labeled "WWLO" at a power supply node 45, and a gate connected to the gate of P-channel transistor 44.
• P-channel transistor 48 has a source connected to VDD, a drain connected to storage node SN, and a gate connected to storage node SNB. Node that a letter "B" after a signal name indicates that the signal name is a logical complement of a signal having the same name but lacking the "B".
• N-channel transistor 50 has a drain connected to storage node SN, a source connected to write word line WWLO, and a gate connected to the gate of P-channel transistor 48.
• N-channel transistor 52 has a drain/source terminal connected to a write bit line labeled "WBLBO", a drain/source terminal connected to storage node SNB, and a gate connected to write word line WWLO.
• N-channel transistor 54 has a drain/source terminal connected to storage node SN, a drain/source terminal connected to write bit line WBLO, and a gate connected to storage node SN.
• N-channel transistor 56 has a first drain/source terminal connected to a power supply voltage conductor labeled "VSS", a second drain/source terminal, and a gate connected to storage node SN. Power supply conductor VSS is routed over the plurality of memory cells 12 to provide the memory cells with a ground connection.
• N-channel transistor 58 has a first drain/source terminal connected to the first drain/source terminal of transistor 56, a second drain/source terminal connected to a read bit line labeled "RBLO”, and a gate connected to a read word line labeled "RWLO".
• power supply voltage VDD is a positive power supply voltage, for example one volt
• power supply voltage VSS is ground
• the power supply voltages may be different.
• VDD may be ground and VSS may be a negative voltage.
• FIG. 3 illustrates a timing diagram of various signals of the memory cell of FIG. 2 versus time. Read and write operations of memory cell 20 will be discussed with reference to FIG. 1, FIG. 2, and FIG. 3. Note that in the illustrated embodiment, a "logic high” voltage is a positive voltage and a “logic low” voltage is equal to about ground potential. In other embodiments, the voltages may be different.
• a read operation begins at time tO and ends at time tl .
• the write word line WWLO is a logic low, allowing the pair of cross-coupled inverters 40 to maintain the logic state of the storage nodes SN/SNB.
• storage node SN is being maintained as a logic high voltage.
• the read bit line RBLO is precharged to a logic high. In another embodiment, the read bit lines may be precharged to ground or to an intermediate voltage.
• row decoder 14 asserts read word line RWLO as a logic high causing N-channel transistor 58 to become conductive. N-channel transistor 56 is already conductive because storage node SN is storing a logic high.
• Transistors 56 and 58 cause the logic high precharge voltage on the read bit line RBLO to be reduced to a logic low.
• the logic low voltage is provided to a sense amplifier of column logic 16 and is then outputted as a bit of DATA. After a predetermined amount of time, the read operation ends with read word line RWLO returning to a logic low potential.
• the logic low of read word line RWLO causes transistor 58 to become substantially non-conductive, allowing bit line precharge circuitry of column logic 16 to return the potential of read bit line RBLO to a logic high in preparation for another read operation.
• a write operation to memory cell 20 occurs between times tl and t2.
• memory cell 20 Prior to the write operation, memory cell 20 is storing a logic high as illustrated in FIG. 3 by storage nodes SN and SNB being a logic high and a logic low, respectively.
• write bit line WBLO is precharged to a logic high by precharge circuitry of column logic 16 and write word line WWLO is de-asserted as a logic low.
• write word line WWLO is asserted as a logic high by row decoder 14 as illustrated in FIG. 3.
• the logic high write word line WWLO causes access transistors 52 and 54 to be conductive, coupling storage node SN to write bit line WBLO and storage node SNB to write bit line WBLBO.
• the voltage at power supply node 45 is raised to substantially the same voltage as the asserted write word line WWLO, causing the voltage at both storage nodes SN and SNB to initially increase to near a logic high.
• a logic low voltage is to be written to memory cell 20, as indicated by write bit line WBLO being reduced to a logic low after the write word line is asserted.
• the logic state of write bit line WBLO is provided to storage node SN via access transistor 54.
• write bit line WBLBO is provided to storage node SNB via transistor 52 (not illustrated in FIG. 3).
• the logic low voltage of write bit line WBLO causes the voltage of storage node SN to be reduced below the voltage of storage node SNB to a voltage low enough such that when the write word line WWLO is de-asserted, the storage node will be reduced to logic low.
• the write word line WWLO is then de-asserted causing the voltage at power supply node 45 to be reduced to about ground potential, and causing access transistors 52 and 54 to become substantially non-conductive.
• the inverters of the pair of cross-coupled inverters 40 begin to function and the bistable nature of the cross-coupled pair causes the voltage of storage node SN be reduced to a logic low and the voltage of SNB to increase to a logic high.
• the write bit lines WBLO and WBLBO are precharged in preparation for another write operation. The write operation ends at time t2.
• FIG. 3 another read operation occurs between times t2 and t3.
• the read operation begins with the assertion of read word line RWLO.
• Storage nodes SN and SNB are storing a logic low and a logic high, respectively.
• the asserted read word line RWLO causes N-channel transistor 58 to be conductive. Because storage node SN is at a logic low, N-channel transistor 56 remains substantially non-conductive.
• Read bit line RBLO is not coupled to power supply conductor VSS and the logic high voltage of read bit line RBLO is sensed and amplified by a sense amplifier of column logic 16. At time t3, the memory cell is ready for another read or write operation.
• FIG. 4 illustrates, in schematic diagram form, a memory cell 20' of the memory of FIG. 1.
• Memory cell 20' is implemented on an integrated circuit using CMOS (complementary metal-oxide semiconductor) transistors.
• CMOS complementary metal-oxide semiconductor
• Memory cell 20' differs from memory cell 20 in that the access transistors are implemented as P-channel transistors 60 and 62.
• memory cell 20' differs in that the write word line WWLO is coupled to power supply node 47 instead of to power supply node 45.
• the power supply conductor VDD is not necessary in the embodiment of FIG. 4.
• FIG. 5 illustrates a timing diagram of various signals of the memory cell of FIG. 4. Read and write operations of memory cell 20' will be discussed referring to FIG. 1, FIG. 4, and FIG. 5.
• a read operation begins at time tO and ends at time tl .
• the write word line WWLO is a logic high causing P-channel access transistors 60 and 62 to be substantially non-conductive, thus allowing the pair of cross-coupled inverters 40 to maintain the logic state of the storage nodes SN/SNB.
• Storage node SN is being maintained as a logic low voltage.
• the read bit line RBLO is precharged to a logic high. In another embodiment, the read bit lines may be precharged to ground or to an intermediate voltage.
• row decoder 14 asserts read word line RWLO as a logic high causing N-channel transistor 58 to become conductive.
• N-channel transistor 56 is substantially non-conductive because storage node SN is storing a logic low.
• the read bit line RBLO is read by column logic 16 as a logic high.
• the logic high is provided to a sense amplifier of column logic 16 and is then outputted as a bit of DATA.
• the read operation ends with read word line RWLO returning to a logic low potential.
• the logic low of read word line RWLO causes transistor 58 to become substantially non-conductive, allowing bit line precharge circuitry of column logic 16 to return the potential of read bit line RBLO to a logic high, if necessary, in preparation for another read operation.
• a write operation to memory cell 20' occurs between times tl and t2.
• memory cell 20' Prior to the write operation, memory cell 20' is storing a logic low as indicated by storage nodes SN and SNB being a logic low and a logic high, respectively.
• write bit line WBLO is precharged to a logic low voltage by precharge circuitry of column logic 16, and write word line WWLO is de-asserted as a logic high.
• write word line WWLO is asserted as a logic low by row decoder 14 as illustrated in FIG. 5.
• the logic low write word line WWLO causes access transistors 60 and 62 to be conductive, coupling storage node SN to write bit line WBLO and storage node SNB to write bit line WBLBO.
• the voltage at power supply node 47 is lowered to substantially the same voltage as the asserted write word line WWLO, causing the voltage at both storage nodes SN and SNB to initially decrease to near a logic low.
• a logic high voltage is to be written to memory cell 20', as indicated by write bit line WBLO being increased to a logic high after the write word line WWLO is asserted.
• the logic state of write bit line WBLO is provided to storage node SN via access transistor 62.
• write bit line WBLBO is provided to storage node SNB via transistor 60 (not illustrated in FIG. 5).
• the logic high voltage of write bit line WBLO causes the voltage of storage node SN to be increased above the voltage of storage node SNB to a voltage high enough that when the write word line WWLO is de-asserted, the voltage of the storage node SN will be increased to logic high.
• the write word line WWLO is then de-asserted causing the voltage at power supply node 47 to be increase to VDD, and causing access transistors 60 and 62 to become substantially non-conductive.
• the inverters of the pair of cross-coupled inverters 40 begin to function and the bistable nature of the cross-coupled pair causes the voltage of storage node SN be increased to a logic high and the voltage of SNB to decrease to a logic low.
• the write bit lines WBLO and WBLBO are both precharged in preparation for another write operation just prior to time t2. The write operation ends at time t2.
• FIG. 5 another read operation occurs between times t2 and t3.
• the read operation begins with the assertion of read word line RWLO.
• Storage nodes SN and SNB are storing a logic high and a logic low, respectively, before the read operation.
• the asserted read word line RWLO causes N-channel transistor 58 to be conductive. Because storage node SN is at a logic high, N-channel transistor 56 becomes conductive.
• Read bit line RBLO is coupled to power supply conductor VSS via transistors 56 and 58 and the read bit line RBLO is reduced to the voltage of VSS (ground).
• the logic low voltage of read bit line RBLO is sensed and amplified by a sense amplifier of column logic 16. At time t3, the memory cell is ready for another read or write operation.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Static Random-Access Memory (AREA)
• Semiconductor Memories (AREA)

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• 2006
  • 2006-11-17 US US11/561,206 patent/US7440313B2/en not_active Expired - Fee Related
• 2007
  • 2007-09-27 CN CN2007800391696A patent/CN101529521B/zh not_active Expired - Fee Related
  • 2007-09-27 WO PCT/US2007/079709 patent/WO2008063741A2/en not_active Ceased
  • 2007-09-27 JP JP2009537251A patent/JP5675105B2/ja not_active Expired - Fee Related
  • 2007-10-11 TW TW096138041A patent/TW200823901A/zh unknown
• 2013
  • 2013-09-30 JP JP2013203039A patent/JP2013257937A/ja active Pending

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