JP5642473B2 - Ｂｇａ半導体パッケージおよびその製造方法 - Google Patents

Ｂｇａ半導体パッケージおよびその製造方法 Download PDF

Info

Publication number
JP5642473B2
JP5642473B2 JP2010212555A JP2010212555A JP5642473B2 JP 5642473 B2 JP5642473 B2 JP 5642473B2 JP 2010212555 A JP2010212555 A JP 2010212555A JP 2010212555 A JP2010212555 A JP 2010212555A JP 5642473 B2 JP5642473 B2 JP 5642473B2
Authority
JP
Japan
Prior art keywords
microball
semiconductor element
substrate
bga
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010212555A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012069690A (ja
JP2012069690A5 (https=
Inventor
紀幸 木村
紀幸 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2010212555A priority Critical patent/JP5642473B2/ja
Priority to TW100133210A priority patent/TW201232731A/zh
Priority to CN201110281227.4A priority patent/CN102412225B/zh
Priority to US13/200,246 priority patent/US8940629B2/en
Priority to KR1020110095258A priority patent/KR101832494B1/ko
Publication of JP2012069690A publication Critical patent/JP2012069690A/ja
Publication of JP2012069690A5 publication Critical patent/JP2012069690A5/ja
Application granted granted Critical
Publication of JP5642473B2 publication Critical patent/JP5642473B2/ja
Priority to US14/595,476 priority patent/US9245864B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2010212555A 2010-09-22 2010-09-22 Ｂｇａ半導体パッケージおよびその製造方法 Expired - Fee Related JP5642473B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2010212555A JP5642473B2 (ja) 2010-09-22 2010-09-22 Ｂｇａ半導体パッケージおよびその製造方法
TW100133210A TW201232731A (en) 2010-09-22 2011-09-15 Ball grid array semiconductor package and method of manufacturing the same
US13/200,246 US8940629B2 (en) 2010-09-22 2011-09-21 Ball grid array semiconductor package and method of manufacturing the same
KR1020110095258A KR101832494B1 (ko) 2010-09-22 2011-09-21 Ｂｇａ 반도체 패키지 및 그 제조 방법
CN201110281227.4A CN102412225B (zh) 2010-09-22 2011-09-21 Bga半导体封装及其制造方法
US14/595,476 US9245864B2 (en) 2010-09-22 2015-01-13 Ball grid array semiconductor package and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010212555A JP5642473B2 (ja) 2010-09-22 2010-09-22 Ｂｇａ半導体パッケージおよびその製造方法

Publications (3)

Publication Number Publication Date
JP2012069690A JP2012069690A (ja) 2012-04-05
JP2012069690A5 JP2012069690A5 (https=) 2013-08-29
JP5642473B2 true JP5642473B2 (ja) 2014-12-17

Family

ID=45817017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010212555A Expired - Fee Related JP5642473B2 (ja) 2010-09-22 2010-09-22 Ｂｇａ半導体パッケージおよびその製造方法

Country Status (5)

Country Link
US (2) US8940629B2 (https=)
JP (1) JP5642473B2 (https=)
KR (1) KR101832494B1 (https=)
CN (1) CN102412225B (https=)
TW (1) TW201232731A (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102062108B1 (ko) 2013-06-10 2020-01-03 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
AT14221U1 (de) * 2014-05-19 2015-06-15 Tridonic Gmbh & Co Kg Leuchtmittel mit LED und Verfahren zur Montage
TW201602715A (zh) * 2014-07-07 2016-01-16 日立麥克賽爾股份有限公司 配列用遮罩及其製造方法
KR20170020002A (ko) 2015-08-13 2017-02-22 삼성전기주식회사 인쇄회로기판 및 이를 포함한 칩 패키지
IT201700073501A1 (it) * 2017-06-30 2018-12-30 St Microelectronics Srl Prodotto a semiconduttore e corrispondente procedimento
JP7063718B2 (ja) * 2018-05-17 2022-05-09 エイブリック株式会社 プリモールド基板とその製造方法および中空型半導体装置とその製造方法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
JP3632930B2 (ja) 1993-12-27 2005-03-30 株式会社ルネサステクノロジ ボールグリッドアレイ半導体装置
JPH08316359A (ja) * 1995-05-16 1996-11-29 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3080579B2 (ja) * 1996-03-06 2000-08-28 富士機工電子株式会社 エアリア・グリッド・アレイ・パッケージの製造方法
JPH1012760A (ja) * 1996-06-24 1998-01-16 Hitachi Cable Ltd 半導体装置
KR100234694B1 (ko) * 1996-10-29 1999-12-15 김영환 비지에이 패키지의 제조방법
US20020106832A1 (en) * 1996-11-26 2002-08-08 Gregory B. Hotchkiss Method and apparatus for attaching solder members to a substrate
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US5950070A (en) * 1997-05-15 1999-09-07 Kulicke & Soffa Investments Method of forming a chip scale package, and a tool used in forming the chip scale package
US6066512A (en) * 1998-01-12 2000-05-23 Seiko Epson Corporation Semiconductor device, method of fabricating the same, and electronic apparatus
JP3876953B2 (ja) * 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JPH11284006A (ja) * 1998-03-31 1999-10-15 Fujitsu Ltd 半導体装置
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6329228B1 (en) * 1999-04-28 2001-12-11 Citizen Watch Co., Ltd. Semiconductor device and method of fabricating the same
JP3398721B2 (ja) * 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
EP1744609B1 (en) * 1999-06-02 2012-12-12 Ibiden Co., Ltd. Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
JP3397725B2 (ja) * 1999-07-07 2003-04-21 沖電気工業株式会社 半導体装置、その製造方法及び半導体素子実装用テープの製造方法
TW512467B (en) * 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
US6400574B1 (en) * 2000-05-11 2002-06-04 Micron Technology, Inc. Molded ball grid array
KR100443504B1 (ko) * 2001-06-12 2004-08-09 주식회사 하이닉스반도체 볼 그리드 어레이 패키지 구조 및 그 제조방법
US6617680B2 (en) * 2001-08-22 2003-09-09 Siliconware Precision Industries Co., Ltd. Chip carrier, semiconductor package and fabricating method thereof
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US7485951B2 (en) * 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
US20050095835A1 (en) * 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
JP2005203390A (ja) * 2004-01-13 2005-07-28 Seiko Instruments Inc 樹脂封止型半導体装置の製造方法
US7205178B2 (en) * 2004-03-24 2007-04-17 Freescale Semiconductor, Inc. Land grid array packaged device and method of forming same
JP4528100B2 (ja) * 2004-11-25 2010-08-18 新光電気工業株式会社 半導体装置及びその製造方法
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
JP4282724B2 (ja) * 2007-02-20 2009-06-24 日本テキサス・インスツルメンツ株式会社 マイクロボールマウンタ用の振込みマスク
JP4809308B2 (ja) * 2007-09-21 2011-11-09 新光電気工業株式会社 基板の製造方法
CN101483163B (zh) * 2008-01-07 2011-11-16 力成科技股份有限公司 窗口型球格阵列封装构造及其基板
JP5588150B2 (ja) * 2009-02-06 2014-09-10 セイコーインスツル株式会社 樹脂封止型半導体装置
JP2010272734A (ja) * 2009-05-22 2010-12-02 Elpida Memory Inc 半導体装置及びその製造方法
JP2011082345A (ja) * 2009-10-07 2011-04-21 Panasonic Corp 半導体装置
US8456021B2 (en) * 2010-11-24 2013-06-04 Texas Instruments Incorporated Integrated circuit device having die bonded to the polymer side of a polymer substrate

Also Published As

Publication number Publication date
JP2012069690A (ja) 2012-04-05
CN102412225A (zh) 2012-04-11
TW201232731A (en) 2012-08-01
CN102412225B (zh) 2016-06-22
KR20120031147A (ko) 2012-03-30
US20150123277A1 (en) 2015-05-07
US9245864B2 (en) 2016-01-26
US20120068340A1 (en) 2012-03-22
KR101832494B1 (ko) 2018-02-26
US8940629B2 (en) 2015-01-27

Similar Documents

Publication Publication Date Title
CN101601133B (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US8569082B2 (en) Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
US8294253B2 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure
US8421199B2 (en) Semiconductor package structure
CN107403765A (zh) 具有可润湿侧面的半导体封装件
US9490224B2 (en) Semiconductor device and manufacturing method thereof
CN103367265B (zh) 多层半导体装置、印刷电路板和多层半导体装置制造方法
JP5642473B2 (ja) Ｂｇａ半導体パッケージおよびその製造方法
CN111863762B (zh) 半导体封装件中的引线稳定化
CN101877334A (zh) 具散热增益的半导体装置
CN206301777U (zh) 半导体封装件
JP2956659B2 (ja) 半導体装置およびそのリードフレーム
CN111199924A (zh) 半导体封装结构及其制作方法
JP2003046055A (ja) 板状体、リードフレームおよび半導体装置の製造方法
JP4018853B2 (ja) ターミナルランドフレーム
KR101168413B1 (ko) 리드 프레임 및 그 제조 방법
JP4705614B2 (ja) 樹脂封止型半導体装置
JPH11274360A (ja) 半導体装置及びその製造方法
JP4409528B2 (ja) 半導体装置
JP2001127195A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法
JPH1197472A (ja) 半導体装置およびその製造方法
JP2000307038A (ja) チップサイズ・パッケージ（ｃｓｐ）及びその作製方法
JP2002237545A (ja) 回路装置の製造方法
JP2000236058A (ja) 半導体装置及びその製造方法
JP2000269389A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130711

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130711

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140415

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140430

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140626

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140722

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140918

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141007

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141029

R150 Certificate of patent or registration of utility model

Ref document number: 5642473

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees