JP5599276B2 - 半導体素子、半導体素子実装体及び半導体素子の製造方法 - Google Patents

半導体素子、半導体素子実装体及び半導体素子の製造方法 Download PDF

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JP5599276B2
JP5599276B2 JP2010213688A JP2010213688A JP5599276B2 JP 5599276 B2 JP5599276 B2 JP 5599276B2 JP 2010213688 A JP2010213688 A JP 2010213688A JP 2010213688 A JP2010213688 A JP 2010213688A JP 5599276 B2 JP5599276 B2 JP 5599276B2
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layer
semiconductor element
mask
conductor layer
post
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Japanese (ja)
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JP2012069761A5 (https=
JP2012069761A (ja
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和貴 小林
直 荒井
孝 栗原
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2010213688A priority Critical patent/JP5599276B2/ja
Priority to US13/223,531 priority patent/US8610268B2/en
Publication of JP2012069761A publication Critical patent/JP2012069761A/ja
Publication of JP2012069761A5 publication Critical patent/JP2012069761A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01215—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/245—Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2010213688A 2010-09-24 2010-09-24 半導体素子、半導体素子実装体及び半導体素子の製造方法 Active JP5599276B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010213688A JP5599276B2 (ja) 2010-09-24 2010-09-24 半導体素子、半導体素子実装体及び半導体素子の製造方法
US13/223,531 US8610268B2 (en) 2010-09-24 2011-09-01 Semiconductor element, semiconductor element mounted board, and method of manufacturing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010213688A JP5599276B2 (ja) 2010-09-24 2010-09-24 半導体素子、半導体素子実装体及び半導体素子の製造方法

Publications (3)

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JP2012069761A JP2012069761A (ja) 2012-04-05
JP2012069761A5 JP2012069761A5 (https=) 2013-07-25
JP5599276B2 true JP5599276B2 (ja) 2014-10-01

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US (1) US8610268B2 (https=)
JP (1) JP5599276B2 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
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US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US10833033B2 (en) 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
US9013037B2 (en) * 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9117820B2 (en) * 2012-08-08 2015-08-25 United Microelectronics Corp. Conductive line of semiconductor device
US9589815B2 (en) * 2012-11-08 2017-03-07 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor IC packaging methods and structures
KR20140100144A (ko) 2013-02-05 2014-08-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9659891B2 (en) 2013-09-09 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a boundary structure, a package on package structure, and a method of making
TWI646639B (zh) * 2013-09-16 2019-01-01 Ｌｇ伊諾特股份有限公司 半導體封裝
US20150262949A1 (en) * 2014-03-14 2015-09-17 Lsi Corporation Method for Fabricating Equal Height Metal Pillars of Different Diameters
JP2016076534A (ja) * 2014-10-03 2016-05-12 イビデン株式会社 金属ポスト付きプリント配線板およびその製造方法
SG11201703125WA (en) * 2014-10-23 2017-05-30 Agency Science Tech & Res Method of bonding a first substrate and a second substrate
JP6510897B2 (ja) * 2015-06-09 2019-05-08 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
CN110517965A (zh) * 2019-08-23 2019-11-29 江苏上达电子有限公司 一种精密线路cof基板金凸块的制造方法
JP2021103733A (ja) * 2019-12-25 2021-07-15 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
WO2026009548A1 (ja) * 2024-07-01 2026-01-08 株式会社村田製作所 回路モジュール及び半田付き回路モジュール

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JPH05218138A (ja) 1992-02-06 1993-08-27 Matsushita Electric Ind Co Ltd フリップチップ実装体
JPH0661233A (ja) * 1992-08-06 1994-03-04 Fujitsu Ltd 半導体装置の製造方法
JPH07201864A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 突起電極形成方法
JP3548814B2 (ja) * 1996-04-03 2004-07-28 カシオ計算機株式会社 突起電極の構造およびその形成方法
JP2891184B2 (ja) * 1996-06-13 1999-05-17 日本電気株式会社 半導体装置及びその製造方法
JPH1041615A (ja) * 1996-07-19 1998-02-13 Matsushita Electric Ind Co Ltd 半導体チップ実装用基板、及び半導体チップの実装方法
JPH11145327A (ja) * 1997-11-07 1999-05-28 Shinko Electric Ind Co Ltd 半導体装置および該半導体装置の実装構造
US6492197B1 (en) * 2000-05-23 2002-12-10 Unitive Electronics Inc. Trilayer/bilayer solder bumps and fabrication methods therefor
JP3860028B2 (ja) * 2001-12-25 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP3861776B2 (ja) * 2002-08-30 2006-12-20 富士通株式会社 半導体装置及びその製造方法
JP5056718B2 (ja) * 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
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US8610268B2 (en) 2013-12-17
US20120074578A1 (en) 2012-03-29
JP2012069761A (ja) 2012-04-05

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