JP5516787B2 - 回路基板 - Google Patents
回路基板 Download PDFInfo
- Publication number
- JP5516787B2 JP5516787B2 JP2013071431A JP2013071431A JP5516787B2 JP 5516787 B2 JP5516787 B2 JP 5516787B2 JP 2013071431 A JP2013071431 A JP 2013071431A JP 2013071431 A JP2013071431 A JP 2013071431A JP 5516787 B2 JP5516787 B2 JP 5516787B2
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- Prior art keywords
- circuit board
- conductor
- axis direction
- external electrode
- insulator layer
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- 239000004020 conductor Substances 0.000 claims description 170
- 239000012212 insulator Substances 0.000 claims description 85
- 238000010030 laminating Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 230000004048 modification Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000005452 bending Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920005992 thermoplastic resin Polymers 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
以下に、本発明の一実施形態に係る回路基板の構成について図面を参照しながら説明する。図1は、本発明の一実施形態に係る回路基板10の外観斜視図である。図2は、図1の回路基板10の分解斜視図である。図3は、図1の回路基板10のA−Aにおける断面構造図である。図4は、図1の回路基板10を積層方向から透視した図である。図1ないし図4において、回路基板10の作製時に、絶縁体層が積層される方向を積層方向と定義する。そして、この積層方向をz軸方向とし、回路基板10の長辺に沿った方向をx軸方向とし、回路基板10の短辺に沿った方向をy軸方向とする。また、回路基板10において、z軸方向の正方向側の面を上面と称し、z軸方向の負方向側の面を下面と称し、その他の面を側面と称す。
以下に、回路基板10の製造方法について図面を参照しながら説明する。まず、一方の主面の全面に銅箔が形成された絶縁体層16を準備する。ここで、絶縁体層16a〜16gでは、銅箔が形成された主面を表面とする。一方、絶縁体層16hでは、銅箔が形成された主面を裏面とする。
回路基板10では、以下に説明するように、プリント配線基板100が変形したとしても、回路基板10がプリント配線基板100から外れることを抑制できる。より詳細には、図10に示す従来の回路基板500及びプリント配線基板600が搭載された電子装置が落下した際の衝撃により、プリント配線基板600に撓みが発生する場合がある。プリント配線基板600に撓みが発生しても、回路基板500は、硬質基板であるので、プリント配線基板600の撓みに追従して大きく変形できない。そのため、外部電極502と外部電極602とを接続しているはんだに負荷がかかる。その結果、はんだが破損して、回路基板500がプリント配線基板600から外れてしまうことがある。
以下に、第1の変形例に係る回路基板10aについて図面を参照しながら説明する。図6は、第1の変形例に係る回路基板10aの分解斜視図である。
G1,G2 グループ
L,L1,L2 コイル
b1〜b17 ビアホール導体
10,10a〜10d 回路基板
11 積層体
12a〜12d,14a〜14f 外部電極
16a〜16h 絶縁体層
18a〜18d,20a〜20f,22a,22b,24a〜24c,28a〜28c,30a〜30f 内部導体
26a〜26d 外部導体
Claims (2)
- 可撓性材料からなる複数の絶縁体層が積層されることにより構成された可撓性を有する積層体と、
前記積層体の内部に設けられたビアホール導体と、
前記ビアホール導体の下側において、該ビアホール導体には接続されておらず、該ビアホール導体に前記絶縁体層を介して対向配置されており、かつ、積層方向から平面視したときに、前記ビアホール導体を内含するように設けられた膜状の導体と、
前記積層体の上面に設けられ、かつ、電子部品が実装される第1の外部電極と、
を備えており、
前記ビアホール導体と重なっている領域において、前記膜状の導体と前記ビアホール導体との間に配置された前記絶縁体層に対してずれが発生し得るように、前記膜状の導体が前記絶縁体層と化学結合していないこと、
を特徴とする回路基板。 - 前記複数の膜状の導体は、前記積層体の積層方向に関する中心面よりも、前記上面側に設けられていること、
を特徴とする請求項1に記載の回路基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013071431A JP5516787B2 (ja) | 2009-04-02 | 2013-03-29 | 回路基板 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009089897 | 2009-04-02 | ||
JP2009089897 | 2009-04-02 | ||
JP2013071431A JP5516787B2 (ja) | 2009-04-02 | 2013-03-29 | 回路基板 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010525957A Division JP5240293B2 (ja) | 2009-04-02 | 2010-02-03 | 回路基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013131777A JP2013131777A (ja) | 2013-07-04 |
JP5516787B2 true JP5516787B2 (ja) | 2014-06-11 |
Family
ID=42827843
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010525957A Expired - Fee Related JP5240293B2 (ja) | 2009-04-02 | 2010-02-03 | 回路基板 |
JP2013071431A Expired - Fee Related JP5516787B2 (ja) | 2009-04-02 | 2013-03-29 | 回路基板 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010525957A Expired - Fee Related JP5240293B2 (ja) | 2009-04-02 | 2010-02-03 | 回路基板 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9136212B2 (ja) |
EP (1) | EP2416355B1 (ja) |
JP (2) | JP5240293B2 (ja) |
KR (1) | KR101473267B1 (ja) |
CN (1) | CN102369600B (ja) |
WO (1) | WO2010113539A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2778670B1 (en) * | 2011-11-07 | 2019-12-18 | Nissan Motor Co., Ltd. | Magnetic body evaluation method |
JP6004078B2 (ja) | 2013-02-15 | 2016-10-05 | 株式会社村田製作所 | 積層回路基板、積層回路基板の製造方法 |
JP2014165210A (ja) * | 2013-02-21 | 2014-09-08 | Fujitsu Component Ltd | モジュール基板 |
USD758372S1 (en) | 2013-03-13 | 2016-06-07 | Nagrastar Llc | Smart card interface |
USD759022S1 (en) * | 2013-03-13 | 2016-06-14 | Nagrastar Llc | Smart card interface |
CN105474762B (zh) * | 2014-02-26 | 2018-05-11 | 株式会社村田制作所 | 多层基板的制造方法及多层基板 |
USD776070S1 (en) * | 2014-03-18 | 2017-01-10 | Sony Corporation | Non-contact type data carrier |
USD864968S1 (en) | 2015-04-30 | 2019-10-29 | Echostar Technologies L.L.C. | Smart card interface |
CN208016129U (zh) * | 2015-09-02 | 2018-10-26 | 株式会社村田制作所 | 树脂电路基板、部件搭载树脂电路基板 |
JP6516023B2 (ja) * | 2016-01-07 | 2019-05-22 | 株式会社村田製作所 | 多層基板、電子機器及び多層基板の製造方法 |
CN208258200U (zh) * | 2016-02-04 | 2018-12-18 | 株式会社村田制作所 | 树脂多层基板 |
US10462901B1 (en) | 2018-07-26 | 2019-10-29 | International Business Machines Corporation | Implementing embedded wire repair for PCB constructs |
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---|---|---|---|---|
CA2059020C (en) * | 1991-01-09 | 1998-08-18 | Kohji Kimbara | Polyimide multilayer wiring board and method of producing same |
JP2551123Y2 (ja) | 1991-07-12 | 1997-10-22 | アルプス電気株式会社 | フレキシブル回路板 |
US6011684A (en) * | 1992-10-21 | 2000-01-04 | Devoe; Alan D. | Monolithic integrated multiple electronic components internally interconnected and externally connected by conductive side castellations to the monolith that are of varying width particularly monolithic multiple capacitors |
US5347258A (en) * | 1993-04-07 | 1994-09-13 | Zycon Corporation | Annular resistor coupled with printed circuit board through-hole |
US5603847A (en) * | 1993-04-07 | 1997-02-18 | Zycon Corporation | Annular circuit components coupled with printed circuit board through-hole |
US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
US6835898B2 (en) * | 1993-11-16 | 2004-12-28 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
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EP2416355A4 (en) | 2012-12-05 |
CN102369600A (zh) | 2012-03-07 |
US9986641B2 (en) | 2018-05-29 |
CN102369600B (zh) | 2014-09-10 |
US9136212B2 (en) | 2015-09-15 |
JPWO2010113539A1 (ja) | 2012-10-04 |
EP2416355A1 (en) | 2012-02-08 |
EP2416355B1 (en) | 2016-12-21 |
KR20110132413A (ko) | 2011-12-07 |
JP5240293B2 (ja) | 2013-07-17 |
US20150342048A1 (en) | 2015-11-26 |
US20120012369A1 (en) | 2012-01-19 |
WO2010113539A1 (ja) | 2010-10-07 |
KR101473267B1 (ko) | 2014-12-16 |
JP2013131777A (ja) | 2013-07-04 |
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