JP5448003B2 - コンピューティングシステムおよびその方法 - Google Patents
コンピューティングシステムおよびその方法 Download PDFInfo
- Publication number
- JP5448003B2 JP5448003B2 JP2011526113A JP2011526113A JP5448003B2 JP 5448003 B2 JP5448003 B2 JP 5448003B2 JP 2011526113 A JP2011526113 A JP 2011526113A JP 2011526113 A JP2011526113 A JP 2011526113A JP 5448003 B2 JP5448003 B2 JP 5448003B2
- Authority
- JP
- Japan
- Prior art keywords
- die
- main board
- package
- dca
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 15
- 238000004891 communication Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 5
- 239000007787 solid Substances 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 28
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000005855 radiation Effects 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000004020 conductor Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
Claims (15)
- メインボードと、
前記メインボードに直接取着されているダイレクト・チップ・アタッチ集積回路ダイ(DCA ICダイ)と、
基板と、前記基板に配設されている第1の集積回路ダイ(ICダイ)とを有し、前記メインボードに取着されており、前記DCA ICダイの少なくとも一部分を被覆しているパッケージと、
前記メインボードに配設されている少なくとも1つの他の部品と、
前記基板に配設されており、前記第1のICダイの上方に積層されている第2のICダイと
を備え、
前記メインボードは、前記DCA ICダイを前記パッケージに結合する少なくとも1つの電気経路と、前記DCA ICダイを前記少なくとも1つの他の部品に結合する少なくとも1つの他の電気経路とを有するコンピューティングシステム。 - 前記第1のICダイおよび前記第2のICダイはそれぞれ、メモリを含む請求項1に記載のコンピューティングシステム。
- 前記パッケージは、ソリッドステートドライブ(SSD)を有する請求項1または2に記載のコンピューティングシステム。
- 前記SSDは、メモリコントローラを含む請求項3に記載のコンピューティングシステム。
- 前記第1のICダイは、前記DCA ICダイに対向している請求項1から4のいずれか一項に記載のコンピューティングシステム。
- 前記DCA ICダイは処理システムを有し、前記パッケージは少なくとも1つのメモリダイを有し、前記少なくとも1つの他の部品は無線通信デバイスを有する請求項1から5のいずれか一項に記載のコンピューティングシステム。
- 前記メインボードに配設されているグラフィクスディスプレイと、
前記メインボードに配設されている電源と
をさらに備え、
前記メインボードは、前記グラフィクスディスプレイと前記DCA ICダイおよび前記パッケージのうち少なくとも1つとを結合する電気経路を有し、前記DCA ICダイおよび前記パッケージを前記電源に電気結合している請求項1から6のいずれか一項に記載のコンピューティングシステム。 - 前記メインボードに配設されているデータ入力デバイスをさらに備える請求項1から7のいずれか一項に記載のコンピューティングシステム。
- 前記パッケージと前記メインボードとの間に配設されているアンダーフィル材料をさらに備える請求項1から8のいずれか一項に記載のコンピューティングシステム。
- ダイレクト・チップ・アタッチ集積回路ダイ(DCA ICダイ)をメインボードに直接取着する段階と、
前記DCA ICダイの少なくとも一部分を被覆する位置にパッケージを置いて、基板と、前記基板に配設されている第1の集積回路ダイ(ICダイ)と、前記第1のICダイの上方に積層して、前記基板に配設する第2のICダイとを有する前記パッケージを前記メインボードに取着する段階と、
前記DCA ICダイと、前記パッケージとの間に、前記メインボード内を通る電気経路を設ける段階と、
前記DCA ICダイと、前記メインボードに配設され、他の部品と結合している端末との間に、前記メインボード内を通る電気経路を設ける段階と
を備える方法。 - 前記端末に部品を電気結合する段階をさらに備える請求項10に記載の方法。
- 前記パッケージを前記メインボードに取着するためのリフロー処理を実行する段階をさらに備え、前記部品は、前記リフロー処理時に前記端末に電気結合される
請求項11に記載の方法。 - 前記DCA ICダイと前記メインボードとの間の空間、および、前記パッケージと前記メインボードとの間の空間にアンダーフィル材料を吐出する段階をさらに備える請求項10から12のいずれか一項に記載の方法。
- 前記アンダーフィル材料は、前記DCA ICダイと前記パッケージとの間の空間を充填する請求項13に記載の方法。
- 前記DCA ICダイを前記メインボードに取着するべく、および、前記パッケージを前記メインボードに取着するべくリフロー処理を1回実行する段階をさらに備える請求項10から14のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/231,965 US10251273B2 (en) | 2008-09-08 | 2008-09-08 | Mainboard assembly including a package overlying a die directly attached to the mainboard |
US12/231,965 | 2008-09-08 | ||
PCT/US2009/055133 WO2010027890A2 (en) | 2008-09-08 | 2009-08-27 | Mainboard assembly including a package overlying a die directly attached to the mainboard |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013195262A Division JP6232681B2 (ja) | 2008-09-08 | 2013-09-20 | コンピューティングシステムおよびその方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012502476A JP2012502476A (ja) | 2012-01-26 |
JP5448003B2 true JP5448003B2 (ja) | 2014-03-19 |
Family
ID=41797795
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011526113A Active JP5448003B2 (ja) | 2008-09-08 | 2009-08-27 | コンピューティングシステムおよびその方法 |
JP2013195262A Active JP6232681B2 (ja) | 2008-09-08 | 2013-09-20 | コンピューティングシステムおよびその方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013195262A Active JP6232681B2 (ja) | 2008-09-08 | 2013-09-20 | コンピューティングシステムおよびその方法 |
Country Status (10)
Country | Link |
---|---|
US (2) | US10251273B2 (ja) |
JP (2) | JP5448003B2 (ja) |
KR (2) | KR20130051517A (ja) |
CN (1) | CN102150262B (ja) |
BR (1) | BRPI0913484B1 (ja) |
DE (1) | DE112009002155B4 (ja) |
GB (1) | GB2475658B (ja) |
RU (1) | RU2480862C2 (ja) |
TW (1) | TWI444120B (ja) |
WO (1) | WO2010027890A2 (ja) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10251273B2 (en) | 2008-09-08 | 2019-04-02 | Intel Corporation | Mainboard assembly including a package overlying a die directly attached to the mainboard |
US8148813B2 (en) * | 2009-07-31 | 2012-04-03 | Altera Corporation | Integrated circuit package architecture |
US9048112B2 (en) | 2010-06-29 | 2015-06-02 | Qualcomm Incorporated | Integrated voltage regulator with embedded passive device(s) for a stacked IC |
KR20120137051A (ko) * | 2011-06-10 | 2012-12-20 | 삼성전자주식회사 | 솔리드 스테이트 드라이브 패키지 및 그의 제조 방법 |
DE112012004185T5 (de) | 2011-10-07 | 2014-06-26 | Volterra Semiconductor Corp. | Leistungsmanagements-Anwendungen von Zwischenverbindungssubstraten |
US9768105B2 (en) * | 2012-04-20 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Rigid interconnect structures in package-on-package assemblies |
US8703539B2 (en) * | 2012-06-29 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple die packaging interposer structure and method |
US9496211B2 (en) | 2012-11-21 | 2016-11-15 | Intel Corporation | Logic die and other components embedded in build-up layers |
US9142477B2 (en) * | 2013-03-08 | 2015-09-22 | Kabushiki Kaisha Toshiba | Semiconductor module |
KR102053349B1 (ko) * | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
EP3050100A4 (en) * | 2013-09-27 | 2017-05-10 | Intel Corporation | Magnetic field shielding for packaging build-up architectures |
US20150286529A1 (en) * | 2014-04-08 | 2015-10-08 | Micron Technology, Inc. | Memory device having controller with local memory |
RU2576666C1 (ru) * | 2014-08-28 | 2016-03-10 | Публичное акционерное общество "Радиофизика" | Способ монтажа мощного полупроводникового элемента |
KR102287396B1 (ko) * | 2014-10-21 | 2021-08-06 | 삼성전자주식회사 | 시스템 온 패키지 모듈과 이를 포함하는 모바일 컴퓨팅 장치 |
JP2017022352A (ja) * | 2015-07-15 | 2017-01-26 | 富士通株式会社 | 半導体装置 |
US10122420B2 (en) | 2015-12-22 | 2018-11-06 | Intel IP Corporation | Wireless in-chip and chip to chip communication |
KR102556052B1 (ko) | 2015-12-23 | 2023-07-14 | 삼성전자주식회사 | 시스템 모듈과 이를 포함하는 모바일 컴퓨팅 장치 |
CN108475671A (zh) * | 2016-02-05 | 2018-08-31 | 英特尔公司 | 用于堆叠引线接合转换的倒装芯片管芯的系统和方法 |
WO2017171850A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Underfilled electronic device package and manufacturing method thereof |
KR102556327B1 (ko) | 2016-04-20 | 2023-07-18 | 삼성전자주식회사 | 패키지 모듈 기판 및 반도체 모듈 |
WO2018190747A1 (ru) * | 2017-04-11 | 2018-10-18 | Леонид Михайлович БЕРЕЩАНСКИЙ | Устройство тревожного оповещения об угрозе личной безопасности |
US10586716B2 (en) | 2017-06-09 | 2020-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
CN107863333A (zh) * | 2017-11-15 | 2018-03-30 | 贵州贵芯半导体有限公司 | 高散热等线距堆栈芯片封装结构及其封装方法 |
CN109817610A (zh) * | 2017-11-21 | 2019-05-28 | 环旭电子股份有限公司 | 半导体封装装置 |
US11081468B2 (en) * | 2019-08-28 | 2021-08-03 | Micron Technology, Inc. | Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses |
CN112616245B (zh) * | 2020-12-14 | 2022-04-19 | 海光信息技术股份有限公司 | 加速处理器加速卡及其制作方法 |
CN113301717A (zh) * | 2021-05-21 | 2021-08-24 | 维沃移动通信有限公司 | 电路板结构以及电子设备 |
Family Cites Families (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03174760A (ja) | 1990-03-29 | 1991-07-29 | Sanyo Electric Co Ltd | 混成集積回路装置 |
US5252857A (en) * | 1991-08-05 | 1993-10-12 | International Business Machines Corporation | Stacked DCA memory chips |
US5313366A (en) * | 1992-08-12 | 1994-05-17 | International Business Machines Corporation | Direct chip attach module (DCAM) |
US5543585A (en) * | 1994-02-02 | 1996-08-06 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
US5525204A (en) * | 1994-09-29 | 1996-06-11 | Motorola, Inc. | Method for fabricating a printed circuit for DCA semiconductor chips |
US5773195A (en) * | 1994-12-01 | 1998-06-30 | International Business Machines Corporation | Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic structures including the cap, and a process of forming the cap and for forming multi-layer electronic structures including the cap |
US5796591A (en) * | 1995-06-07 | 1998-08-18 | International Business Machines Corporation | Direct chip attach circuit card |
US5634268A (en) * | 1995-06-07 | 1997-06-03 | International Business Machines Corporation | Method for making direct chip attach circuit card |
US5769989A (en) * | 1995-09-19 | 1998-06-23 | International Business Machines Corporation | Method and system for reworkable direct chip attach (DCA) structure with thermal enhancement |
JPH09260433A (ja) | 1996-03-22 | 1997-10-03 | Nitto Denko Corp | 半導体装置の製法およびそれによって得られた半導体装置 |
US5940686A (en) * | 1996-04-12 | 1999-08-17 | Conexant Systems, Inc. | Method for manufacturing multi-chip modules utilizing direct lead attach |
US5897336A (en) * | 1996-08-05 | 1999-04-27 | International Business Machines Corporation | Direct chip attach for low alpha emission interconnect system |
US5910644A (en) * | 1997-06-11 | 1999-06-08 | International Business Machines Corporation | Universal surface finish for DCA, SMT and pad on pad interconnections |
JPH113969A (ja) | 1997-06-13 | 1999-01-06 | Matsushita Electric Ind Co Ltd | チップ部品が積層された基板部品 |
US6313522B1 (en) | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
SG75873A1 (en) * | 1998-09-01 | 2000-10-24 | Texas Instr Singapore Pte Ltd | Stacked flip-chip integrated circuit assemblage |
US7233321B1 (en) * | 1998-12-15 | 2007-06-19 | Intel Corporation | Pointing device with integrated audio input |
US6750551B1 (en) * | 1999-12-28 | 2004-06-15 | Intel Corporation | Direct BGA attachment without solder reflow |
US6301121B1 (en) * | 1999-04-05 | 2001-10-09 | Paul T. Lin | Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing process |
US6306688B1 (en) | 1999-04-28 | 2001-10-23 | Teravicta Technologies, Inc. | Method of reworkably removing a fluorinated polymer encapsulant |
US6341418B1 (en) * | 1999-04-29 | 2002-01-29 | International Business Machines Corporation | Method for direct chip attach by solder bumps and an underfill layer |
JP2001207031A (ja) | 2000-01-28 | 2001-07-31 | Nitto Denko Corp | 半導体封止用樹脂組成物及び半導体装置 |
US7102892B2 (en) * | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
US6900534B2 (en) * | 2000-03-16 | 2005-05-31 | Texas Instruments Incorporated | Direct attach chip scale package |
JP2002204053A (ja) | 2001-01-04 | 2002-07-19 | Mitsubishi Electric Corp | 回路実装方法、回路実装基板及び半導体装置 |
TW472372B (en) * | 2001-01-17 | 2002-01-11 | Siliconware Precision Industries Co Ltd | Memory module with direct chip attach and the manufacturing process thereof |
US6730860B2 (en) * | 2001-09-13 | 2004-05-04 | Intel Corporation | Electronic assembly and a method of constructing an electronic assembly |
JP4663184B2 (ja) * | 2001-09-26 | 2011-03-30 | パナソニック株式会社 | 半導体装置の製造方法 |
ES2440770T3 (es) | 2002-02-26 | 2014-01-30 | Legacy Electronics, Inc. | Un soporte modular de microplaquetas de circuitos integrados |
US7294928B2 (en) * | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US6787392B2 (en) * | 2002-09-09 | 2004-09-07 | Semiconductor Components Industries, L.L.C. | Structure and method of direct chip attach |
US6845664B1 (en) * | 2002-10-03 | 2005-01-25 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | MEMS direct chip attach packaging methodologies and apparatuses for harsh environments |
US7034387B2 (en) * | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
JP2004179232A (ja) | 2002-11-25 | 2004-06-24 | Seiko Epson Corp | 半導体装置及びその製造方法並びに電子機器 |
US6861288B2 (en) | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
US6835580B1 (en) * | 2003-06-26 | 2004-12-28 | Semiconductor Components Industries, L.L.C. | Direct chip attach structure and method |
US7144538B2 (en) * | 2003-06-26 | 2006-12-05 | Semiconductor Components Industries, Llc | Method for making a direct chip attach device and structure |
JP2006040870A (ja) | 2004-02-20 | 2006-02-09 | Matsushita Electric Ind Co Ltd | 接続部材および実装体、ならびにその製造方法 |
JP4441328B2 (ja) | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US7218007B2 (en) | 2004-09-28 | 2007-05-15 | Intel Corporation | Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices |
US7817434B2 (en) * | 2004-10-14 | 2010-10-19 | Agere Systems Inc. | Method and apparatus for improving thermal energy dissipation in a direct-chip-attach coupling configuration of an integrated circuit and a circuit board |
US7217994B2 (en) * | 2004-12-01 | 2007-05-15 | Kyocera Wireless Corp. | Stack package for high density integrated circuits |
US7445962B2 (en) * | 2005-02-10 | 2008-11-04 | Stats Chippac Ltd. | Stacked integrated circuits package system with dense routability and high thermal conductivity |
JP4827556B2 (ja) | 2005-03-18 | 2011-11-30 | キヤノン株式会社 | 積層型半導体パッケージ |
US7317256B2 (en) * | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
JP4817892B2 (ja) * | 2005-06-28 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2006013555A (ja) | 2005-09-22 | 2006-01-12 | Oki Electric Ind Co Ltd | 半導体装置 |
TW200740735A (en) | 2006-01-31 | 2007-11-01 | Asahi Kasei Chemicals Corp | Industrial process for production of high-purity diol |
CN101375299B (zh) * | 2006-02-02 | 2012-08-08 | 松下电器产业株式会社 | 存储卡及存储卡的制造方法 |
US7435619B2 (en) * | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US7692295B2 (en) * | 2006-03-31 | 2010-04-06 | Intel Corporation | Single package wireless communication device |
JP5005321B2 (ja) | 2006-11-08 | 2012-08-22 | パナソニック株式会社 | 半導体装置 |
US7619901B2 (en) * | 2007-06-25 | 2009-11-17 | Epic Technologies, Inc. | Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system |
JP2007266640A (ja) | 2007-07-11 | 2007-10-11 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
RU72339U8 (ru) * | 2007-12-27 | 2008-06-10 | Общество с ограниченной ответственностью "НТЦ "Фактор" | Модуль многопроцессорной вычислительной системы (варианты) |
US7901987B2 (en) * | 2008-03-19 | 2011-03-08 | Stats Chippac Ltd. | Package-on-package system with internal stacking module interposer |
US7971347B2 (en) * | 2008-06-27 | 2011-07-05 | Intel Corporation | Method of interconnecting workpieces |
US10251273B2 (en) | 2008-09-08 | 2019-04-02 | Intel Corporation | Mainboard assembly including a package overlying a die directly attached to the mainboard |
-
2008
- 2008-09-08 US US12/231,965 patent/US10251273B2/en active Active
-
2009
- 2009-08-27 JP JP2011526113A patent/JP5448003B2/ja active Active
- 2009-08-27 WO PCT/US2009/055133 patent/WO2010027890A2/en active Application Filing
- 2009-08-27 KR KR1020137011381A patent/KR20130051517A/ko active Search and Examination
- 2009-08-27 DE DE112009002155.7T patent/DE112009002155B4/de active Active
- 2009-08-27 RU RU2011113546/28A patent/RU2480862C2/ru not_active IP Right Cessation
- 2009-08-27 BR BRPI0913484-0A patent/BRPI0913484B1/pt not_active IP Right Cessation
- 2009-08-27 GB GB1104809.7A patent/GB2475658B/en active Active
- 2009-08-27 CN CN2009801350137A patent/CN102150262B/zh active Active
- 2009-08-27 KR KR1020117005490A patent/KR20110039396A/ko active Application Filing
- 2009-08-31 TW TW098129247A patent/TWI444120B/zh active
-
2013
- 2013-09-20 JP JP2013195262A patent/JP6232681B2/ja active Active
-
2019
- 2019-02-20 US US16/281,045 patent/US10555417B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2010027890A3 (en) | 2010-05-20 |
GB2475658A (en) | 2011-05-25 |
JP2014030042A (ja) | 2014-02-13 |
BRPI0913484B1 (pt) | 2019-06-04 |
GB2475658B (en) | 2012-11-28 |
US20100061056A1 (en) | 2010-03-11 |
WO2010027890A2 (en) | 2010-03-11 |
RU2480862C2 (ru) | 2013-04-27 |
BRPI0913484A2 (pt) | 2016-08-30 |
DE112009002155B4 (de) | 2023-10-19 |
CN102150262B (zh) | 2013-02-27 |
KR20110039396A (ko) | 2011-04-15 |
DE112009002155T5 (de) | 2012-01-12 |
KR20130051517A (ko) | 2013-05-20 |
CN102150262A (zh) | 2011-08-10 |
GB201104809D0 (en) | 2011-05-04 |
TW201026184A (en) | 2010-07-01 |
TWI444120B (zh) | 2014-07-01 |
JP6232681B2 (ja) | 2017-11-22 |
JP2012502476A (ja) | 2012-01-26 |
US10555417B2 (en) | 2020-02-04 |
US20190182958A1 (en) | 2019-06-13 |
US10251273B2 (en) | 2019-04-02 |
RU2011113546A (ru) | 2012-10-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6232681B2 (ja) | コンピューティングシステムおよびその方法 | |
US10879219B2 (en) | Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure | |
JP7324351B2 (ja) | フレキシブル回路基板及びこれを含むチップパッケージ | |
JP4395166B2 (ja) | コンデンサを内蔵した半導体装置及びその製造方法 | |
TWI773855B (zh) | 薄膜基板結構、覆晶薄膜封裝以及封裝模組 | |
KR20130073515A (ko) | 반도체 패키지 및 반도체 패키지 제조 방법 | |
CN113169156B (zh) | 电子组件 | |
JP6320681B2 (ja) | 半導体装置 | |
JP2005340292A (ja) | 配線基板及びその製造方法、半導体装置及びその製造方法、電子デバイス並びに電子機器 | |
JP2018113480A (ja) | 半導体装置 | |
JP2009289977A (ja) | 電子部品モジュール | |
CN113169156A (zh) | 电子组件 | |
JP2008124107A (ja) | 配線基板、半導体部品及び配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120608 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120619 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120919 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120926 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121018 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20130521 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130920 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20130924 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20131017 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131126 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131218 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 5448003 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |