RU2011113546A - Системная плата, включающая модуль над кристаллом, непосредственно закрепленным на системной плате - Google Patents
Системная плата, включающая модуль над кристаллом, непосредственно закрепленным на системной плате Download PDFInfo
- Publication number
- RU2011113546A RU2011113546A RU2011113546/28A RU2011113546A RU2011113546A RU 2011113546 A RU2011113546 A RU 2011113546A RU 2011113546/28 A RU2011113546/28 A RU 2011113546/28A RU 2011113546 A RU2011113546 A RU 2011113546A RU 2011113546 A RU2011113546 A RU 2011113546A
- Authority
- RU
- Russia
- Prior art keywords
- board
- chip
- system board
- module
- directly attached
- Prior art date
Links
- 239000013078 crystal Substances 0.000 claims abstract 13
- 239000000758 substrate Substances 0.000 claims abstract 6
- 239000004065 semiconductor Substances 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims 6
- 239000000463 material Substances 0.000 claims 3
- 238000005476 soldering Methods 0.000 claims 3
- 229910000679 solder Inorganic materials 0.000 claims 2
- 238000009434 installation Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
1. Вычислительная система, содержащая: ! системную плату; ! кристалл интегральной схемы, непосредственно закрепленный на системной плате; модуль, закрепленный на системной плате и перекрывающий, по меньшей мере, один участок непосредственно закрепляемого на системной плате кристалла; а также, по меньшей мере, один другой компонент, закрепленный на системной плате; ! которая включает, по меньшей мере, один электрический канал, соединяющий непосредственно закрепляемый на системной плате кристалл с модулем и, по меньшей мере, один электрический канал, соединяющий непосредственно закрепляемый на системной плате кристалл с указанным другим компонентом. ! 2. Система по п.1, в которой модуль содержит: ! подложку; и ! первый кристалл интегральной схемы (ИС), размещенный на подложке. ! 3. Система по п.2, дополнительно содержащая второй кристалл ИС, размещенный на подложке и расположенный над первым кристаллом ИС. ! 4. Система по п.3, в которой и первый кристалл ИС и второй кристалл ИС содержат запоминающее устройство. ! 5. Система по п.4, в которой модуль содержит полупроводниковый диск. ! 6. Система по п.5, в которой полупроводниковый диск включает контроллер памяти. ! 7. Система по п.2, в которой первый кристалл ИС расположен напротив непосредственно закрепляемого на плате кристалла. ! 8. Система по п.1, в которой непосредственно закрепляемый на плате кристалл содержит процессорную систему, модуль включает, по меньшей мере, один кристалл памяти и, по меньшей мере, один другой компонент содержит беспроводное устройство связи. ! 9. Система по п.8, дополнительно содержащая: ! графический дисплей, расположенный на системной плате, системн
Claims (17)
1. Вычислительная система, содержащая:
системную плату;
кристалл интегральной схемы, непосредственно закрепленный на системной плате; модуль, закрепленный на системной плате и перекрывающий, по меньшей мере, один участок непосредственно закрепляемого на системной плате кристалла; а также, по меньшей мере, один другой компонент, закрепленный на системной плате;
которая включает, по меньшей мере, один электрический канал, соединяющий непосредственно закрепляемый на системной плате кристалл с модулем и, по меньшей мере, один электрический канал, соединяющий непосредственно закрепляемый на системной плате кристалл с указанным другим компонентом.
2. Система по п.1, в которой модуль содержит:
подложку; и
первый кристалл интегральной схемы (ИС), размещенный на подложке.
3. Система по п.2, дополнительно содержащая второй кристалл ИС, размещенный на подложке и расположенный над первым кристаллом ИС.
4. Система по п.3, в которой и первый кристалл ИС и второй кристалл ИС содержат запоминающее устройство.
5. Система по п.4, в которой модуль содержит полупроводниковый диск.
6. Система по п.5, в которой полупроводниковый диск включает контроллер памяти.
7. Система по п.2, в которой первый кристалл ИС расположен напротив непосредственно закрепляемого на плате кристалла.
8. Система по п.1, в которой непосредственно закрепляемый на плате кристалл содержит процессорную систему, модуль включает, по меньшей мере, один кристалл памяти и, по меньшей мере, один другой компонент содержит беспроводное устройство связи.
9. Система по п.8, дополнительно содержащая:
графический дисплей, расположенный на системной плате, системная плата включает электрический канал, связывающий графический дисплей, по меньшей мере, с одним непосредственно закрепляемым на плате кристаллом и модулем; а также источник энергии, закрепленный на системной плате, причем системная плата соединяет непосредственно закрепляемый на системной плате кристалл и модуль с источником энергии.
10. Система по п.8, дополнительно содержащая устройство ввода данных, расположенное на системной плате.
11. Система по п.1, дополнительно содержащая подкладочный материал, расположенный между модулем и системной платой.
12. Способ, содержащий:
непосредственное крепление кристалла интегральной схемы (непосредственно закрепляемого на плате) к системной плате;
установку модуля с перекрытием, по меньшей мере, одного участка непосредственно закрепляемого на плате кристалла и крепление модуля к системной плате;
создание электрического канала, проходящего через системную плату между непосредственно закрепляемым на плате кристаллом и модулем;
а также
создание электрического канала, проходящего через системную плату между непосредственно закрепляемым на плате кристаллом и контактом, расположенным на системной плате, контакт предназначен для подключения другого компонента.
13. Способ по п.12, дополнительно содержащий электрическое подсоединение компонента к контакту.
14. Способ по п.13, дополнительно содержащий осуществление операции пайки расплавленного дозированного припоя для крепления модуля к системной плате, в котором компонент электрически соединяется с контактом при выполнении операции пайки.
15. Способ по п.12, дополнительно содержащий нанесение подкладочного материала в пространство между непосредственно закрепляемым на плате кристаллом и системной платой и в пространство между модулем и системной платой.
16. Способ по п.15, в котором подкладочный материал занимает пространство между непосредственно закрепляемым на плате кристаллом и модулем.
17. Способ по п.12, дополнительно содержащий выполнение одиночной операции пайки расплавленного дозированного припоя для крепления непосредственно закрепляемого на плате кристалла к системной плате и крепления модуля к системной плате.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/231,965 | 2008-09-08 | ||
US12/231,965 US10251273B2 (en) | 2008-09-08 | 2008-09-08 | Mainboard assembly including a package overlying a die directly attached to the mainboard |
PCT/US2009/055133 WO2010027890A2 (en) | 2008-09-08 | 2009-08-27 | Mainboard assembly including a package overlying a die directly attached to the mainboard |
Publications (2)
Publication Number | Publication Date |
---|---|
RU2011113546A true RU2011113546A (ru) | 2012-10-20 |
RU2480862C2 RU2480862C2 (ru) | 2013-04-27 |
Family
ID=41797795
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
RU2011113546/28A RU2480862C2 (ru) | 2008-09-08 | 2009-08-27 | Системная плата, включающая модуль над кристаллом, непосредственно закрепленным на системной плате |
Country Status (10)
Country | Link |
---|---|
US (2) | US10251273B2 (ru) |
JP (2) | JP5448003B2 (ru) |
KR (2) | KR20110039396A (ru) |
CN (1) | CN102150262B (ru) |
BR (1) | BRPI0913484B1 (ru) |
DE (1) | DE112009002155B4 (ru) |
GB (1) | GB2475658B (ru) |
RU (1) | RU2480862C2 (ru) |
TW (1) | TWI444120B (ru) |
WO (1) | WO2010027890A2 (ru) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10251273B2 (en) | 2008-09-08 | 2019-04-02 | Intel Corporation | Mainboard assembly including a package overlying a die directly attached to the mainboard |
US8148813B2 (en) * | 2009-07-31 | 2012-04-03 | Altera Corporation | Integrated circuit package architecture |
US9048112B2 (en) * | 2010-06-29 | 2015-06-02 | Qualcomm Incorporated | Integrated voltage regulator with embedded passive device(s) for a stacked IC |
KR20120137051A (ko) * | 2011-06-10 | 2012-12-20 | 삼성전자주식회사 | 솔리드 스테이트 드라이브 패키지 및 그의 제조 방법 |
CN103975427B (zh) * | 2011-10-07 | 2017-03-01 | 沃尔泰拉半导体公司 | 互连衬底的功率管理应用 |
US9768105B2 (en) * | 2012-04-20 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Rigid interconnect structures in package-on-package assemblies |
US8703539B2 (en) * | 2012-06-29 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple die packaging interposer structure and method |
US9496211B2 (en) * | 2012-11-21 | 2016-11-15 | Intel Corporation | Logic die and other components embedded in build-up layers |
US9142477B2 (en) * | 2013-03-08 | 2015-09-22 | Kabushiki Kaisha Toshiba | Semiconductor module |
KR102053349B1 (ko) * | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
US9345184B2 (en) * | 2013-09-27 | 2016-05-17 | Intel Corporation | Magnetic field shielding for packaging build-up architectures |
US20150286529A1 (en) * | 2014-04-08 | 2015-10-08 | Micron Technology, Inc. | Memory device having controller with local memory |
RU2576666C1 (ru) * | 2014-08-28 | 2016-03-10 | Публичное акционерное общество "Радиофизика" | Способ монтажа мощного полупроводникового элемента |
KR102287396B1 (ko) * | 2014-10-21 | 2021-08-06 | 삼성전자주식회사 | 시스템 온 패키지 모듈과 이를 포함하는 모바일 컴퓨팅 장치 |
JP2017022352A (ja) * | 2015-07-15 | 2017-01-26 | 富士通株式会社 | 半導体装置 |
US10122420B2 (en) * | 2015-12-22 | 2018-11-06 | Intel IP Corporation | Wireless in-chip and chip to chip communication |
KR102556052B1 (ko) | 2015-12-23 | 2023-07-14 | 삼성전자주식회사 | 시스템 모듈과 이를 포함하는 모바일 컴퓨팅 장치 |
WO2017135971A1 (en) * | 2016-02-05 | 2017-08-10 | Intel Corporation | System and method for stacking wire-bond converted flip-chip die |
US10672625B2 (en) * | 2016-04-01 | 2020-06-02 | Intel Corporation | Electronic device package with recessed substrate for underfill containment |
KR102556327B1 (ko) | 2016-04-20 | 2023-07-18 | 삼성전자주식회사 | 패키지 모듈 기판 및 반도체 모듈 |
WO2018190747A1 (ru) * | 2017-04-11 | 2018-10-18 | Леонид Михайлович БЕРЕЩАНСКИЙ | Устройство тревожного оповещения об угрозе личной безопасности |
US10586716B2 (en) * | 2017-06-09 | 2020-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
CN107863333A (zh) * | 2017-11-15 | 2018-03-30 | 贵州贵芯半导体有限公司 | 高散热等线距堆栈芯片封装结构及其封装方法 |
CN109817610A (zh) * | 2017-11-21 | 2019-05-28 | 环旭电子股份有限公司 | 半导体封装装置 |
US11081468B2 (en) * | 2019-08-28 | 2021-08-03 | Micron Technology, Inc. | Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses |
CN112616245B (zh) * | 2020-12-14 | 2022-04-19 | 海光信息技术股份有限公司 | 加速处理器加速卡及其制作方法 |
CN113301717A (zh) * | 2021-05-21 | 2021-08-24 | 维沃移动通信有限公司 | 电路板结构以及电子设备 |
Family Cites Families (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03174760A (ja) | 1990-03-29 | 1991-07-29 | Sanyo Electric Co Ltd | 混成集積回路装置 |
US5252857A (en) | 1991-08-05 | 1993-10-12 | International Business Machines Corporation | Stacked DCA memory chips |
US5313366A (en) | 1992-08-12 | 1994-05-17 | International Business Machines Corporation | Direct chip attach module (DCAM) |
US5543585A (en) | 1994-02-02 | 1996-08-06 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
US5525204A (en) | 1994-09-29 | 1996-06-11 | Motorola, Inc. | Method for fabricating a printed circuit for DCA semiconductor chips |
US5773195A (en) | 1994-12-01 | 1998-06-30 | International Business Machines Corporation | Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic structures including the cap, and a process of forming the cap and for forming multi-layer electronic structures including the cap |
US5634268A (en) | 1995-06-07 | 1997-06-03 | International Business Machines Corporation | Method for making direct chip attach circuit card |
US5796591A (en) | 1995-06-07 | 1998-08-18 | International Business Machines Corporation | Direct chip attach circuit card |
US5769989A (en) | 1995-09-19 | 1998-06-23 | International Business Machines Corporation | Method and system for reworkable direct chip attach (DCA) structure with thermal enhancement |
JPH09260433A (ja) | 1996-03-22 | 1997-10-03 | Nitto Denko Corp | 半導体装置の製法およびそれによって得られた半導体装置 |
US5940686A (en) | 1996-04-12 | 1999-08-17 | Conexant Systems, Inc. | Method for manufacturing multi-chip modules utilizing direct lead attach |
US5897336A (en) | 1996-08-05 | 1999-04-27 | International Business Machines Corporation | Direct chip attach for low alpha emission interconnect system |
US5910644A (en) | 1997-06-11 | 1999-06-08 | International Business Machines Corporation | Universal surface finish for DCA, SMT and pad on pad interconnections |
JPH113969A (ja) * | 1997-06-13 | 1999-01-06 | Matsushita Electric Ind Co Ltd | チップ部品が積層された基板部品 |
US6313522B1 (en) | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
SG75873A1 (en) * | 1998-09-01 | 2000-10-24 | Texas Instr Singapore Pte Ltd | Stacked flip-chip integrated circuit assemblage |
US7233321B1 (en) * | 1998-12-15 | 2007-06-19 | Intel Corporation | Pointing device with integrated audio input |
US6750551B1 (en) | 1999-12-28 | 2004-06-15 | Intel Corporation | Direct BGA attachment without solder reflow |
US6301121B1 (en) | 1999-04-05 | 2001-10-09 | Paul T. Lin | Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing process |
US6306688B1 (en) | 1999-04-28 | 2001-10-23 | Teravicta Technologies, Inc. | Method of reworkably removing a fluorinated polymer encapsulant |
US6341418B1 (en) | 1999-04-29 | 2002-01-29 | International Business Machines Corporation | Method for direct chip attach by solder bumps and an underfill layer |
JP2001207031A (ja) | 2000-01-28 | 2001-07-31 | Nitto Denko Corp | 半導体封止用樹脂組成物及び半導体装置 |
US7102892B2 (en) | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
US6900534B2 (en) | 2000-03-16 | 2005-05-31 | Texas Instruments Incorporated | Direct attach chip scale package |
JP2002204053A (ja) | 2001-01-04 | 2002-07-19 | Mitsubishi Electric Corp | 回路実装方法、回路実装基板及び半導体装置 |
TW472372B (en) | 2001-01-17 | 2002-01-11 | Siliconware Precision Industries Co Ltd | Memory module with direct chip attach and the manufacturing process thereof |
US6730860B2 (en) | 2001-09-13 | 2004-05-04 | Intel Corporation | Electronic assembly and a method of constructing an electronic assembly |
JP4663184B2 (ja) | 2001-09-26 | 2011-03-30 | パナソニック株式会社 | 半導体装置の製造方法 |
WO2003073506A2 (en) | 2002-02-26 | 2003-09-04 | Legacy Electronics, Inc. | A modular integrated circuit chip carrier |
US7294928B2 (en) * | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US6787392B2 (en) | 2002-09-09 | 2004-09-07 | Semiconductor Components Industries, L.L.C. | Structure and method of direct chip attach |
US6845664B1 (en) | 2002-10-03 | 2005-01-25 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | MEMS direct chip attach packaging methodologies and apparatuses for harsh environments |
US7034387B2 (en) * | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
JP2004179232A (ja) | 2002-11-25 | 2004-06-24 | Seiko Epson Corp | 半導体装置及びその製造方法並びに電子機器 |
US6861288B2 (en) | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
US7144538B2 (en) | 2003-06-26 | 2006-12-05 | Semiconductor Components Industries, Llc | Method for making a direct chip attach device and structure |
US6835580B1 (en) | 2003-06-26 | 2004-12-28 | Semiconductor Components Industries, L.L.C. | Direct chip attach structure and method |
JP2006040870A (ja) | 2004-02-20 | 2006-02-09 | Matsushita Electric Ind Co Ltd | 接続部材および実装体、ならびにその製造方法 |
JP4441328B2 (ja) | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US7218007B2 (en) | 2004-09-28 | 2007-05-15 | Intel Corporation | Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices |
US7817434B2 (en) | 2004-10-14 | 2010-10-19 | Agere Systems Inc. | Method and apparatus for improving thermal energy dissipation in a direct-chip-attach coupling configuration of an integrated circuit and a circuit board |
US7217994B2 (en) * | 2004-12-01 | 2007-05-15 | Kyocera Wireless Corp. | Stack package for high density integrated circuits |
US7445962B2 (en) * | 2005-02-10 | 2008-11-04 | Stats Chippac Ltd. | Stacked integrated circuits package system with dense routability and high thermal conductivity |
JP4827556B2 (ja) * | 2005-03-18 | 2011-11-30 | キヤノン株式会社 | 積層型半導体パッケージ |
US7317256B2 (en) | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
JP4817892B2 (ja) * | 2005-06-28 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2006013555A (ja) | 2005-09-22 | 2006-01-12 | Oki Electric Ind Co Ltd | 半導体装置 |
TW200740735A (en) | 2006-01-31 | 2007-11-01 | Asahi Kasei Chemicals Corp | Industrial process for production of high-purity diol |
CN101375299B (zh) * | 2006-02-02 | 2012-08-08 | 松下电器产业株式会社 | 存储卡及存储卡的制造方法 |
US7435619B2 (en) | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US7692295B2 (en) | 2006-03-31 | 2010-04-06 | Intel Corporation | Single package wireless communication device |
JP5005321B2 (ja) | 2006-11-08 | 2012-08-22 | パナソニック株式会社 | 半導体装置 |
US8384199B2 (en) * | 2007-06-25 | 2013-02-26 | Epic Technologies, Inc. | Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system |
JP2007266640A (ja) | 2007-07-11 | 2007-10-11 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
RU72339U8 (ru) * | 2007-12-27 | 2008-06-10 | Общество с ограниченной ответственностью "НТЦ "Фактор" | Модуль многопроцессорной вычислительной системы (варианты) |
US7901987B2 (en) * | 2008-03-19 | 2011-03-08 | Stats Chippac Ltd. | Package-on-package system with internal stacking module interposer |
US7971347B2 (en) * | 2008-06-27 | 2011-07-05 | Intel Corporation | Method of interconnecting workpieces |
US10251273B2 (en) * | 2008-09-08 | 2019-04-02 | Intel Corporation | Mainboard assembly including a package overlying a die directly attached to the mainboard |
-
2008
- 2008-09-08 US US12/231,965 patent/US10251273B2/en active Active
-
2009
- 2009-08-27 JP JP2011526113A patent/JP5448003B2/ja active Active
- 2009-08-27 BR BRPI0913484-0A patent/BRPI0913484B1/pt not_active IP Right Cessation
- 2009-08-27 WO PCT/US2009/055133 patent/WO2010027890A2/en active Application Filing
- 2009-08-27 DE DE112009002155.7T patent/DE112009002155B4/de active Active
- 2009-08-27 GB GB1104809.7A patent/GB2475658B/en active Active
- 2009-08-27 CN CN2009801350137A patent/CN102150262B/zh active Active
- 2009-08-27 KR KR1020117005490A patent/KR20110039396A/ko active Application Filing
- 2009-08-27 RU RU2011113546/28A patent/RU2480862C2/ru not_active IP Right Cessation
- 2009-08-27 KR KR1020137011381A patent/KR20130051517A/ko active Search and Examination
- 2009-08-31 TW TW098129247A patent/TWI444120B/zh active
-
2013
- 2013-09-20 JP JP2013195262A patent/JP6232681B2/ja active Active
-
2019
- 2019-02-20 US US16/281,045 patent/US10555417B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10555417B2 (en) | 2020-02-04 |
KR20130051517A (ko) | 2013-05-20 |
US20190182958A1 (en) | 2019-06-13 |
DE112009002155B4 (de) | 2023-10-19 |
GB201104809D0 (en) | 2011-05-04 |
GB2475658A (en) | 2011-05-25 |
TWI444120B (zh) | 2014-07-01 |
CN102150262A (zh) | 2011-08-10 |
CN102150262B (zh) | 2013-02-27 |
WO2010027890A3 (en) | 2010-05-20 |
BRPI0913484B1 (pt) | 2019-06-04 |
GB2475658B (en) | 2012-11-28 |
KR20110039396A (ko) | 2011-04-15 |
US20100061056A1 (en) | 2010-03-11 |
JP2012502476A (ja) | 2012-01-26 |
JP6232681B2 (ja) | 2017-11-22 |
JP2014030042A (ja) | 2014-02-13 |
WO2010027890A2 (en) | 2010-03-11 |
JP5448003B2 (ja) | 2014-03-19 |
RU2480862C2 (ru) | 2013-04-27 |
DE112009002155T5 (de) | 2012-01-12 |
TW201026184A (en) | 2010-07-01 |
BRPI0913484A2 (pt) | 2016-08-30 |
US10251273B2 (en) | 2019-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
RU2011113546A (ru) | Системная плата, включающая модуль над кристаллом, непосредственно закрепленным на системной плате | |
ATE473489T1 (de) | Duales chipkartensystem | |
TW200611389A (en) | Integrated circuit package device and method for manufacturing the same | |
TW200802760A (en) | Flip chip MLP with folded heat sink | |
WO2017045358A1 (zh) | 柔性基板和显示装置 | |
US8338941B2 (en) | Semiconductor packages and methods of fabricating the same | |
US20060145323A1 (en) | Multi-chip package mounted memory card | |
TW200603352A (en) | Semiconductor device | |
WO2011115440A3 (en) | Large capacity memory module mounting device for portable terminal | |
KR20130101192A (ko) | 다수의 단차가 있는 인쇄회로 기판 (pcb)을 갖는 반도체 패키지 및 반도체 패키지 제조 방법 | |
WO2011103731A1 (zh) | 一种无线通讯模块和一种封装方法 | |
CN203025654U (zh) | 光学鼠标传感器封装和无线鼠标 | |
CN201514607U (zh) | 延伸式散热模块以及具有该模块的计算机装置 | |
KR20100045076A (ko) | 반도체 패키지 | |
US10130010B2 (en) | Internal heat-dissipation terminal | |
CN204857708U (zh) | 一种mosfet芯片封装结构 | |
CN217789992U (zh) | 转接板及具有其的电路板 | |
TWI236127B (en) | Input/output structure and integrated circuit using the same | |
CN204792769U (zh) | 一种mosfet芯片封装结构 | |
CN108228392B (zh) | 控制设备 | |
CN204792770U (zh) | 一种mosfet芯片封装结构 | |
CN204792802U (zh) | 一种mosfet芯片封装结构 | |
CN201956344U (zh) | 一种驱动裸片与贴片的兼容封装结构 | |
CN100375095C (zh) | 中央处理器与北桥芯片共构模块 | |
CN204741017U (zh) | 一种超薄mosfet芯片封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | The patent is invalid due to non-payment of fees |
Effective date: 20190828 |