JP5393057B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP5393057B2 JP5393057B2 JP2008145776A JP2008145776A JP5393057B2 JP 5393057 B2 JP5393057 B2 JP 5393057B2 JP 2008145776 A JP2008145776 A JP 2008145776A JP 2008145776 A JP2008145776 A JP 2008145776A JP 5393057 B2 JP5393057 B2 JP 5393057B2
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- insulating film
- semiconductor layer
- layer
- semiconductor device
- substrate
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- G02F1/1362—Active matrix addressed cells
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Description
図1は、本発明に係る半導体装置の主要な構成を説明するための上面図及び断面図である。図1は、特に薄膜トランジスタの構成を示しており、図1(A)は上面図、図1(B)は図1(A)における破線O−P間の断面図、図1(C)は図1(A)における破線Q−R間の断面図を示している。なお、図1(A)は、一部薄膜等を省略している。
本実施の形態では、半導体層に変質処理を行い、絶縁膜を形成する際に、プラズマ処理により半導体層表面に絶縁膜を形成し、半導体装置を作製する例について、図4〜図6を用いて説明する。なお、上記実施の形態1と重複する構成は、簡略化及び一部省略して説明する。
本実施の形態では、上記の実施の形態1及び2と異なる作製方法で半導体装置を作製する例について、図7及び図8を用いて説明する。以下、実施の形態1及び実施の形態2と同様の構成については同一の符号を付し、説明を省略する。
本発明に係る半導体装置は、CPU(中央演算回路:Central Processing Unit)等の集積回路に適用することができる。本実施の形態では、上記実施の形態1乃至3に示した半導体装置を適用したCPUの例に関して、図面を用いて以下に説明する。
本実施の形態では、上記実施の形態で示した半導体装置の使用形態の一例について説明する。具体的には、非接触でデータの入出力が可能である半導体装置の適用例に関して、図面を用いて以下に説明する。非接触でデータの入出力が可能である半導体装置は利用の形態によって、RFIDタグ、IDタグ、ICタグ、ICチップ、RFタグ、無線タグ、電子タグ、又は無線チップとも呼ばれる。
82 電源回路
83 リセット回路
84 クロック発生回路
85 データ復調回路
86 データ変調回路
87 制御回路
88 記憶回路
89 アンテナ
91 コード抽出回路
92 コード判定回路
93 CRC判定回路
94 出力ユニット回路
101 基板
102a 絶縁膜
102b 絶縁膜
103 半導体層
104 絶縁膜
105 絶縁膜
106 導電層
107 絶縁膜
108 絶縁膜
109a コンタクトホール
109b コンタクトホール
110a 導電層
110b 導電層
111 チャネル形成領域
112a 不純物領域
112b 不純物領域
113 薄膜トランジスタ
114 絶縁膜
115 絶縁膜
116 絶縁膜
117 絶縁膜
118 絶縁膜
119 絶縁膜
120 曲率中心位置
201 第1のプラズマ処理室
202 第2のプラズマ処理室
203 ロードロック室
204 共通室
205 ロボットアーム
206 カセット
210 排気口
211 基板保持台
212 矢印
213 マイクロ波
214 アンテナ
215 導波管
216 誘電体板
217 領域
218 シャワープレート
227 絶縁膜
2130 絶縁膜
2131 薄膜集積回路
2132 導電層
2133 基板
2134 導電性粒子
2135 樹脂
2136 導電層
2180 半導体装置
3200 通信手段
3210 表示部
3220 品物
3230 半導体装置
3240 リーダ/ライタ
3250 半導体装置
3260 商品
3600 基板
3601 演算回路
3602 演算回路用制御部
3603 命令解析部
3604 割り込み制御部
3605 タイミング制御部
3606 レジスタ
3607 レジスタ制御部
3608 バスインターフェース
3609 ROM
3620 ROMインターフェース
3621 クロック信号CLK1
3622 クロック信号CLK2
3660 CPU
3700 基板
3701 画素部
3702 走査線駆動回路
3703 信号線駆動回路
3704 CPU
3705 コントロール回路
Claims (5)
- 絶縁表面を有する基板上に、島状の半導体層を形成し、
第1の変質処理を行い、前記島状の半導体層の表面に第1の絶縁膜を形成し、
前記第1の絶縁膜を除去するとともに、前記島状の半導体層の下端部を露出し、
前記第1の絶縁膜が除去され、下端部が露出した前記島状の半導体層に第2の変質処理を行い、該島状の半導体層の表面に第2の絶縁膜を形成し、
前記第2の絶縁膜上に導電層を形成し、
前記第1の変質処理と前記第2の変質処理により、前記島状の半導体層の上端部及び下端部に丸みをもたせることを特徴とする半導体装置の作製方法。 - 請求項1において、
前記第1の変質処理は、プラズマ処理により行うことを特徴とする半導体装置の作製方法。 - 請求項1又は請求項2において、
前記第2の変質処理は、プラズマ処理により行うことを特徴とする半導体装置の作製方法。 - 絶縁表面を有する基板上に、島状の半導体層を形成し、
第1の変質処理を行い、前記島状の半導体層の表面に第1の絶縁膜を形成し、
前記第1の絶縁膜を除去し、
前記第1の絶縁膜が除去された前記島状の半導体層に第2の変質処理を行い、該島状の半導体層の表面に第2の絶縁膜を形成し、
前記第2の絶縁膜を除去し、
前記第2の絶縁膜が除去された前記島状の半導体層に第3の変質処理を行い、該島状の半導体層の表面に第3の絶縁膜を形成し、
前記第3の絶縁膜上に導電層を形成し、
前記第1の変質処理、前記第2の変質処理及び前記第3の変質処理により、前記島状の半導体層の上端部に丸みをもたせることを特徴とする半導体装置の作製方法。 - 請求項4において、
前記第3の変質処理は、プラズマ処理により行うことを特徴とする半導体装置の作製方法。
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2008
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US20080308911A1 (en) | 2008-12-18 |
JP2009021565A (ja) | 2009-01-29 |
JP5703358B2 (ja) | 2015-04-15 |
US8921902B2 (en) | 2014-12-30 |
JP2014042051A (ja) | 2014-03-06 |
US20130214393A1 (en) | 2013-08-22 |
US8420456B2 (en) | 2013-04-16 |
CN101325162B (zh) | 2013-05-08 |
CN101325162A (zh) | 2008-12-17 |
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