JP5389770B2 - 電子素子内蔵印刷回路基板及びその製造方法 - Google Patents
電子素子内蔵印刷回路基板及びその製造方法 Download PDFInfo
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- JP5389770B2 JP5389770B2 JP2010255631A JP2010255631A JP5389770B2 JP 5389770 B2 JP5389770 B2 JP 5389770B2 JP 2010255631 A JP2010255631 A JP 2010255631A JP 2010255631 A JP2010255631 A JP 2010255631A JP 5389770 B2 JP5389770 B2 JP 5389770B2
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- insulating resin
- electronic element
- circuit board
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- Expired - Fee Related
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/019—Manufacture or treatment using temporary auxiliary substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
120 電子素子
121 メッキ電極パッド
130 回路層
140 コア層
150 接触部材S
Claims (13)
- 一定の厚さを有するメッキ電極パッドを備えた電子素子;
前記メッキ電極パッドの下端面を露出し、その中心に前記電子素子を成すベース本体の中心が位置するように、前記電子素子を内蔵する絶縁樹脂層;及び
前記メッキ電極パッド上に配置された回路パターンを備えて、層間接続を成して前記絶縁樹脂層の両面に夫々配置された回路層;
を含み、
前記メッキ電極パッドの厚さは前記電子素子を覆う前記絶縁樹脂層の厚さと同一であり、前記電子素子と前記回路層とが前記メッキ電極パッドによって直接的に電気的接続をなす、電子素子内蔵印刷回路基板。 - 前記一定の厚さは5から250μmの範囲を有する請求項1に記載の電子素子内蔵印刷回路基板。
- 前記絶縁樹脂層は単一層で構成される請求項1に記載の電子素子内蔵印刷回路基板。
- 前記電子素子と対応されたキャビティを備えたコア層をさらに含んで、
前記絶縁樹脂層は前記コア層のキャビティに充填されて前記コア層上に配置される請求項1に記載の電子素子内蔵印刷回路基板。 - 前記絶縁樹脂層は熱硬化性樹脂で形成される請求項1に記載の電子素子内蔵印刷回路基板。
- 前記電子素子は、本体、本体上に形成された回路層、及び絶縁層を備えた能動素子であり、
前記絶縁樹脂層の中心は前記電子素子の本体の中心と一致する請求項1に記載の電子素子内蔵印刷回路基板。 - 接着部材を提供する段階;
前記接着部材上に一定の厚さを有するメッキ電極パッドを備えた電子素子を付着させる段階;
前記電子素子を含んだ前記接着部材上に絶縁シートを加熱圧着して、前記電子素子を成すベース本体の中心とその中心が一致するように絶縁樹脂層を形成する段階;
前記電子素子を内蔵した絶縁樹脂層から前記接着部材を取り除く段階;及び
前記メッキ電極パッド上に配置された回路パターンを備えて、層間接続を成して前記絶縁樹脂層の両面に夫々配置された回路層を形成する段階;
を含み、
前記メッキ電極パッドの厚さは前記電子素子を覆う前記絶縁樹脂層の厚さと同一であり、前記電子素子と前記回路層とが前記メッキ電極パッドによって直接的に電気的接続をなす、電子素子内蔵印刷回路基板の製造方法。 - 前記絶縁シートは熱硬化性樹脂で形成される請求項7に記載の電子素子内蔵印刷回路基板の製造方法。
- 前記一定の厚さは5から250μmの範囲を有する請求項7に記載の電子素子内蔵印刷回路基板の製造方法。
- 接着部材を提供する段階;
前記接着部材上に電子素子を付着する段階;
前記電子素子と対応されたキャビティを有するコア層を前記接着部材上に付着する段階;
前記電子素子を含んだ前記コア層上に絶縁シートを加熱圧着して、前記電子素子を成すベース本体の中心とその中心が一致するように絶縁樹脂層を形成する段階;
前記絶縁樹脂層を含んだコア層から前記接着部材を取り除く段階;及び
メッキ電極パッド上に配置された回路パターンを備えて、層間接続を成して前記絶縁樹脂層の両面に夫々配置された回路層を形成する段階;
を含み、
前記メッキ電極パッドの厚さは前記電子素子を覆う前記絶縁樹脂層の厚さと同一であり、前記電子素子と前記回路層とが前記メッキ電極パッドによって直接的に電気的接続をなす、電子素子内蔵印刷回路基板の製造方法。 - 前記絶縁シートは熱硬化性樹脂で形成される請求項10に記載の電子素子内蔵印刷回路基板の製造方法。
- 前記メッキ電極パッドの厚さは5から250μmの範囲を有する請求項10に記載の電子素子内蔵印刷回路基板の製造方法。
- 前記コア層はアンクラッド部材である請求項10に記載の電子素子内蔵印刷回路基板の製造方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020100050511A KR101085733B1 (ko) | 2010-05-28 | 2010-05-28 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
| KR10-2010-0050511 | 2010-05-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2011249759A JP2011249759A (ja) | 2011-12-08 |
| JP5389770B2 true JP5389770B2 (ja) | 2014-01-15 |
Family
ID=45021144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010255631A Expired - Fee Related JP5389770B2 (ja) | 2010-05-28 | 2010-11-16 | 電子素子内蔵印刷回路基板及びその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8780572B2 (ja) |
| JP (1) | JP5389770B2 (ja) |
| KR (1) | KR101085733B1 (ja) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101003585B1 (ko) * | 2008-06-25 | 2010-12-22 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
| KR20120026855A (ko) | 2010-09-10 | 2012-03-20 | 삼성전기주식회사 | 임베디드 볼 그리드 어레이 기판 및 그 제조 방법 |
| DE102011105346A1 (de) * | 2011-06-21 | 2012-12-27 | Schweizer Electronic Ag | Elektronische Baugruppe und Verfahren zu deren Herstellung |
| US20130044448A1 (en) * | 2011-08-18 | 2013-02-21 | Biotronik Se & Co. Kg | Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement |
| JP6166878B2 (ja) | 2012-08-30 | 2017-07-19 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
| JP5998792B2 (ja) * | 2012-09-21 | 2016-09-28 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
| KR101472672B1 (ko) * | 2013-04-26 | 2014-12-12 | 삼성전기주식회사 | 전자부품 내장 인쇄회로기판 및 그 제조방법 |
| US10219384B2 (en) | 2013-11-27 | 2019-02-26 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Circuit board structure |
| AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
| AT515447B1 (de) * | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
| US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
| KR102186148B1 (ko) * | 2014-02-28 | 2020-12-03 | 삼성전기주식회사 | 임베디드 기판 및 임베디드 기판의 제조 방법 |
| KR102231101B1 (ko) * | 2014-11-18 | 2021-03-23 | 삼성전기주식회사 | 소자 내장형 인쇄회로기판 및 그 제조방법 |
| US9837484B2 (en) | 2015-05-27 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming substrate including embedded component with symmetrical structure |
| US12014868B2 (en) * | 2020-08-14 | 2024-06-18 | Cyntec Co., Ltd. | Electrode structure |
| DE102021115848A1 (de) | 2021-06-18 | 2022-12-22 | Rolls-Royce Deutschland Ltd & Co Kg | Leiterplatte |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232776B (zh) * | 1999-09-02 | 2011-04-20 | 揖斐电株式会社 | 印刷布线板 |
| JP4270769B2 (ja) | 2000-12-15 | 2009-06-03 | イビデン株式会社 | 多層プリント配線板の製造方法 |
| JP2002299787A (ja) * | 2001-03-30 | 2002-10-11 | Matsushita Commun Ind Co Ltd | 高周波回路構造およびその製造方法 |
| JP2004055967A (ja) * | 2002-07-23 | 2004-02-19 | Matsushita Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
| US7141884B2 (en) * | 2003-07-03 | 2006-11-28 | Matsushita Electric Industrial Co., Ltd. | Module with a built-in semiconductor and method for producing the same |
| JP4575071B2 (ja) | 2004-08-02 | 2010-11-04 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
| JP4407527B2 (ja) | 2005-02-14 | 2010-02-03 | パナソニック株式会社 | 部品内蔵モジュールの製造方法 |
| WO2007034629A1 (ja) | 2005-09-20 | 2007-03-29 | Murata Manufacturing Co., Ltd. | 部品内蔵モジュールの製造方法および部品内蔵モジュール |
| US8101868B2 (en) | 2005-10-14 | 2012-01-24 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
| FI20060256A7 (fi) | 2006-03-17 | 2006-03-20 | Imbera Electronics Oy | Piirilevyn valmistaminen ja komponentin sisältävä piirilevy |
| KR100836651B1 (ko) * | 2007-01-16 | 2008-06-10 | 삼성전기주식회사 | 소자내장기판 및 그 제조방법 |
| US20100103634A1 (en) * | 2007-03-30 | 2010-04-29 | Takuo Funaya | Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment |
| KR100811034B1 (ko) * | 2007-04-30 | 2008-03-06 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판의 제조방법 |
| KR100821154B1 (ko) | 2007-07-11 | 2008-04-14 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
| KR100982795B1 (ko) * | 2008-07-10 | 2010-09-16 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 제조방법 |
| KR20110045098A (ko) * | 2008-09-30 | 2011-05-03 | 이비덴 가부시키가이샤 | 전자 부품 내장 배선판 및 그의 제조 방법 |
| JP5161732B2 (ja) | 2008-11-11 | 2013-03-13 | 新光電気工業株式会社 | 半導体装置の製造方法 |
| KR101104210B1 (ko) * | 2010-03-05 | 2012-01-10 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 및 그 제조방법 |
-
2010
- 2010-05-28 KR KR1020100050511A patent/KR101085733B1/ko not_active Expired - Fee Related
- 2010-10-05 US US12/923,720 patent/US8780572B2/en not_active Expired - Fee Related
- 2010-11-16 JP JP2010255631A patent/JP5389770B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US8780572B2 (en) | 2014-07-15 |
| JP2011249759A (ja) | 2011-12-08 |
| KR101085733B1 (ko) | 2011-11-21 |
| US20110290546A1 (en) | 2011-12-01 |
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