JP5225102B2 - 異なる高さのコンタクト線を有する高密度mosfet回路を製造するための構造および方法 - Google Patents
異なる高さのコンタクト線を有する高密度mosfet回路を製造するための構造および方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 154
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 70
- 229920005591 polysilicon Polymers 0.000 claims description 70
- 238000000151 deposition Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910052732 germanium Inorganic materials 0.000 claims description 19
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 description 34
- 229920002120 photoresistant polymer Polymers 0.000 description 24
- 238000010586 diagram Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 229910021332 silicide Inorganic materials 0.000 description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 11
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 11
- 238000005498 polishing Methods 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
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- 230000000903 blocking effect Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
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- 229910044991 metal oxide Inorganic materials 0.000 description 3
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- 230000003068 static effect Effects 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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Description
Claims (8)
- ソースおよびドレインと、
前記ソースまたはドレインの外側にあって前記ソースまたはドレインと金属バイアを介して接続するコンタクト線と、
前記ソースおよびドレインの間に位置するゲートと、
前記ゲートの側壁上のゲート・スペーサと、
前記コンタクト線の前記ゲートの側とは反対側の側壁上の単一のコンタクト線スペーサと、を含み、
前記コンタクト線が、前記ゲートの高さよりも低い高さを有し、前記コンタクト線スペーサが、前記ゲート・スペーサの高さよりも低い高さを有し、
前記ゲートが、第1のゲート層と、前記第1のゲート層の上、少なくとも1つの後続のゲート層の下に位置するポリシリコン・ゲルマニウム・ゲート層とを含む、MOSFET回路。 - 前記コンタクト線スペーサが、前記ゲート・スペーサの厚さよりも薄い厚さを有する、請求項1に記載のMOSFET回路。
- ソースおよびドレインと、
前記ソースまたはドレインの外側にあって前記ソースまたはドレインと金属バイアを介して接続するコンタクト線と、
前記ソースおよびドレインの間に位置する第1のゲートと、
前記第1のゲート層の上に位置する少なくとも1つの後続のゲート層と、
前記第1のゲート層および前記少なくとも1つの後続のゲート層の側壁上のゲート・スペーサと
前記コンタクト線の前記第1のゲートの側とは反対側の側壁上の単一のコンタクト線スペーサと、含み、
前記コンタクト線が、前記第1のゲート層と前記少なくとも1つの後続のゲート層とを合わせた高さよりも低い高さを有し、
前記コンタクト線スペーサが、前記ゲート・スペーサの高さよりも低い高さを有し、
前記第1のゲート層の上、前記少なくとも1つの後続のゲート層の下に位置するポリシリコン・ゲルマニウム・ゲート層をさらに含む、MOSFET回路。 - 前記コンタクト線スペーサが、前記ゲート・スペーサの厚さよりも薄い厚さを有する、請求項3に記載のMOSFET回路。
- MOSFET回路を製造する方法であって、
順番に積層された第1のポリシリコン層、ポリシリコン・ゲルマニウム層、および第2のポリシリコン層をパターン形成して、少なくとも1つのコンタクト線および少なくとも1つのゲートを形成すること、
前記ゲートを保護し、前記コンタクト線を露出させること、
前記コンタクト線の高さを低減させて、その結果としての前記コンタクト線の高さが前記ゲートの高さよりも低くなるようにすること、
前記ゲートの側壁に第1のスペーサを形成すること、および
前記コンタクト線の前記ゲートの側とは反対側の側壁に前記第1のスペーサの高さよりも低い高さの第2のスペーサを形成することを含み、
前記コンタクト線は、前記ゲートの両側に形成されるソースおよびドレインの外側にあって前記ソースまたはドレインと金属バイアを介して接続する、方法。 - 前記第2のスペーサが、前記第1のスペーサの厚さよりも薄い、請求項5に記載の方法。
- 前記第2のスペーサを形成することが、
前記コンタクト線の両側に2つのスペーサを形成すること、および
前記2つのスペーサのうちの前記ゲートの側とは反対側の前記第2のスペーサを保護し、前記第1のスペーサを保護した上で、前記2つのスペーサのうちの前記ゲートの側の保護されていないスペーサをエッチングすることを含む、請求項5または6に記載の方法。 - MOSFET回路を製造する方法であって、
基板の上に第1のポリシリコン層を付着させること、
前記第1のポリシリコン層の上にポリシリコン・ゲルマニウム層を付着させること、
前記ポリシリコン・ゲルマニウム層の上に第2のポリシリコン層を付着させること、
前記第1のポリシリコン層、前記ポリシリコン・ゲルマニウム層および前記第2のポリシリコン層をパターン形成して、コンタクト線スタックおよびゲート・スタックを形成すること、
前記コンタクト線スタックの前記第2のポリシリコン層を除去することにより、前記コンタクト線スタックが、前記ゲート・スタックの高さよりも低い高さとすること、
前記ゲート・スタックの側壁に第1のスペーサを形成すること、および
前記コンタクト線スタックの前記ゲートの側とは反対側の側壁に前記第1のスペーサの高さよりも低い高さの第2のスペーサを形成することを含み、
前記コンタクト線スタックは、前記ゲート・スタックの両側に形成されるソースおよびドレインの外側にあって前記ソースまたはドレインと金属バイアを介して接続する、方法。
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US11/306,707 | 2006-01-09 | ||
US11/306,707 US7339230B2 (en) | 2006-01-09 | 2006-01-09 | Structure and method for making high density mosfet circuits with different height contact lines |
PCT/US2007/060265 WO2007082199A2 (en) | 2006-01-09 | 2007-01-09 | Structure and method for making high density mosfet circuits with different height contact lines |
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JP2009522819A JP2009522819A (ja) | 2009-06-11 |
JP5225102B2 true JP5225102B2 (ja) | 2013-07-03 |
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EP (1) | EP1979941B1 (ja) |
JP (1) | JP5225102B2 (ja) |
CN (1) | CN101361186B (ja) |
AT (1) | ATE535941T1 (ja) |
TW (1) | TWI409948B (ja) |
WO (1) | WO2007082199A2 (ja) |
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KR20100101446A (ko) | 2009-03-09 | 2010-09-17 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US8729627B2 (en) * | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
US8507375B1 (en) * | 2012-02-02 | 2013-08-13 | GlobalFoundries, Inc. | Alignment tolerant semiconductor contact and method |
US9786557B1 (en) * | 2016-04-12 | 2017-10-10 | International Business Machines Corporation | Two-dimensional self-aligned super via integration on self-aligned gate contact |
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CN101361186A (zh) | 2009-02-04 |
EP1979941A2 (en) | 2008-10-15 |
US20070170472A1 (en) | 2007-07-26 |
EP1979941B1 (en) | 2011-11-30 |
US20080029836A1 (en) | 2008-02-07 |
WO2007082199A3 (en) | 2007-11-29 |
ATE535941T1 (de) | 2011-12-15 |
TW200742074A (en) | 2007-11-01 |
WO2007082199A2 (en) | 2007-07-19 |
US7750415B2 (en) | 2010-07-06 |
EP1979941A4 (en) | 2011-03-23 |
CN101361186B (zh) | 2012-07-18 |
US7339230B2 (en) | 2008-03-04 |
JP2009522819A (ja) | 2009-06-11 |
TWI409948B (zh) | 2013-09-21 |
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