US20210028114A1 - Semiconductor device and fabrication method for the same - Google Patents
Semiconductor device and fabrication method for the same Download PDFInfo
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- US20210028114A1 US20210028114A1 US17/068,804 US202017068804A US2021028114A1 US 20210028114 A1 US20210028114 A1 US 20210028114A1 US 202017068804 A US202017068804 A US 202017068804A US 2021028114 A1 US2021028114 A1 US 2021028114A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title description 26
- 238000004519 manufacturing process Methods 0.000 title description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 34
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 84
- 229910021332 silicide Inorganic materials 0.000 description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
- 230000004075 alteration Effects 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
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- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
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- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- 229910000077 silane Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device having a local interconnect structure and a fabrication method for the same.
- the local interconnect structure refers to routing, including a shared contact plug, that connects an element and an interconnect mutually without use of global wiring formed in a wiring layer.
- MIS metal-insulator-semiconductor
- SRAM static random access memory
- FIG. 10 shows a cross-sectional configuration of a conventional semiconductor device having a shared contact.
- an active region 107 surrounded with an isolation region 106 is formed in a semiconductor substrate 101 .
- a MIS transistor 110 is formed in the active region 107 .
- a gate electrode 103 A of the MIS transistor 110 is formed on the active region 107 with a gate insulating film 102 A interposed therebetween.
- Source/drain regions 104 a and 104 b are formed in portions of the active region 107 located on both sides of the gate electrode 103 A.
- Sidewalls 105 A are formed on both side faces of the gate electrode 103 A.
- a gate interconnect 103 B is formed on a portion of the active region 107 located on the side of the source/drain region 104 a opposite to the side thereof closer to the gate electrode 103 A, with an insulating film 102 B interposed therebetween. Sidewalls 105 B are formed on both side faces of the gate interconnect 103 B.
- An underlying insulating film 120 and an interlayer insulating film 121 are formed on the semiconductor substrate 101 to cover the gate electrode 103 A and the gate interconnect 103 B.
- a shared contact plug 108 connected to both the source/drain region 104 a and the gate interconnect 103 B and a contact plug 109 connected to the source/drain region 104 b are formed through the underlying insulating film 120 and the interlayer insulating film 121 .
- the conventional semiconductor device has the following problem.
- To form a shared contact plug it is necessary to form an opening (contact hole) that exposes the top surfaces of the source/drain region and the gate interconnect through the interlayer insulating film.
- the contact hole for the shared contact plug is therefore considerably larger than a contact hole for forming a normal contact plug.
- Such contact holes having considerably different sizes are formed by dry etching, there arises a difference in etched dimension (etching critical dimension) according to the difference in opening area, and this makes it difficult to control the dimensions of the shared contact plug and the normal contact plug (see Y.
- An object of the present invention is providing a semiconductor device having a local interconnect structure involving no increase in the size of source/drain regions.
- a semiconductor device is configured to have a local interconnect structure that has a SiGe layer formed on a source/drain region to protrude above the top surface of a semiconductor substrate.
- the semiconductor device of the present invention includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate located on the sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate; and a first contact plug connected to the first silicon-germanium layer, wherein the gate interconnect and the first source/drain region are connected via a local interconnect structure including the first silicon-germanium layer.
- the aspect ratio of the contact hole can be reduced compared with the case of forming a contact plug directly connected to both the source/drain region and the gate interconnect. This improves the precision of formation of the contact hole, and thus makes it unnecessary to increase the size of the source/drain region. As a result, a downsized semiconductor device having a low-resistance local interconnect structure can be implemented.
- the first fabrication method for a semiconductor device of the present invention includes the steps of: (a) forming a gate electrode and a gate interconnect spaced from each other on a semiconductor substrate; (b) forming a first source/drain region and a second source/drain region in portions of the semiconductor substrate located on a side of the gate electrode closer to the gate interconnect and on the opposite side of the gate electrode, respectively; (c) forming a first silicon-germanium layer to extend over the top surfaces of the first source drain region and the gate interconnect; (d) forming an interlayer insulating film on the semiconductor substrate after the step (c); and (e) forming a first contact plug through the interlayer insulating film to be connected to the first silicon-germanium layer.
- the first source/drain region and the conductive film are electrically connected with each other via the SiGe layer.
- This can reduce the wiring resistance between the first source/drain region and the conductive film.
- the contact plug can only be in contact with the SiGe layer, it is unnecessary to provide a shared contact plug.
- the aspect ratio of the contact hole can be reduced, and thus the contact hole can be formed with high precision. It is therefore unnecessary to increase the size of the first source/drain region. As a result, a downsized semiconductor device with low wiring resistance can be fabricated.
- the second fabrication method for a semiconductor device of the present invention includes the steps of: (a) forming a gate electrode and a gate interconnect spaced from each other on a semiconductor substrate; (b) forming a first source/drain region and a second source/drain region in portions of the semiconductor substrate located on a side of the gate electrode closer to the gate interconnect and on the opposite side of the gate electrode, respectively; (c) forming a first silicon-germanium layer on the first source drain region to protrude above the top surface of the semiconductor substrate; (d) forming an interlayer insulating film on the semiconductor substrate after the step (c); and (e) forming a shared contact plug through the interlayer insulating film to be connected to part of the first silicon-germanium layer and part of the gate interconnect.
- the aspect ratio of the contact hole for formation of the shared contact plug can be reduced.
- the contact hole can be formed with high precision, and this makes it unnecessary to increase the size of the first source/drain region.
- a downsized semiconductor device with low wiring resistance can be fabricated.
- FIG. 1 is a cross-sectional view of a semiconductor device of Embodiment 1 of the present invention.
- FIGS. 2A to 2C are cross-sectional views sequentially illustrating process steps of a fabrication method for the semiconductor device of Embodiment 1 of the present invention.
- FIGS. 3A to 3C are cross-sectional views sequentially illustrating process steps of the fabrication method for the semiconductor device of Embodiment 1 of the present invention.
- FIGS. 4A and 4B are cross-sectional views sequentially illustrating process steps of the fabrication method for the semiconductor device of Embodiment 1 of the present invention.
- FIG. 5 is a cross-sectional view illustrating a process step of the fabrication method for the semiconductor device of Embodiment 1 of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device of Embodiment 2 of the present invention.
- FIGS. 7A and 7B are cross-sectional views sequentially illustrating process steps of a fabrication method for the semiconductor device of Embodiment 2 of the present invention.
- FIGS. 8A and 8B are cross-sectional views sequentially illustrating process steps of the fabrication method for the semiconductor device of Embodiment 2 of the present invention.
- FIG. 9 is a cross-sectional view of a semiconductor device of an alteration to Embodiment 2 of the present invention.
- FIG. 10 is a cross-sectional view of a conventional semiconductor device.
- FIG. 1 shows a cross-sectional configuration of a semiconductor device of Embodiment 1 of the present invention.
- the semiconductor device of this embodiment has a local interconnect structure 60 composed of a SiGe layer 61 formed to extend over the top surfaces of a first source/drain region 29 A, a sidewall 43 A and a gate interconnect 42 .
- an n-type well 16 is formed in a semiconductor substrate 11 made of silicon (Si), and an active region 18 surrounded with an isolation region 17 is formed in the n-type well 16 .
- a p-type MIS transistor 12 is formed in the active region 18 .
- the MIS transistor 12 includes a gate electrode 22 formed on the active region 18 with a gate insulating film 21 interposed therebetween and sidewalls 23 formed on both side faces of the gate electrode 22 .
- Each of the sidewalls 23 has an offset sidewall 24 having a plate-shaped cross-section, an inner sidewall 25 having an L-shaped cross-section and an outer sidewall 26 covering the inner sidewall 25 .
- P-type extension regions 28 A and 28 B are formed in portions of the active region 18 located on both sides of the gate electrode 22 .
- First and second p-type source/drain regions 29 A and 29 B, having depressions in their top portions, are formed in portions of the active region 18 located outside of the respective sidewalls 23 .
- a gate interconnect 42 is formed on the active region 18 , with an insulating film 41 interposed therebetween, at a position opposite to the gate electrode 22 with respect to the first source/drain region 29 A.
- a sidewall 43 A is formed on one of the side faces of the gate interconnect 42 closer to the first source/drain region 29 A, and a sidewall 43 B is formed on the other side face of the gate interconnect 42 .
- the sidewall 43 A is lower in height than the sidewall 43 B, with part of the side face of the gate interconnect 42 closer to the first source/drain region 29 A being left uncovered with the sidewall 43 A.
- Each of the sidewalls 43 A and 43 B has an offset sidewall 44 having a plate-shaped cross-section, an inner sidewall 45 having an L-shaped cross-section and an outer sidewall 46 covering the inner sidewall 45 .
- the first source/drain region 29 A and the gate interconnect 42 are electrically connected to each other via the silicon-germanium (SiGe) layer 61 that constitutes the local interconnect structure 60 . This can reduce the wiring resistance between the first source/drain region 29 A and the gate interconnect 42 .
- a contact plug 62 is formed on the portion of the SiGe layer 61 that buries the depression on the first source/drain region 29 A via a silicide layer 67 .
- a contact plug 66 is formed on the portion of a SiGe layer 65 that buries the depression on the second source/drain region 29 B via the silicide layer 67 .
- the contact plugs 62 and 66 are formed through an underlying insulating film 71 and an interlayer insulating film 72 formed sequentially to cover the gate electrode 22 , the gate interconnect 42 and the SiGe layers 61 and 65 .
- the SiGe layer 61 is used as the local interconnect structure 60 for connecting the first source/drain region 29 A with the gate interconnect 42 .
- the contact plug 62 reaching the silicide layer 67 on the SiGe layer 61 is not required to be large, but can be of the same size as the contact plug 66 reaching the silicide layer 67 on the SiGe layer 65 .
- the contact plugs 62 and 66 can be easily controlled without the necessity of increasing the size of the first source/drain region 29 A. As a result, the semiconductor device can be downsized.
- the SiGe layers 61 and 65 are formed to bury the depressions in the top portions of the first and second source/drain regions 29 A and 29 B. With these SiGe layers, compressive stress in the gate length direction is applied to the channel region of the MIS transistor 12 . This improves the mobility of hole carriers, and thus can improve the driving force of the p-type MIS transistor.
- the top portions of the SiGe layers 61 and 65 and the gate electrode 22 are silicified to form the silicide layer 67 .
- the contact plugs 62 and 66 are therefore in contact with the SiGe layers 61 and 65 via the silicide layer 67 . This can further reduce the wiring resistance.
- an isolation region 17 is formed in the semiconductor substrate 11 made of Si, to define the active region 18 surrounded with the isolation region 17 .
- N-type impurity ions are implanted in the semiconductor substrate 11 to form the n-type well 16 .
- an insulating film made of SiO 2 and the like having a thickness of about 2 nm and a polysilicon film having a thickness of about 100 nm are sequentially formed on the semiconductor substrate 11 .
- the polysilicon film and the insulating film are then selectively etched, to form the gate insulating film 21 and the gate electrode 22 on the active region 18 , and also the insulating film 41 and the gate interconnect 42 at a position on the active region 18 spaced from the gate electrode 22 .
- the insulating film 41 and the gate interconnect 42 are not necessarily formed on the active region 18 but may be formed on the isolation region 17 .
- a resist mask or a hard mask may be used as an etching mask for the polysilicon film and the insulating film.
- an insulating film made of SiO 2 and the like is formed on the semiconductor substrate 11 and then etched back, to form the offset sidewalls 24 and 44 on the side faces of the gate electrode 22 and gate interconnect 42 , respectively.
- a p-type impurity is implanted in the active region 18 to form the p-type extension regions 28 A and 28 B as shallow source/drain regions.
- a silicon oxide film and a silicon nitride film are sequentially deposited on the semiconductor substrate 11 and then etched back. This results in formation of the inner sidewalls 25 made of the silicon oxide film and the outer sidewalls 26 made of the silicon nitride film on both side faces of the gate electrode 22 via the offset sidewalls 24 , as well as formation of the inner sidewalls 45 made of the silicon oxide film and the outer sidewalls 46 made of the silicon nitride film on both side faces of the gate interconnect 42 via the offset sidewalls 44 .
- the sidewalls 23 are formed on both side faces of the gate electrode 22
- the sidewall 43 A is formed on the side face of the gate interconnect 42 closer to the gate electrode 22
- the sidewall 43 B is formed on the other side face of the gate interconnect 42 .
- a p-type impurity is then implanted in the active region 18 using the gate electrode 22 and the sidewalls 23 as a mask, to form the p-type first and second source/drain regions 29 A and 29 B as deep source/drain regions in portions of the active region 18 located outside of the sidewalls 23 .
- a protection film 81 made of SiO 2 and the like having a thickness of about 50 nm is formed on the entire surface of the semiconductor substrate 11 .
- the protection film 81 is partly removed to expose the first and second source/drain regions 29 A and 29 B, the gate interconnect 42 and the sidewall 43 A, while being left unremoved on the gate electrode 22 not to expose the top surface of the gate electrode 22 .
- the semiconductor substrate 11 is etched, to form depressions 18 a and 18 b having a depth of about 40 nm on the portions of the active region 18 where the first and second source/drain regions 29 A and 29 B are formed.
- the gate interconnect 42 is etched at its top portion, to become lower in height than the gate electrode 22 and the sidewall 43 B.
- the sidewall 43 A is also etched to become lower in height than the sidewall 43 B.
- the sidewall 43 A is further etched selectively to expose the upper part of the side face of the gate interconnect 42 closer to the gate electrode 22 .
- the etching may be made by dry etching, wet etching using an organic alkaline etchant or a combined method thereof.
- a p-type SiGe layer is epitaxially grown on the top surface of the gate interconnect 42 , the side face of the gate interconnect 42 , the top surface of the first source/drain region 29 A and the top surface of the second source/drain region 29 B, on all of which Si is exposed.
- the SiGe layer 61 is formed to extend over the top surfaces of the first source/drain region 29 A and the gate interconnect 42
- the SiGe layer 65 is formed on the second source/drain region 29 B.
- the first source/drain region 29 A and the gate interconnect 42 are therefore electrically connected with each other.
- the SiGe layers 61 and 65 may be formed by low-pressure chemical vapor deposition (low-pressure CVD) using silane gas (SiH 4 ), germane gas (GeH 4 ) and a p-type dopant such as diborane (B 2 H 6 ).
- the protection film 81 is selectively removed.
- a metal film having a high melting point such as nickel (Ni) is deposited on the semiconductor substrate 11 to a thickness of several nanometers and then heat-treated, to silicify the top portions of the SiGe layers 61 and 65 , the gate interconnect 42 and the gate electrode 22 , to thereby form the silicide layer 67 .
- the unreacted remainder of the metal film is then removed.
- the underlying insulating film 71 made of silicon nitride is formed on the entire surface of the semiconductor substrate 11 , and then the interlayer insulating film 72 made of silicon oxide is formed on the underlying insulating film 71 . Thereafter, a contact hole 72 a and a contact hole 72 b are formed through the interlayer insulating film 72 and the underlying insulating film 71 to reach the portion of the silicide layer 67 on the SiGe layer 61 and the portion thereof on the SiGe layer 65 , respectively.
- the contact hole 72 a may be formed at any position as long as it reaches the silicide film 67 on the SiGe layer 61 .
- the contact hole 72 a may be formed at a position above the gate interconnect 42 , for example.
- the contact holes 72 a and 72 b are buried with a conductive material such as tungsten, to form the contact plug 62 connected to the SiGe layer 61 via the silicide layer 67 and the contact plug 66 connected to the SiGe layer 65 via the silicide layer 67 .
- the SiGe layer 61 is used as the local interconnect structure for connecting the first source/drain region 29 A with the gate interconnect 42 .
- the contact hole 72 a reaching the silicide layer 67 on the SiGe layer 61 is not required to be large, but can be of the same size as the contact hole 72 b reaching the silicide layer 67 on the SiGe layer 65 .
- the contact holes can be formed with high precision. This makes it possible to reduce the size of the first source/drain region 29 A, and thus the semiconductor device can be downsized.
- the contact hole 72 a can be of the same size as the contact hole 72 b . The contact holes can therefore be formed with high precision.
- the sidewall 43 A is made short to expose part of the side face of the gate interconnect 42 closer to the first source/drain region 29 A.
- the SiGe layer 61 therefore grows also on the side face of the gate interconnect 42 , and this ensures the connection between the SiGe layer grown on the first source/drain region 29 A and the SiGe layer grown on the gate interconnect 42 . Note that it is not necessarily required to expose the side face of the gate interconnect 42 closer to the first source/drain region 29 A if only the SiGe layer 61 can be formed to extend over the top surfaces of the first source/drain region 29 A and the gate interconnect 42 .
- the depressions 18 a and 18 b were formed on the first and second source/drain regions 29 A and 29 B, and the SiGe layers 61 and 65 were formed to bury the depressions 18 a and 18 b .
- compressive stress in the gate length direction is applied to the channel region of the MIS transistor, and this improves the driving force of the p-type MIS transistor. If such an effect of improving the driving force is unnecessary, the depressions 18 a and 18 b may not be formed. If no such depressions are formed, the SiGe layer 65 may not be formed on the second source/drain region 29 B.
- an n-type MIS transistor may be formed in a similar manner. In this case, it is unnecessary to form depressions on the source/drain regions.
- FIG. 6 shows a cross-sectional configuration of a semiconductor device of Embodiment 2.
- the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.
- the semiconductor device of this embodiment has a local interconnect structure 60 composed of a SiGe layer 61 formed on a first source/drain region 29 A and a shared contact plug 63 connected to part of the SiGe layer 61 and part of a gate interconnect 42 .
- the shared contact plug 63 is greater in size than a contact plug 66 .
- the SiGe layer 61 protruding from the top surface of the semiconductor substrate 11 , the aspect ratio of the contact hole for formation of the shared contact plug 63 can be reduced. The requirements of etching precision of the contact hole can therefore be widely eased. Hence, it is unnecessary to increase the size of the first source/drain region 29 A, and thus the semiconductor device can be downsized.
- a protection film 81 made of SiO 2 and the like is formed on the entire surface of the semiconductor substrate 11 , and then the portion thereof overlying the first source/drain region 29 A is removed.
- the protection film 81 is therefore left behind covering the gate electrode 22 , the gate interconnect 42 and the second source/drain region 29 B.
- the SiGe film 61 is epitaxially grown on the top surface of the first source/drain region 29 A on which Si is exposed, to obtain the SiGe film 61 protruding from the semiconductor substrate 11 .
- a metal film having a high melting point such as nickel (Ni) is deposited on the semiconductor substrate 11 to a thickness of several nanometers and then heat-treated, to silicify the top portions of the SiGe layer 61 , the gate electrode 22 , the gate interconnect 42 and the second source/drain region 29 B, to form a silicide layer 67 .
- an underlying insulating film 71 made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 11 , and then an interlayer insulating film 72 made of a silicon oxide film is formed on the underlying insulating film 71 .
- a contact hole 72 a and a contact hole 72 b are formed through the interlayer insulating film 72 and the underlying insulating film 71 , to reach the portions of the silicide layer 67 on the SiGe layer 61 and the gate interconnect 42 and to reach the portion of the silicide layer 67 on the second source/drain region 29 B, respectively.
- the sidewall 43 A exposed in the contact hole 72 a may be etched selectively to make the sidewall 43 A lower in height than the gate interconnect 42 to thereby expose part of the side face of the gate interconnect 42 closer to the gate electrode 22 .
- the contact holes 72 a and 72 b are buried with a conductive material such as tungsten, to form the shared contact plug 63 connected to the SiGe layer 61 and the gate interconnect 42 via the silicide layer 67 and the contact plug 66 connected to the second source/drain region 29 B via the silicide layer 67 .
- a conductive material such as tungsten
- no SiGe layer is formed on the second source/drain region 29 B.
- a SiGe layer may be formed on the second source/drain region 29 B.
- depressions may be formed in the top portions of the first and second source/drain regions 29 A and 29 B. In this case, however, the top surface of the SiGe layer 61 formed on the first source/drain region 29 A should protrude above the top surface of the semiconductor substrate 11 sufficiently to ensure that the aspect ratio of the contact hole 72 a is not large.
- FIG. 9 shows a cross-sectional configuration of a semiconductor device of an alteration to Embodiment 2 of the present invention.
- the semiconductor device of this alteration has a local interconnect structure 60 composed of a first SiGe layer 61 A formed on the first source/drain region 29 A, a second SiGe layer 61 B formed on the gate interconnect 42 and a shared contact plug 63 connected to part of the first SiGe layer 61 A and part of the second SiGe layer 61 B.
- the second SiGe layer 61 B on the gate interconnect 42 extends toward the sidewall 43 A, narrowing the space between the first and second SiGe layers 61 A and 61 B.
- the contact hole for the shared contact plug 63 can be made small compared with the configuration without the second SiGe layer 61 B.
- the SiGe layer may be formed also on the second source/drain region 29 B, and depressions may be formed in the top portions of the first and second source/drain regions 29 A and 29 B, as in Embodiment 1.
- the gate interconnect 42 and the sidewall 43 A are the same in height, the sidewall 43 A may be made lower in height than the gate interconnect 42 to expose part of the side face of the gate interconnect 42 closer to the gate electrode 22 .
- the semiconductor devices of the above embodiments and alteration respectively have a contact plug electrically connected to the second source/drain region.
- a contact plug connected to the second source/drain region is not necessarily required.
- a contact plug connected to the gate electrode may be provided.
- the SiGe layer was formed after formation of the source/drain regions.
- the source/drain regions may be formed by ion implantation after formation of the SiGe layer.
- SiO 2 was used as the material of the gate insulating film.
- a film having a high dielectric constant (high-K film) made of hafnium dioxide (HfO 2 ), a hafnium silicate (HfSiO x (x>1) or the like, in place of SiO 2 may be used.
- part of the gate interconnect was formed on the active region.
- the entire of the gate interconnect may be formed on the isolation region, or on the active region.
- the semiconductor devices of the above embodiments and alteration can be used for a MIS transistor constituting part of a SRAM cell, or may be applied to a MIS transistor constituting part of another circuit section such as a logic section. Otherwise the inventive semiconductor devices can be used for devices other than memory.
- a semiconductor device provided with a local interconnect structure involving no increase in the size of source/drain regions can be implemented, and thus the present invention is useful as a semiconductor device having a local interconnect structure and a fabrication method for such a semiconductor device.
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Abstract
The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
Description
- This application is a Continuation of U.S. application Ser. No. 15/013,946, filed on Feb. 2, 2016. U.S. application Ser. No. 15/013,946 is a Continuation of U.S. application Ser. No. 13/687,407, filed on Nov. 28, 2012, now U.S. Pat. No. 9,287,392, issued Mar. 15, 2016. U.S. application Ser. No. 13/687,407 is a Divisional of U.S. application Ser. No. 13/149,554, filed on May 31, 2011, now U.S. Pat. No. 8,344,455, issued Jan. 1, 2013. U.S. application Ser. No. 13/149,554 is a Divisional of U.S. application Ser. No. 12/247,518, filed on Oct. 8, 2008, now U.S. Pat. No. 7,977,800, issued Jul. 12, 2011. U.S. application Ser. No. 12/247,518 claims priority to Japanese Patent Application No. 2007-282678, filed on Oct. 31, 2007, the entire contents of each of which are hereby incorporated by reference.
- The present invention relates to a semiconductor device having a local interconnect structure and a fabrication method for the same.
- In recent years, with the trend toward finer semiconductor devices, gate electrodes tend to have larger contact resistance and wiring resistance. To address this problem, a local interconnect structure is used to connect a gate electrode with a source/drain region to thereby reduce wiring resistance (see Japanese Laid-Open Patent Publication No. 2007-150244, for example). The local interconnect structure as used herein refers to routing, including a shared contact plug, that connects an element and an interconnect mutually without use of global wiring formed in a wiring layer.
- In particular, in a metal-insulator-semiconductor (MIS) transistor constituting a static random access memory (SRAM) cell, such a local interconnect structure is very effective because with use of the local interconnect structure, not only the reduction in wiring resistance but also reduction in the size of the SRAM cell can be attained.
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FIG. 10 shows a cross-sectional configuration of a conventional semiconductor device having a shared contact. As shown inFIG. 10 , anactive region 107 surrounded with anisolation region 106 is formed in asemiconductor substrate 101. AMIS transistor 110 is formed in theactive region 107. Agate electrode 103A of theMIS transistor 110 is formed on theactive region 107 with agate insulating film 102A interposed therebetween. Source/drain regions active region 107 located on both sides of thegate electrode 103A.Sidewalls 105A are formed on both side faces of thegate electrode 103A. - A
gate interconnect 103B is formed on a portion of theactive region 107 located on the side of the source/drain region 104 a opposite to the side thereof closer to thegate electrode 103A, with aninsulating film 102B interposed therebetween.Sidewalls 105B are formed on both side faces of thegate interconnect 103B. - An underlying
insulating film 120 and aninterlayer insulating film 121 are formed on thesemiconductor substrate 101 to cover thegate electrode 103A and thegate interconnect 103B. A sharedcontact plug 108 connected to both the source/drain region 104 a and thegate interconnect 103B and acontact plug 109 connected to the source/drain region 104 b are formed through the underlyinginsulating film 120 and theinterlayer insulating film 121. - With the connection of the source/
drain region 104 a with thegate interconnect 103B via the sharedcontact plug 108, it is possible to not only reduce wiring resistance but also reduce the occupation area, compared with a configuration in which contacts are separately formed for the source/drain region 104 a and thegate interconnect 103B and are connected to each other in a wiring layer. Hence, semiconductor devices adopting a local interconnect structure such as the shared contact plug can be downsized without increasing wiring resistance. - However, the conventional semiconductor device has the following problem. To form a shared contact plug, it is necessary to form an opening (contact hole) that exposes the top surfaces of the source/drain region and the gate interconnect through the interlayer insulating film. The contact hole for the shared contact plug is therefore considerably larger than a contact hole for forming a normal contact plug. When such contact holes having considerably different sizes are formed by dry etching, there arises a difference in etched dimension (etching critical dimension) according to the difference in opening area, and this makes it difficult to control the dimensions of the shared contact plug and the normal contact plug (see Y. Kimura et al, Optimization of contact formation process for 45 nm technology node Ultra High Density SRAM”, Extended Abstracts of the 54th Meeting, Japan Society of Applied Physics, 2007, p. 931, for example). Hence, to secure the alignment margin between the shared contact plug and the source/drain region, the area of the source/drain region must be increased. This raises a problem of increasing the size of the resultant semiconductor device.
- An object of the present invention is providing a semiconductor device having a local interconnect structure involving no increase in the size of source/drain regions.
- To attain the above object, according to the present invention, a semiconductor device is configured to have a local interconnect structure that has a SiGe layer formed on a source/drain region to protrude above the top surface of a semiconductor substrate.
- Specifically, the semiconductor device of the present invention includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate located on the sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate; and a first contact plug connected to the first silicon-germanium layer, wherein the gate interconnect and the first source/drain region are connected via a local interconnect structure including the first silicon-germanium layer.
- In the semiconductor device of the present invention, the aspect ratio of the contact hole can be reduced compared with the case of forming a contact plug directly connected to both the source/drain region and the gate interconnect. This improves the precision of formation of the contact hole, and thus makes it unnecessary to increase the size of the source/drain region. As a result, a downsized semiconductor device having a low-resistance local interconnect structure can be implemented.
- The first fabrication method for a semiconductor device of the present invention includes the steps of: (a) forming a gate electrode and a gate interconnect spaced from each other on a semiconductor substrate; (b) forming a first source/drain region and a second source/drain region in portions of the semiconductor substrate located on a side of the gate electrode closer to the gate interconnect and on the opposite side of the gate electrode, respectively; (c) forming a first silicon-germanium layer to extend over the top surfaces of the first source drain region and the gate interconnect; (d) forming an interlayer insulating film on the semiconductor substrate after the step (c); and (e) forming a first contact plug through the interlayer insulating film to be connected to the first silicon-germanium layer.
- In the first fabrication method for a semiconductor device, the first source/drain region and the conductive film are electrically connected with each other via the SiGe layer. This can reduce the wiring resistance between the first source/drain region and the conductive film. Also, since the contact plug can only be in contact with the SiGe layer, it is unnecessary to provide a shared contact plug. Hence, the aspect ratio of the contact hole can be reduced, and thus the contact hole can be formed with high precision. It is therefore unnecessary to increase the size of the first source/drain region. As a result, a downsized semiconductor device with low wiring resistance can be fabricated.
- The second fabrication method for a semiconductor device of the present invention includes the steps of: (a) forming a gate electrode and a gate interconnect spaced from each other on a semiconductor substrate; (b) forming a first source/drain region and a second source/drain region in portions of the semiconductor substrate located on a side of the gate electrode closer to the gate interconnect and on the opposite side of the gate electrode, respectively; (c) forming a first silicon-germanium layer on the first source drain region to protrude above the top surface of the semiconductor substrate; (d) forming an interlayer insulating film on the semiconductor substrate after the step (c); and (e) forming a shared contact plug through the interlayer insulating film to be connected to part of the first silicon-germanium layer and part of the gate interconnect.
- In the second fabrication method for a semiconductor device, the aspect ratio of the contact hole for formation of the shared contact plug can be reduced. Hence, the contact hole can be formed with high precision, and this makes it unnecessary to increase the size of the first source/drain region. As a result, a downsized semiconductor device with low wiring resistance can be fabricated.
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FIG. 1 is a cross-sectional view of a semiconductor device of Embodiment 1 of the present invention. -
FIGS. 2A to 2C are cross-sectional views sequentially illustrating process steps of a fabrication method for the semiconductor device of Embodiment 1 of the present invention. -
FIGS. 3A to 3C are cross-sectional views sequentially illustrating process steps of the fabrication method for the semiconductor device of Embodiment 1 of the present invention. -
FIGS. 4A and 4B are cross-sectional views sequentially illustrating process steps of the fabrication method for the semiconductor device of Embodiment 1 of the present invention. -
FIG. 5 is a cross-sectional view illustrating a process step of the fabrication method for the semiconductor device of Embodiment 1 of the present invention. -
FIG. 6 is a cross-sectional view of a semiconductor device of Embodiment 2 of the present invention. -
FIGS. 7A and 7B are cross-sectional views sequentially illustrating process steps of a fabrication method for the semiconductor device of Embodiment 2 of the present invention. -
FIGS. 8A and 8B are cross-sectional views sequentially illustrating process steps of the fabrication method for the semiconductor device of Embodiment 2 of the present invention. -
FIG. 9 is a cross-sectional view of a semiconductor device of an alteration to Embodiment 2 of the present invention. -
FIG. 10 is a cross-sectional view of a conventional semiconductor device. -
FIG. 1 shows a cross-sectional configuration of a semiconductor device of Embodiment 1 of the present invention. As shown inFIG. 1 , the semiconductor device of this embodiment has alocal interconnect structure 60 composed of aSiGe layer 61 formed to extend over the top surfaces of a first source/drain region 29A, asidewall 43A and agate interconnect 42. - As shown in
FIG. 1 , an n-type well 16 is formed in asemiconductor substrate 11 made of silicon (Si), and anactive region 18 surrounded with anisolation region 17 is formed in the n-type well 16. A p-type MIS transistor 12 is formed in theactive region 18. - The
MIS transistor 12 includes agate electrode 22 formed on theactive region 18 with agate insulating film 21 interposed therebetween and sidewalls 23 formed on both side faces of thegate electrode 22. Each of thesidewalls 23 has an offsetsidewall 24 having a plate-shaped cross-section, aninner sidewall 25 having an L-shaped cross-section and anouter sidewall 26 covering theinner sidewall 25. - P-
type extension regions active region 18 located on both sides of thegate electrode 22. First and second p-type source/drain regions active region 18 located outside of therespective sidewalls 23. - A
gate interconnect 42 is formed on theactive region 18, with an insulatingfilm 41 interposed therebetween, at a position opposite to thegate electrode 22 with respect to the first source/drain region 29A. Asidewall 43A is formed on one of the side faces of thegate interconnect 42 closer to the first source/drain region 29A, and asidewall 43B is formed on the other side face of thegate interconnect 42. Thesidewall 43A is lower in height than thesidewall 43B, with part of the side face of thegate interconnect 42 closer to the first source/drain region 29A being left uncovered with thesidewall 43A. - Each of the
sidewalls sidewall 44 having a plate-shaped cross-section, aninner sidewall 45 having an L-shaped cross-section and anouter sidewall 46 covering theinner sidewall 45. - The first source/
drain region 29A and thegate interconnect 42 are electrically connected to each other via the silicon-germanium (SiGe)layer 61 that constitutes thelocal interconnect structure 60. This can reduce the wiring resistance between the first source/drain region 29A and thegate interconnect 42. Acontact plug 62 is formed on the portion of theSiGe layer 61 that buries the depression on the first source/drain region 29A via asilicide layer 67. Likewise, acontact plug 66 is formed on the portion of aSiGe layer 65 that buries the depression on the second source/drain region 29B via thesilicide layer 67. The contact plugs 62 and 66 are formed through an underlying insulatingfilm 71 and aninterlayer insulating film 72 formed sequentially to cover thegate electrode 22, thegate interconnect 42 and the SiGe layers 61 and 65. - In the semiconductor device of this embodiment, as shown in
FIG. 1 , theSiGe layer 61 is used as thelocal interconnect structure 60 for connecting the first source/drain region 29A with thegate interconnect 42. Hence, thecontact plug 62 reaching thesilicide layer 67 on theSiGe layer 61 is not required to be large, but can be of the same size as thecontact plug 66 reaching thesilicide layer 67 on theSiGe layer 65. In formation of the contact holes through the underlying insulatingfilm 71 and the interlayer insulatinglayer 72, therefore, there will arise no etching critical dimension according to the difference in opening area. Thus, the dimensions of the contact plugs 62 and 66 can be easily controlled without the necessity of increasing the size of the first source/drain region 29A. As a result, the semiconductor device can be downsized. - The SiGe layers 61 and 65 are formed to bury the depressions in the top portions of the first and second source/
drain regions MIS transistor 12. This improves the mobility of hole carriers, and thus can improve the driving force of the p-type MIS transistor. - In this embodiment, the top portions of the SiGe layers 61 and 65 and the
gate electrode 22 are silicified to form thesilicide layer 67. The contact plugs 62 and 66 are therefore in contact with the SiGe layers 61 and 65 via thesilicide layer 67. This can further reduce the wiring resistance. - Hereinafter, a fabrication method for the semiconductor device of Embodiment 1 will be described with reference to
FIGS. 2A to 2C, 3A to 3C, 4A, 4B and 5 . First, as shown inFIG. 2A , anisolation region 17 is formed in thesemiconductor substrate 11 made of Si, to define theactive region 18 surrounded with theisolation region 17. N-type impurity ions are implanted in thesemiconductor substrate 11 to form the n-type well 16. Subsequently, an insulating film made of SiO2 and the like having a thickness of about 2 nm and a polysilicon film having a thickness of about 100 nm are sequentially formed on thesemiconductor substrate 11. The polysilicon film and the insulating film are then selectively etched, to form thegate insulating film 21 and thegate electrode 22 on theactive region 18, and also the insulatingfilm 41 and thegate interconnect 42 at a position on theactive region 18 spaced from thegate electrode 22. Note that the insulatingfilm 41 and thegate interconnect 42 are not necessarily formed on theactive region 18 but may be formed on theisolation region 17. A resist mask or a hard mask may be used as an etching mask for the polysilicon film and the insulating film. - Thereafter, an insulating film made of SiO2 and the like is formed on the
semiconductor substrate 11 and then etched back, to form the offset sidewalls 24 and 44 on the side faces of thegate electrode 22 andgate interconnect 42, respectively. - Using the
gate electrode 22 and the offset sidewalls 24 as a mask, a p-type impurity is implanted in theactive region 18 to form the p-type extension regions - Subsequently, a silicon oxide film and a silicon nitride film are sequentially deposited on the
semiconductor substrate 11 and then etched back. This results in formation of theinner sidewalls 25 made of the silicon oxide film and theouter sidewalls 26 made of the silicon nitride film on both side faces of thegate electrode 22 via the offsetsidewalls 24, as well as formation of theinner sidewalls 45 made of the silicon oxide film and theouter sidewalls 46 made of the silicon nitride film on both side faces of thegate interconnect 42 via the offsetsidewalls 44. Hence, thesidewalls 23 are formed on both side faces of thegate electrode 22, thesidewall 43A is formed on the side face of thegate interconnect 42 closer to thegate electrode 22, and thesidewall 43B is formed on the other side face of thegate interconnect 42. - A p-type impurity is then implanted in the
active region 18 using thegate electrode 22 and thesidewalls 23 as a mask, to form the p-type first and second source/drain regions active region 18 located outside of thesidewalls 23. - As shown in
FIG. 2B , aprotection film 81 made of SiO2 and the like having a thickness of about 50 nm is formed on the entire surface of thesemiconductor substrate 11. - As shown in
FIG. 2C , theprotection film 81 is partly removed to expose the first and second source/drain regions gate interconnect 42 and thesidewall 43A, while being left unremoved on thegate electrode 22 not to expose the top surface of thegate electrode 22. - As shown in
FIG. 3A , using theprotection film 81 and thesidewalls 23 as a mask, thesemiconductor substrate 11 is etched, to formdepressions active region 18 where the first and second source/drain regions gate interconnect 42 is etched at its top portion, to become lower in height than thegate electrode 22 and thesidewall 43B. Thesidewall 43A is also etched to become lower in height than thesidewall 43B. Thesidewall 43A is further etched selectively to expose the upper part of the side face of thegate interconnect 42 closer to thegate electrode 22. The etching may be made by dry etching, wet etching using an organic alkaline etchant or a combined method thereof. - As shown in
FIG. 3B , a p-type SiGe layer is epitaxially grown on the top surface of thegate interconnect 42, the side face of thegate interconnect 42, the top surface of the first source/drain region 29A and the top surface of the second source/drain region 29B, on all of which Si is exposed. In this way, theSiGe layer 61 is formed to extend over the top surfaces of the first source/drain region 29A and thegate interconnect 42, and theSiGe layer 65 is formed on the second source/drain region 29B. The first source/drain region 29A and thegate interconnect 42 are therefore electrically connected with each other. The portion of theSiGe layer 61 located on the first source/drain region 29A and theSiGe layer 65 respectively bury thedepressions semiconductor substrate 11. The SiGe layers 61 and 65 may be formed by low-pressure chemical vapor deposition (low-pressure CVD) using silane gas (SiH4), germane gas (GeH4) and a p-type dopant such as diborane (B2H6). - As shown in
FIG. 3C , theprotection film 81 is selectively removed. - As shown in
FIG. 4A , a metal film having a high melting point such as nickel (Ni) is deposited on thesemiconductor substrate 11 to a thickness of several nanometers and then heat-treated, to silicify the top portions of the SiGe layers 61 and 65, thegate interconnect 42 and thegate electrode 22, to thereby form thesilicide layer 67. The unreacted remainder of the metal film is then removed. - As shown in
FIG. 4B , the underlying insulatingfilm 71 made of silicon nitride is formed on the entire surface of thesemiconductor substrate 11, and then theinterlayer insulating film 72 made of silicon oxide is formed on the underlying insulatingfilm 71. Thereafter, acontact hole 72 a and acontact hole 72 b are formed through theinterlayer insulating film 72 and the underlying insulatingfilm 71 to reach the portion of thesilicide layer 67 on theSiGe layer 61 and the portion thereof on theSiGe layer 65, respectively. Note that thecontact hole 72 a may be formed at any position as long as it reaches thesilicide film 67 on theSiGe layer 61. Hence, in place of the position above the first source/drain region 29A as in the illustrated example, thecontact hole 72 a may be formed at a position above thegate interconnect 42, for example. - As shown in
FIG. 5 , the contact holes 72 a and 72 b are buried with a conductive material such as tungsten, to form thecontact plug 62 connected to theSiGe layer 61 via thesilicide layer 67 and thecontact plug 66 connected to theSiGe layer 65 via thesilicide layer 67. - In the fabrication method for the semiconductor device of this embodiment, the
SiGe layer 61 is used as the local interconnect structure for connecting the first source/drain region 29A with thegate interconnect 42. Hence, unlike the local interconnect structure made of the conventional sharedcontact 108 as shown inFIG. 10 , it is unnecessary to form a large contact hole. In other words, in this embodiment, in which the first source/drain region 29A and thegate interconnect 42 are connected with each other via theSiGe layer 61, thecontact hole 72 a reaching thesilicide layer 67 on theSiGe layer 61 is not required to be large, but can be of the same size as thecontact hole 72 b reaching thesilicide layer 67 on theSiGe layer 65. Accordingly, with no etching critical dimension occurring according to the difference in contact hole opening area, the contact holes can be formed with high precision. This makes it possible to reduce the size of the first source/drain region 29A, and thus the semiconductor device can be downsized. In the configuration of connecting thecontact hole 72 a to theSiGe layer 61 at a position above thegate interconnect 42, also, thecontact hole 72 a can be of the same size as thecontact hole 72 b. The contact holes can therefore be formed with high precision. - Also, in the fabrication method for the semiconductor device of this embodiment, the
sidewall 43A is made short to expose part of the side face of thegate interconnect 42 closer to the first source/drain region 29A. TheSiGe layer 61 therefore grows also on the side face of thegate interconnect 42, and this ensures the connection between the SiGe layer grown on the first source/drain region 29A and the SiGe layer grown on thegate interconnect 42. Note that it is not necessarily required to expose the side face of thegate interconnect 42 closer to the first source/drain region 29A if only theSiGe layer 61 can be formed to extend over the top surfaces of the first source/drain region 29A and thegate interconnect 42. - In this embodiment, the
depressions drain regions depressions depressions SiGe layer 65 may not be formed on the second source/drain region 29B. Like the p-type MIS transistor, an n-type MIS transistor may be formed in a similar manner. In this case, it is unnecessary to form depressions on the source/drain regions. - Embodiment 2 of the present invention will be described with reference to the relevant drawings.
FIG. 6 shows a cross-sectional configuration of a semiconductor device of Embodiment 2. InFIG. 6 , the same components as those inFIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here. - As shown in
FIG. 6 , the semiconductor device of this embodiment has alocal interconnect structure 60 composed of aSiGe layer 61 formed on a first source/drain region 29A and a sharedcontact plug 63 connected to part of theSiGe layer 61 and part of agate interconnect 42. - In this embodiment, the shared
contact plug 63 is greater in size than acontact plug 66. However, with theSiGe layer 61 protruding from the top surface of thesemiconductor substrate 11, the aspect ratio of the contact hole for formation of the sharedcontact plug 63 can be reduced. The requirements of etching precision of the contact hole can therefore be widely eased. Hence, it is unnecessary to increase the size of the first source/drain region 29A, and thus the semiconductor device can be downsized. - Hereinafter, a fabrication method for the semiconductor device of Embodiment 2 will be described with reference to
FIGS. 7A, 7B, 8A and 8B . The process steps up to the formation of the first and second source/drain regions - As shown in
FIG. 7A , after the formation of the first and second source/drain regions protection film 81 made of SiO2 and the like is formed on the entire surface of thesemiconductor substrate 11, and then the portion thereof overlying the first source/drain region 29A is removed. Theprotection film 81 is therefore left behind covering thegate electrode 22, thegate interconnect 42 and the second source/drain region 29B. - As shown in
FIG. 7B , theSiGe film 61 is epitaxially grown on the top surface of the first source/drain region 29A on which Si is exposed, to obtain theSiGe film 61 protruding from thesemiconductor substrate 11. - As shown in
FIG. 8A , after selective removal of theprotection film 81, a metal film having a high melting point such as nickel (Ni) is deposited on thesemiconductor substrate 11 to a thickness of several nanometers and then heat-treated, to silicify the top portions of theSiGe layer 61, thegate electrode 22, thegate interconnect 42 and the second source/drain region 29B, to form asilicide layer 67. After removal of the unreacted remainder of the metal film, an underlying insulatingfilm 71 made of a silicon nitride film is formed on the entire surface of thesemiconductor substrate 11, and then aninterlayer insulating film 72 made of a silicon oxide film is formed on the underlying insulatingfilm 71. Subsequently, acontact hole 72 a and acontact hole 72 b are formed through theinterlayer insulating film 72 and the underlying insulatingfilm 71, to reach the portions of thesilicide layer 67 on theSiGe layer 61 and thegate interconnect 42 and to reach the portion of thesilicide layer 67 on the second source/drain region 29B, respectively. In this relation, thesidewall 43A exposed in thecontact hole 72 a may be etched selectively to make thesidewall 43A lower in height than thegate interconnect 42 to thereby expose part of the side face of thegate interconnect 42 closer to thegate electrode 22. - As shown in
FIG. 8B , the contact holes 72 a and 72 b are buried with a conductive material such as tungsten, to form the sharedcontact plug 63 connected to theSiGe layer 61 and thegate interconnect 42 via thesilicide layer 67 and thecontact plug 66 connected to the second source/drain region 29B via thesilicide layer 67. - In this embodiment, no SiGe layer is formed on the second source/
drain region 29B. Alternatively, a SiGe layer may be formed on the second source/drain region 29B. Also, as in Embodiment 1, depressions may be formed in the top portions of the first and second source/drain regions SiGe layer 61 formed on the first source/drain region 29A should protrude above the top surface of thesemiconductor substrate 11 sufficiently to ensure that the aspect ratio of thecontact hole 72 a is not large. - An alteration to Embodiment 2 of the present invention will be described with reference to the relevant drawings.
FIG. 9 shows a cross-sectional configuration of a semiconductor device of an alteration to Embodiment 2 of the present invention. As shown inFIG. 9 , the semiconductor device of this alteration has alocal interconnect structure 60 composed of afirst SiGe layer 61A formed on the first source/drain region 29A, asecond SiGe layer 61B formed on thegate interconnect 42 and a sharedcontact plug 63 connected to part of thefirst SiGe layer 61A and part of thesecond SiGe layer 61B. - With the above configuration, the
second SiGe layer 61B on thegate interconnect 42 extends toward thesidewall 43A, narrowing the space between the first and second SiGe layers 61A and 61B. Hence, the contact hole for the sharedcontact plug 63 can be made small compared with the configuration without thesecond SiGe layer 61B. - In this alteration, also, the SiGe layer may be formed also on the second source/
drain region 29B, and depressions may be formed in the top portions of the first and second source/drain regions gate interconnect 42 and thesidewall 43A are the same in height, thesidewall 43A may be made lower in height than thegate interconnect 42 to expose part of the side face of thegate interconnect 42 closer to thegate electrode 22. - The semiconductor devices of the above embodiments and alteration respectively have a contact plug electrically connected to the second source/drain region. Such a contact plug connected to the second source/drain region is not necessarily required. Also, a contact plug connected to the gate electrode may be provided.
- In the above embodiments and alteration, the SiGe layer was formed after formation of the source/drain regions. Alternatively, the source/drain regions may be formed by ion implantation after formation of the SiGe layer. SiO2 was used as the material of the gate insulating film. Alternatively, a film having a high dielectric constant (high-K film) made of hafnium dioxide (HfO2), a hafnium silicate (HfSiOx (x>1) or the like, in place of SiO2, may be used.
- In the above embodiments and alteration, part of the gate interconnect was formed on the active region. Alternatively, the entire of the gate interconnect may be formed on the isolation region, or on the active region.
- The semiconductor devices of the above embodiments and alteration can be used for a MIS transistor constituting part of a SRAM cell, or may be applied to a MIS transistor constituting part of another circuit section such as a logic section. Otherwise the inventive semiconductor devices can be used for devices other than memory.
- As described above, according to the present invention, a semiconductor device provided with a local interconnect structure involving no increase in the size of source/drain regions can be implemented, and thus the present invention is useful as a semiconductor device having a local interconnect structure and a fabrication method for such a semiconductor device.
- The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims (1)
1. A semiconductor device comprising:
a gate electrode formed on an active region of a semiconductor substrate;
a first silicon-germanium layer formed in a first depression provided in a portion of the active region;
the first silicon-germanium layer comprising silicon, germanium, or some combination thereof;
a gate interconnect formed at a position opposite to the gate electrode with respect to the first depression;
a first contact plug comprised of tungsten;
a first sidewall formed on the side face of the gate interconnect closer to the first depression;
a second sidewall formed on the other side face of the gate interconnect;
wherein in a cross-sectional configuration, the first sidewall is lower in height than the second sidewall, and the gate interconnect is formed at least partly on the active region.
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US13/687,407 US9287392B2 (en) | 2007-10-31 | 2012-11-28 | Semiconductor device and fabrication method for the same |
US15/013,946 US9780039B2 (en) | 2007-10-31 | 2016-02-02 | Semiconductor device and fabrication method for the same |
US15/679,836 US10804203B2 (en) | 2007-10-31 | 2017-08-17 | Semiconductor device and fabrication method for the same |
US17/068,804 US20210028114A1 (en) | 2007-10-31 | 2020-10-12 | Semiconductor device and fabrication method for the same |
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US17/068,804 Abandoned US20210028114A1 (en) | 2007-10-31 | 2020-10-12 | Semiconductor device and fabrication method for the same |
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US9287392B2 (en) | 2016-03-15 |
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JP2009111200A (en) | 2009-05-21 |
US9780039B2 (en) | 2017-10-03 |
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