JP4160846B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MIS type semiconductor device having a shared contact and a manufacturing method thereof, and more particularly, to an SRAM having a shared contact and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, further miniaturization is required in the field of MIS type transistors, and various methods are being studied. As one of the methods, there is a method of forming a shared contact that is a common contact from above the gate electrode of one MIS type transistor to the source or drain region of another MIS type transistor ( For example, see Patent Document 1).
[0003]
Hereinafter, a case where the shared contact is used for the SRAM memory cell will be described with reference to FIGS. 9A and 9B. FIG. 9A is a plan view showing a structure of an SRAM provided with a conventional shared contact.
[0004]
As shown in FIG. 9A, in the conventional SRAM memory cell, the PMIS transistors 405a and 405b for loading, the NMIS transistors 406a and 406b for driver, and the NMIS transistor 407a for accessing are included in the semiconductor layer 401. , 407b. Each transistor is provided in the active region R of the semiconductor layer 401, and the side of the active region R is surrounded by an isolation insulating film 402 made of an insulator.
[0005]
The gate electrode 420 of the driver NMIS transistor 406a and the gate electrode 408 of the load PMIS transistor 405a are part of the same wiring layer 410, respectively. The wiring layer 410 extends to the side of the source region 409 of the load PMIS transistor 405b. In addition, a shared contact 421 is provided from above the region located on the side of the source region 409 in the wiring layer 410 to above the source region 409. On the other hand, the gate electrode 423 of the driver NMIS transistor 406b and the gate electrode 424 of the load PMIS transistor 405b are part of the same wiring layer 425. The wiring layer 425 extends to the side of the source region 426 of the load PMIS transistor 405a. In addition, a shared contact 404 is provided over a region located on the side of the source region 426 in the wiring layer 425 and over the source region 426. A drain contact 420 is formed on the drain region 422 of the PMIS transistor 405a. A gate electrode 408 of a PMIS transistor 405a is formed on one side of the drain region 422, and a gate electrode 419 of another PMIS transistor is formed on the other side.
[0006]
[Patent Literature]
JP-A-9-199586
[0007]
[Problems to be solved by the invention]
However, the following problems have occurred in the conventional semiconductor device.
[0008]
FIG. 9B is a cross-sectional view taken along the line (IX)-(IX) showing the structure of the conventional SRAM provided with the shared contact. The opening 415 for providing the shared contact 404 is formed by selectively removing the interlayer insulating film 414 by anisotropic dry etching and then removing the liner insulating film 413 by dry etching. However, in this step, a portion of the sidewall spacer 412 exposed at the surface of the opening 415 is etched, so that the sidewall spacer 412 becomes smaller than the other sidewall spacers 416.
[0009]
Furthermore, depending on the degree of process variation, the sidewall spacer 412 may be almost completely removed, and the shallow p-type impurity region 411 provided under the sidewall spacer 412 may be exposed. If the opening 415 is filled with the metal of the contact material with the shallow p-type impurity region 416 exposed, the shallow p-type impurity region 411 and the metal come into contact with each other. As a result, a junction leakage current is generated from the semiconductor layer 401 to the shared contact, so that the yield is reduced.
[0010]
The object of the present invention is to reduce the yield due to the occurrence of junction leakage current by taking measures to increase the process margin against the reduction of the film thickness of the sidewall spacer exposed at the opening when forming the shared contact. A semiconductor device and a manufacturing method thereof are provided.
[0011]
[Means for Solving the Problems]
A first semiconductor device of the present invention includes a semiconductor layer having a plurality of active regions including a first active region and a second active region, and a side of the plurality of active regions, at least a part of which is the semiconductor An isolation insulating film provided higher than the layer, a first element provided in the first active region and having a first electrode, a part of which is the first electrode, and the other one A first wiring layer extending on the isolation insulating film and on a side of the first wiring layer, and located on a side of the other part of the first wiring layer. In the portion, a first sidewall spacer in contact with the boundary between the isolation insulating film and the second active region, and a self-alignment provided in the second active region, using the first sidewall spacer as a mask. A second element having a first impurity diffusion layer formed on the substrate; and A second impurity diffusion layer provided in a region interposed between the first impurity diffusion layer and the isolation insulating film, and above the semiconductor layer and the isolation insulating film. The interlayer insulating film, a part of the first impurity diffusion layer, a part of the first sidewall spacer, and a part of the first wiring layer are provided over the interlayer insulating film. A first shared contact.
[0012]
As a result, the film thickness reduction of the portion of the first sidewall spacer located below the first shared contact is suppressed, so that the contact between the first shared contact and the second impurity diffusion layer is prevented. be able to. Thereby, it is possible to suppress a decrease in yield due to the occurrence of junction leakage current.
[0013]
In the boundary, the height of the upper surface of the semiconductor layer in the second active region is higher by 10 nm or more and 30 nm or less than the height of the upper surface of the isolation insulating film, whereby the semiconductor layer and the isolation insulating film It is possible to more reliably suppress the film loss of the first sidewall spacer without increasing the residue in the step portion.
[0014]
It is preferable that an end of the first sidewall spacer on the side in contact with the first wiring layer is provided on the boundary.
[0015]
The first MIS transistor is a first MIS transistor for loading, is provided in the second active region, has a second MIS transistor having a gate electrode, and one of the plurality of active regions. And a first driver MIS transistor having a gate electrode which is a part of the first wiring layer and a second MIS transistor provided in one of the plurality of active regions and having a gate electrode. The driver MIS transistor, the gate electrode of the second load MIS transistor, and the gate electrode of the second driver MIS transistor are included as a part, and the other part is the isolation insulating film. A second wiring layer extending above the second wiring layer and a side of the second wiring layer, and in the portion located on the side of the other part of the second wiring layer, the separation is performed. A second sidewall spacer in contact with a boundary between the insulating film and the semiconductor layer; a portion of the first active region; a portion of the second sidewall spacer; and the second extension portion. By further including the second shared contact provided over the top, it is possible to miniaturize the SRAM without decreasing the yield.
[0016]
A second semiconductor device of the present invention includes a semiconductor layer, an isolation insulating film surrounding an active region made of the semiconductor layer, and having at least a part of the upper surface higher than the upper surface of the semiconductor layer, and the isolation A wiring layer formed on the insulating film, a sidewall spacer provided on a side of the wiring layer, at least a part of which is in contact with a boundary between the isolation insulating film and the active region, and the active layer An impurity diffusion layer formed in the region, an interlayer insulating film provided above the semiconductor layer, an opening formed in the interlayer insulating film and reaching the impurity diffusion layer, and formed in the opening And the opening is formed over a part of each of the wiring layer, the sidewall spacer, and the impurity diffusion layer, and the contact causes the wiring layer and the impurity to be impure. A diffusion layer are electrically connected.
[0017]
As a result, film thickness reduction of the portion of the sidewall spacer located below the contact is suppressed, so that contact between the contact and the impurity diffusion layer can be prevented. Thereby, it is possible to suppress a decrease in yield due to the occurrence of junction leakage current.
[0018]
The first method for manufacturing a semiconductor device of the present invention includes a step (a) of forming an isolation insulating film surrounding the first active region and the second active region, which are part of the semiconductor layer, and Forming a first wiring layer having a portion extending above the first active region and another portion extending above the isolation insulating film; and masking the first wiring layer (C) performing ion implantation into the second active region, and a first sidewall spacer on the side surface of the first wiring layer, and the other part of the first wiring layer. A step (d) of forming a contact with the boundary between the isolation insulating film and the semiconductor layer on the side of the first active layer, and the second activity using the first wiring layer and the first sidewall spacer as a mask. A step (e) of ion-implanting the region, the semiconductor layer and the isolation insulating film A step (f) of forming an interlayer insulating film covering the upper side, a part of the second active region, a part of the first sidewall spacer, and the first wiring in the interlayer insulating film; A step (g) of forming a first opening by removing a region extending above the other part of the layer; and a first shared contact by filling the first opening with a conductor. Forming (h).
[0019]
Accordingly, in the step (d), the height of the portion of the first sidewall spacer that is in contact with the semiconductor layer can be increased. Therefore, in the step (g), the first sidewall spacer film is formed. Since the reduction can be reduced, in step (h), the impurity diffusion layer formed in step (e) and the shared contact are difficult to contact. Thereby, it is possible to suppress a decrease in yield due to the occurrence of junction leakage current.
[0020]
In the step (g), it is preferable that dry etching of the interlayer insulating film is selectively performed on the first sidewall spacer in order to form the first opening.
[0021]
In the step (a), the upper surface of the isolation insulating film is formed higher than the upper surface of the semiconductor layer by not less than 10 nm and not more than 30 nm, thereby reducing the residue in the step portion between the semiconductor layer and the isolation insulating film. In addition, film loss of the first sidewall spacer can be suppressed.
[0022]
In the step (g), a part of the interlayer insulating film is removed to form a contact opening for the gate electrode and an opening for the source / drain. In the step (h), The opening for the gate electrode and the opening for the source / drain can be filled with a conductor.
[0023]
In the step (a), the isolation active film surrounds the sides of the third active region and the fourth active region that are part of the semiconductor layer. In the step (b), the first active region As part of the wiring layer, a gate electrode is formed on the third active region, and a part of the gate electrode is located above the second active region and above the fourth active region. A second wiring layer is formed, the other part of which extends above the isolation insulating film. In the step (c), the second wiring layer is used as a mask to form the first wiring layer. In the step (d), a second sidewall spacer is formed on the side surface of the second wiring layer, and the other part of the second wiring layer is laterally formed. In contact with the boundary between the isolation insulating film and the semiconductor layer. In the step (e), ions are implanted into the first active region using the second wiring layer and the second sidewall spacer as a mask. In the step (g), among the interlayer insulating films, A second opening is formed by removing a region extending above the first active region, a part of the second sidewall spacer, and the other part of the second wiring layer. In the step (h), the second shared contact is formed by filling the second opening, so that even the SRAM can be miniaturized without a decrease in yield.
[0024]
Before the step (a), the method further includes a step (i) of forming a stopper film covering the semiconductor layer. In the step (a), a part of the stopper film, a part of the semiconductor layer, After forming the groove by removing the trench and filling the groove with an insulator, a photoresist covering at least the first shared contact and the second shared contact is formed, and the photoresist is used as a mask. By forming the isolation insulating film by etching the insulating film, the isolation insulating film does not depend on the density of the pattern ratio in the region where the first shared contact and the second shared contact are formed. A step between the film and the semiconductor layer can be secured.
[0025]
The semiconductor layer includes an SRAM cell region in which the first shared contact and the second shared contact are provided, and a peripheral region that is an area excluding the SRAM cell region. In the step (a), By removing a part of the insulating film in the peripheral region by performing the etching, the isolation insulating film and the semiconductor in the SRAM cell region are obtained even when the pattern rate in the peripheral region is higher than that in the SRAM cell region. A step between the layers can be secured.
[0026]
According to a second method of manufacturing the semiconductor device of the present invention, the step (a) of forming an isolation insulating film having an upper surface higher than the upper surface of the active region surrounding the active region formed of a part of the semiconductor layer, A step (b) of forming a wiring layer on the isolation insulating film; and a side wall spacer having at least a part of the bottom surface in contact with a boundary between the isolation insulating film and the active region on the side surface of the wiring layer. A step (c) of forming, and a step (d) of forming an impurity diffusion layer by implanting ions into the active region using the sidewall spacer as a mask, and after the step (d), above the semiconductor layer A step (e) of forming an interlayer insulating film on the substrate, a step (f) of forming an opening reaching the impurity diffusion layer in the interlayer insulating film, and a step (g) of forming a contact in the opening. Comprising the step (f) In the step (g), the opening over the wiring layer, the sidewall spacer, and the impurity diffusion layer is formed. In the step (g), the wiring layer and the impurity diffusion layer are formed by the contact. Are electrically connected.
[0027]
As a result, the sidewall spacer can be formed high in the step (c), so that the film thickness of the sidewall spacer can be reduced in the step (f), and the impurity diffusion layer and the shared contact are in contact with each other. A difficult semiconductor device can be obtained. Thereby, it is possible to suppress a decrease in yield due to the occurrence of junction leakage current.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, in the first to third embodiments, a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
[0029]
(First embodiment)
FIG. 1A is a plan view showing the structure of the semiconductor device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along line (I)-(I) shown in FIG.
[0030]
As shown in FIG. 1A, the semiconductor device of this embodiment includes a semiconductor layer 101 and an isolation insulating film 102 that separates the semiconductor layer 101 into active regions R by surrounding the sides of the semiconductor layer 101. have. An element 120 is provided in the active region R of the semiconductor layer 101, and an element 121 is provided in the active region R separated from the element 120 by the isolation insulating film 102.
[0031]
The element 120 includes a source region 122 and a drain region 123 provided in the semiconductor layer 101, a gate electrode 124 provided on the semiconductor layer 101 with a gate insulating film (not shown) interposed therebetween, and a source region 122 A source contact 125 provided above and a drain contact 126 provided on the drain region 123 are provided.
[0032]
On the other hand, the element 121 includes a source region 127 and a drain region 128 provided in the semiconductor layer 101, a gate electrode 129 provided on the semiconductor layer 101 with a gate insulating film (not shown) interposed therebetween, and a drain region. And a drain contact 130 provided thereon.
[0033]
The gate electrode 124 of the element 120 is a part of the wiring layer 105, and the wiring layer 105 extends to a portion of the isolation insulating film 102 that is located on the side of the source region 127 of the element 121. A shared contact 113 is provided from above the portion of the wiring layer 105 located on the side of the source region 127 to above the source region 127.
[0034]
Here, although not shown in FIG. 1A, sidewall spacers are provided on the side surfaces of the wiring layer 105. Hereinafter, the sidewall spacer will be described with reference to FIG.
[0035]
As illustrated in FIG. 1B, the wiring layer 105 is provided on the isolation insulating film 102 and extends to the side of the source region 127. The wiring layer 105 is provided so that its side surface is along the outline of the isolation insulating film 102. The side wall spacer 108 surrounds the side of the wiring layer 105, and is classified into two types, that is, the side wall spacers 108a and 108b, depending on the provided region. The sidewall spacer 108 a is a portion provided on the side facing the semiconductor layer 101 on the side surface of the wiring layer 105, and the sidewall spacer 108 b is facing the isolation insulating film 102 on the side surface of the wiring layer 105. The part provided on the side. A shared contact 113 formed by embedding a barrier film and a metal film is provided in an opening 112 provided in the gate insulating film 103, the liner film 110, and the interlayer insulating film 111 formed on the substrate. . The shared contact 113 is provided so as to be in contact with the wiring layer 105, the sidewall spacer 108 a, and the source region 127 in the semiconductor layer 101. By this shared contact 113, the source region 127 and the wiring layer 105 are electrically connected.
[0036]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 2A to 2G are cross-sectional views taken along the line (I)-(I) showing the manufacturing process of the semiconductor device according to the first embodiment.
[0037]
First, in the step shown in FIG. 2A, after the region surrounding the active region R in the n-type semiconductor layer 101 is removed and filled with an insulating film, the isolation insulating film 102 having a depth of 300 nm is formed. The gate insulating film 103 having a thickness of 2 nm is formed by oxidizing the upper portion of the active region R of the conductor layer 101. Thereafter, a polycrystalline silicon film 104 having a thickness of 150 nm is formed on the gate insulating film 103. Here, the isolation insulating film 102 is formed so that its upper surface is higher by 20 nm than the upper surface of the semiconductor layer 101. Here, the difference in height between the isolation insulating film 102 and the semiconductor layer 101 is preferably 10 nm to 30 nm.
[0038]
By oxidizing the upper part of the active region R of the semiconductor layer 101, a gate insulating film 103 having a thickness of 2 nm is formed. A 150 nm-thick polycrystalline silicon film 104 is formed on the gate insulating film 103.
[0039]
Next, in the step shown in FIG. 2B, a photoresist layer (not shown) is formed on the polycrystalline silicon film 104, and dry etching is performed using the photoresist layer as a mask, whereby the wiring layer 105 is formed. Form. Here, as shown in FIG. 1A, a part of the wiring layer 105 serves as the gate electrode 124 of the MISFET. Further, the wiring layer 105 is provided so as to extend over the isolation insulating film 102 and to have its end portion in contact with the end portion of the active region R of the element 121. After the wiring layer 105 is formed, the photoresist layer (not shown) is removed. At this time, the end of the wiring layer 105 may be displaced from the boundary of the active region R in the range up to 40 nm due to misalignment of the mask when forming the photoresist layer.
[0040]
Next, in the step shown in FIG. 2C, boron (B) is ion-implanted into the active region R of the semiconductor layer 101 at an implantation energy of 3 KeV, thereby forming a shallow p-type impurity having a depth of 20 nm that becomes an SD extension region. Region 106 is formed. Thereafter, a silicon nitride film 107 having a thickness of 60 nm is deposited on the semiconductor layer 101.
[0041]
Next, sidewall spacers 108 made of silicon nitride are formed on the side surfaces of the wiring layer 105 by performing anisotropic dry etching in the step shown in FIG. Here, the side wall spacer 108 surrounds the side of the wiring layer 105, and is classified into two types, that is, the side wall spacers 108a and 108b, depending on the provided region. The width of the lower surface of the sidewall spacer 108a is typically 55 nm.
[0042]
Conventionally, as shown in FIG. 9B, both the wiring layer 410 and the sidewall spacer 412 are provided on the semiconductor layer 401. In contrast, in the present embodiment, the wiring layer 105 is formed on the isolation insulating film 102, and the sidewall spacer 108 a extends to the semiconductor layer 101. As described above, since the isolation insulating film 102 is formed higher than the semiconductor layer 101, the sidewall spacer 108a of this embodiment is formed higher by the height. Here, a typical height of the sidewall spacer 108a is a height from the semiconductor layer 101 to 170 nm.
[0043]
Further, the width of the lower surface of the sidewall spacer 108a varies. This variation in the width of the lower surface is considered to be caused by a variation in the film thickness of the silicon nitride film 107 to be deposited and a variation in the surface coating characteristics of the silicon nitride. On the other hand, as described above, there is also variation depending on the position where the side surface of the wiring layer 105 is formed, and the side surface of the wiring layer 105 is displaced from the boundary between the active region R and the isolation insulating film 102 within a range of 40 nm. May be formed. Considering these two variations, it is preferable to set the width of the lower surface of the sidewall spacer 108a to 50 nm or more. When such a width is set, the sidewall spacer 108 can be more reliably formed on the boundary even when the process changes. Further, when the width of the lower surface of the sidewall spacer 108 is 100 nm or less, the size of the sidewall spacer 108 can be kept within an appropriate size as an ion implantation mask.
[0044]
Next, in the step shown in FIG. 2E, an impurity such as boron is ion-implanted at 40 KeV using the wiring layer 105 and the sidewall spacer 108 as a mask, so that the source region 127 and the drain region 128 (FIG. 1A ), A deep p-type impurity region 109 having a depth of 45 nm is formed. Subsequently, the substrate is covered with a liner film 110 made of silicon nitride and having a thickness of 20 nm, and then a silicon oxide film (not shown) having a thickness of 600 nm is deposited. Thereafter, the interlayer insulating film 111 is formed by planarizing the surface of the silicon oxide film by CMP.
[0045]
Next, a photoresist (not shown) is formed on the interlayer insulating film 111 in the step shown in FIG. Using the photoresist as a mask, anisotropic dry etching of the interlayer insulating film 111 is selectively performed on the liner film 110. Thus, an opening 112 for a shared contact is formed from above the source region 127 over a portion of the sidewall spacer 108a and the wiring layer 105 that is located on the side of the source region 127. Furthermore, by performing dry etching, the photoresist and the liner film 110 exposed on the lower surface of the opening 112 are removed. At this time, a part of the sidewall spacer 108a exposed in the opening 112 is also removed, and when the film thickness is most severe, the height of the sidewall spacer 108a is reduced to 50 nm. Thereafter, the gate insulating film 103 exposed in the opening 112 is removed.
[0046]
Next, in the step shown in FIG. 2G, after a barrier film made of titanium and titanium nitride and a metal film made of tungsten are sequentially formed on the substrate, an unnecessary metal film on the interlayer insulating film 111 is formed by CMP. By removing the barrier film, the shared contact 113 made of the barrier film and the metal film is formed in the opening 112. By this shared contact 113, the source region 127 and the wiring layer 105 are electrically connected. Thereafter, by forming a metal wiring or the like using a known process, the formation of the semiconductor device having a shared contact is completed.
[0047]
In a conventional semiconductor device having a shared contact, a wiring layer functioning as a gate electrode of one MIS type transistor extends on a semiconductor layer provided with another MIS type transistor. At this time, there was a problem that the sidewall formed on the side surface of the wiring layer was reduced. In order to reduce this problem, in this embodiment, focusing on the fact that the isolation insulating film 102 is formed higher than the semiconductor layer 101, a wiring layer 105 is formed on the isolation insulating film 102 to form a semiconductor. Sidewall spacers 108 a are formed on the layer 101. Accordingly, the height of the sidewall spacer 108a can be increased by a level difference between the semiconductor layer 101 and the isolation insulating film 102, as compared with the conventional case. From the above, when the opening 112 is formed in the step shown in FIG. 1F, a decrease in the width near the lower surface of the sidewall spacer 108a can be suppressed. This will be described below.
[0048]
In the present embodiment, as shown in FIG. 2D, the height of the sidewall spacer 108a is higher than that of the conventional one. In the side wall spacer 108a, the width from the bottom surface to the upward direction becomes narrower than that of the side wall spacer 108b having the same height as the conventional one. This is because when the silicon nitride film 107 is etched in the process shown in FIG. 2D, the portion of the silicon nitride film 107 (shown in FIG. 2C) that covers the upper end portion of the wiring layer 105 is the same. This is because the portion of the silicon nitride film 107 covering the side surface of the wiring layer 105 is difficult to remove. Therefore, after the sidewall spacer is formed, when anisotropic etching is performed from above to form the opening 112 in the step shown in FIG. 2F, the sidewall spacer 108a has the sidewall spacer. Since there are many thick portions as compared with 108b, film reduction (reduction in width) near the bottom surface is reduced.
[0049]
As described above, in this embodiment, the margin for the film thickness reduction of the sidewall spacer 108a is increased, and the shallow p-type impurity region 106 located therebelow is exposed due to the decrease in the width of the sidewall spacer 108a. Can be suppressed. Therefore, it is possible to suppress a decrease in yield due to the occurrence of junction leakage current.
[0050]
FIG. 3 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment. In the semiconductor device shown in FIG. 3, the wiring layer 132 is provided on the isolation insulating film 102 away from the outline thereof, and the sidewall spacer 131 made of a silicon nitride film is formed on the side surface of the wiring layer 132. Yes. Of the sidewall spacers 131, the sidewall spacer 131 b is provided on the isolation insulating film 102, and the sidewall spacer 131 a is provided on the isolation insulating film 102 over the semiconductor layer 101. ing. In this case, any part of the lower surface of the sidewall spacer 131 a may be provided on the boundary between the semiconductor layer 101 and the isolation insulating film 102. Also in this case, since the height of the sidewall spacer 131a is higher than that in the conventional case, the width becomes thicker than in the conventional case. Therefore, if anisotropic etching is performed from above to form a shared contact, the reduction in the width of the lower surface of the sidewall spacer 131a can be reduced.
[0051]
In this embodiment, the gate insulating film 103 is left on the semiconductor layer 101. However, after the gate electrodes 124 and 129 are formed, the gate insulating film 103 other than the portion located below the gate electrodes 124 and 129 is formed. May be removed. Instead, in the step shown in FIG. 2C, an oxide film having a thickness of about 5 nm is formed on the entire surface of the substrate before the silicon nitride film 107 is formed, and then the silicon nitride film 107 is formed on the oxide film. May be formed.
[0052]
(Second Embodiment)
In the second embodiment, a case where the structure described in the first embodiment is applied to an SRAM will be described.
[0053]
FIG. 4A is a circuit diagram showing the memory cell of the semiconductor device in the second embodiment, and FIG. 4B is a plan view showing the structure of the semiconductor device (SRAM) in the second embodiment.
[0054]
As shown in FIG. 4A, the memory cell of this embodiment includes load PMIS transistors 205a and 205b, driver NMIS transistors 206a and 206b, and access NMIS transistors 207a and 207b.
[0055]
As shown in FIG. 4B, the semiconductor device viewed in a plan view includes a semiconductor layer 201 and an isolation insulating film 202 that separates the semiconductor layer 201 into active regions R by surrounding the sides of the semiconductor layer 201. And have. In each active region R, load PMIS transistors 205a and 205b, driver NMIS transistors 206a and 206b, and access NMIS transistors 207a and 207b are provided.
[0056]
The gate electrode 209 of the driver NMIS transistor 206a and the gate electrode 210 of the load PMIS transistor 205a are part of the same wiring layer 211, respectively. The wiring layer 211 extends over a portion of the isolation insulating film 202 located on the side of the source region 212 of the PMIS transistor 205b. In addition, a shared contact 213 is provided from above the region of the wiring layer 211 located on the side of the source region 212 to above the source region 212. A portion of shared contact 213 located above source region 212 functions as a source electrode contact. From the above layout, the shared contact 213 is a common contact between the gate electrode 209 and the gate electrode 210 which are part of the wiring layer 211 and the source region 212 of the PMIS transistor 205b. A drain contact 220 is formed on the drain region 222 of the PMIS transistor 205a. A gate electrode 210 of the PMIS transistor 205a is formed on one side of the drain region 222, and a gate electrode 219 of another PMIS transistor is formed on the other side.
[0057]
On the other hand, the gate electrode 214 of the load PMIS transistor 205b and the gate electrode 215 of the driver NMIS transistor 206b are part of the same wiring layer 216, respectively. The wiring layer 216 extends over a portion of the isolation insulating film 202 located on the side of the source region 217 of the PMIS transistor 205a. A shared contact 218 is provided from the upper side of the wiring layer 216 located on the side of the source region 217 to the upper side of the source region 217. A portion of shared contact 218 located above source region 217 functions as a source electrode contact. From the above layout, the shared contact 218 electrically connects the gate electrode 214 of the PMIS transistor 205b and the gate electrode 215 of the NMIS transistor 206b, which are part of the wiring layer 216, and the source region 217 of the PMIS transistor 205a. .
[0058]
Next, the configuration around the shared contact 218 will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the structure taken along the line (IV)-(IV) shown in FIG.
[0059]
As shown in FIG. 5, the wiring layer 216 is provided on the isolation insulating film 202 and extends to the side of the source region 217. The wiring layer 216 is provided so that its side surface is along the outline of the isolation insulating film 202. The side of the wiring layer 216 is surrounded by a sidewall spacer 208, and is classified into two, sidewall spacers 208a and 208b, depending on the region provided. The sidewall spacer 208 a is a portion provided on the side of the wiring layer 216 that faces the semiconductor layer 201, and the sidewall spacer 208 b faces the isolation insulating film 202 of the side of the wiring layer 216. The part provided on the side. A shared contact 218 formed by embedding a barrier film and a metal film in an opening provided in the liner film 223 and the interlayer insulating film 224 formed on the substrate is provided. The shared contact 218 is provided in contact with the wiring layer 216, the sidewall spacer 208a, and the source region 217. In addition, a drain contact 220 formed by embedding a barrier film and a metal film in an opening provided in the liner film 223 and the interlayer insulating film 224 formed on the substrate is provided so as to be in contact with the drain region 222. .
[0060]
In the structure shown in FIG. 5, the end of the sidewall spacer 208a on the side in contact with the wiring layer 216 is located on the boundary between the isolation insulating film 202 and the semiconductor layer 101. The effect can be obtained if the lower surface of the sidewall spacer 208a is positioned on the boundary.
[0061]
In this embodiment, focusing on the fact that the isolation insulating film 202 is formed higher than the semiconductor layer 201, the wiring layer 216 is formed on the isolation insulating film 202, and the sidewall is formed on the semiconductor layer 201. The spacer 208a was formed. Accordingly, the height of the sidewall spacer 208a can be increased by a level difference between the semiconductor layer 201 and the isolation insulating film 202, as compared with the conventional case. For example, in the case where the isolation insulating film 202 is formed higher than the semiconductor layer 201 by 20 nm, the sidewall spacer 208a can be formed higher by 20 nm.
[0062]
When the height of the sidewall spacer 208a is increased, for the reason described in the first embodiment, when the opening for the shared contact 218 is formed, the reduction in film thickness near the lower surface of the sidewall spacer 208a is suppressed. Can do.
[0063]
That is, by increasing the margin for the film thickness reduction of the sidewall spacer 208a, it is possible to suppress the exposure of the shallow p-type impurity region 221 located therebelow due to the decrease in the width of the sidewall spacer 208a. Therefore, it is possible to suppress a decrease in yield due to the occurrence of junction leakage current.
[0064]
In the present embodiment, the difference between the height of the upper surface of the isolation insulating film 202 and the height of the upper surface of the semiconductor layer 201 is set to 20 nm. However, if this difference is 10 nm or more, the film thickness reduction of the sidewall spacer 208a can be effectively suppressed. Further, if this step is 30 nm or less, a residue is hardly generated in the dry etching process for forming the wiring layer, so that a decrease in yield can be suppressed.
[0065]
In the present embodiment, for example, a laminated film made of an oxide film and a nitride film may be used as the sidewall spacer 208, a silicon nitride film may be used as the liner film 223, and a silicon oxide film as the interlayer insulating film 224. May be used.
[0066]
(Third embodiment)
In the third embodiment, a method of manufacturing a semiconductor device having an SRAM memory cell region as described in the second embodiment and further having a logic circuit region will be described with reference to FIGS. This will be described with reference to FIGS. 7 (a) to (c) and FIGS. 8 (a) to (c). FIGS. 6A to 6D, FIGS. 7A to 7C, and FIGS. 8A to 8C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the third embodiment. Note that the cross section of the SRAM memory cell region in these drawings corresponds to the cross section taken along line (IV)-(IV) in FIG.
[0067]
First, in the step shown in FIG. 6A, a 10 nm-thickness silicon oxide film 302 and a 100 nm-thickness silicon nitride film 303 are deposited on an n-type silicon substrate 301.
[0068]
Next, in the step shown in FIG. 6B, a photoresist layer 304 is formed so as to cover the active region R of the silicon substrate 301. Subsequently, by performing anisotropic dry etching using the photoresist layer 304 as a mask, a groove having a depth of 300 nm is formed by removing part of the silicon substrate 301 through the silicon nitride film 303 and the silicon oxide film 302. 305 is formed.
[0069]
Next, in the step shown in FIG. 6C, the photoresist layer 304 is removed. Subsequently, a 600 nm-thickness silicon oxide film (not shown) is deposited on the silicon substrate 301 to fill the trench 305. Thereafter, the silicon oxide film is polished and planarized by CMP to remove the silicon oxide film on the silicon nitride film 303 and form isolation insulating films 306a and 306b filling the trench 305. . Here, the isolation insulating film 306a refers to that located in the SRAM cell region, and the isolation insulating film 306b refers to that located in the logic region.
[0070]
Next, in the step shown in FIG. 6D, a photoresist 307 that covers the SRAM cell region and exposes the logic region is formed. Subsequently, wet etching is performed using the photoresist 307 as a mask to remove the isolation insulating film 306b in the logic region by a depth of 10 nm. Thus, the upper surface of the isolation insulating film 306a in the SRAM cell region is higher than the upper surface of the isolation insulating film 306b in the logic region.
[0071]
When the pattern rate of the active region in the SRAM cell region is lower than the pattern rate in the logic region, the SRAM memory cell region is obtained by performing uniform etching in the SRAM cell region and the logic region in the step shown in FIG. The height of the upper surface of the isolation insulating film 306a is lower than the height of the isolation insulating film 306b in the logic region. Here, the pattern rate refers to the degree of pattern density. However, in this embodiment, in the step shown in FIG. 6D, the step between the isolation insulating film 306a and the silicon substrate 301 in the SRAM cell region is performed in order to perform the etching with the SRAM memory cell region masked. The insulating film 306a for isolation in the logic region can be etched while ensuring the above.
[0072]
Next, in the step shown in FIG. 7A, the photoresist 307, the silicon nitride film 303, and the silicon oxide film 302 are sequentially removed.
[0073]
Next, in the step shown in FIG. 7B, a gate insulating film 308 is formed to cover the active region R of the silicon substrate 301, and a polycrystalline silicon film (not shown) having a thickness of 150 nm is formed on the gate insulating film 308. Z). Thereafter, a photoresist (not shown) is formed on the polycrystalline silicon film, and dry etching of the polycrystalline silicon film is performed using the photoresist as a mask, thereby forming a wiring layer 309 that partially becomes a gate electrode. To do. In the SRAM cell region, the wiring layer 309 is provided in the same pattern as the wiring layer 211 and the like shown in FIG.
[0074]
Thereafter, the photoresist is removed, and boron is ion-implanted with an implantation energy of 3 KeV using the wiring layer 309 as a mask, thereby forming a p-type impurity region 310 having a depth of 20 nm serving as an SD extension region.
[0075]
Next, in the step shown in FIG. 7C, a base oxide film and a silicon nitride film (not shown) covering the wiring layer 309 are deposited on the substrate, and anisotropic dry etching is performed to thereby form the wiring layer. Sidewall spacers 311 are formed on the side surfaces of 309. Note that the sidewall spacer 311 in the SRAM cell region includes two sidewall spacers 311a and 311b. The sidewall spacer 311a is provided on the side of the wiring layer 309 provided on the isolation insulating film 306a in the SRAM cell region, and on the side of the wiring layer 309 that faces the silicon substrate 301. The part provided in The sidewall spacer 311b is provided on the side of the wiring layer 309 provided on the isolation insulating film 306a in the SRAM cell region, and on the side of the wiring layer 309 facing the isolation insulating film 306a. The part provided in Thereafter, boron is ion-implanted with an implantation energy of 40 KeV using the wiring layer 309 and the sidewall spacer 311 as a mask, thereby forming a deep impurity region 312 having a depth of 45 nm, which becomes a source region and a drain region.
[0076]
Next, in the step shown in FIG. 8A, on the substrate, a 5 nm-thick base insulating film (not shown) made of a silicon oxide film, a 20 nm-thick liner film 313 made of a silicon nitride film, A 600 nm thick interlayer insulating film 314 made of a silicon oxide film is deposited. Thereafter, the surface of the interlayer insulating film 314 is planarized by CMP.
[0077]
Next, a photoresist (not shown) is formed on the interlayer insulating film 314 in the step shown in FIG. After that, anisotropic dry etching is performed using a photoresist as a mask, thereby forming contact openings 315 and openings 316 that penetrate the interlayer insulating film 314 and reach the liner film 313. Thereafter, dry etching is performed to remove the photoresist, the contact opening 315 and the liner film 313 exposed on the lower surface of the opening 316 and the base insulating film.
[0078]
At this time, part of the sidewall spacer 311a exposed in the opening 316 is also removed, and when the film thickness is most severe, the height of the sidewall spacer 311a is 50 nm.
[0079]
Next, in the step shown in FIG. 8C, a contact 317 and a shared contact 318 are formed by embedding a barrier film made of titanium and titanium nitride and a metal film made of tungsten in the contact opening 315 and the opening 316. To do. Thereafter, a metal wiring or the like is formed using a known process, whereby a semiconductor device having a shared contact is completed.
[0080]
In the present embodiment, the height of the sidewall spacer 311a can be increased by forming the wiring layer 309 on the isolation insulating film 306a. Therefore, for the same reason as in the first embodiment, when the opening 316 is formed, a decrease in the width near the lower surface of the sidewall spacer 311a can be suppressed.
[0081]
Furthermore, in this embodiment, the height of the isolation insulating film 306a in the SRAM cell region can be formed higher than that of the isolation insulating film 306b in the logic region. In other words, the height of the isolation insulating film 306a in the region where the shared contact 318 is provided can be controlled to be high independently of other regions.
[0082]
In this embodiment, wet etching is performed in the step shown in FIG. 6D using the photoresist 307 formed so as to cover the SRAM cell region as a mask. However, when the distance between the region where the shared contact is formed and the gate electrode in the logic region is set to 400 nm or more, the isolation insulating film 306a is covered so as to cover the portion where the shared contact is formed. After the photoresist is formed, wet etching or dry etching may be performed.
[0083]
(Other embodiments)
The present invention can also be applied to a semiconductor device having a salicide structure and a method for manufacturing the same. Specifically, in the first embodiment, after the step shown in FIG. 2D, a metal is deposited on the substrate and annealed, so that the wiring layer 105 and the p-type impurity diffusion layer 109 are formed. A silicide layer is formed on (127). In this case, in the step shown in FIG. 2F, it is possible to prevent a part of the sidewall from being removed and exposing a region of the active region R that is not covered by the silicide layer. Similarly, in the third embodiment, after the step shown in FIG. 7C, a metal is deposited on the upper portion of the wiring layer 309 having the gate electrode and the upper portion of the impurity region 312 and annealing is performed. A silicide layer may be formed by this, and in this case, the same effect can be obtained.
[0084]
【The invention's effect】
As described above, in the present invention, the gate electrode connected to the shared contact is formed on the isolation insulating film formed so as to be higher than the surface of the semiconductor substrate, whereby the sidewall in the opening of the shared contact is formed. The spacer can be formed relatively thick. As a result, the margin for reducing the sidewall spacer film in the shared contact opening process can be expanded, and the yield reduction due to the generation of junction leakage current in the shared contact formation region can be prevented.
[Brief description of the drawings]
FIG. 1A is a plan view showing a structure of a semiconductor device according to a first embodiment, and FIG. 1B is a cross-sectional view taken along line (I)-(I) shown in FIG. is there.
FIGS. 2A to 2G are cross-sectional views taken along the line (I)-(I) showing the manufacturing process of the semiconductor device according to the first embodiment; FIGS.
FIG. 3 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment.
4A is a circuit diagram showing a memory cell of a semiconductor device according to a second embodiment, and FIG. 4B is a plan view showing a structure of a semiconductor device (SRAM) according to the second embodiment. is there.
FIG. 5 is a cross-sectional view showing a structure taken along line (IV)-(IV) shown in FIG.
6A to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment.
7A to 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment.
8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment.
9A is a plan view showing the structure of a conventional SRAM provided with a shared contact, and FIG. 9B is a cross-sectional view taken along line (IX)-(IX) shown in FIG. 9A; It is sectional drawing.
[Explanation of symbols]
101 Semiconductor layer
102 Insulating film for separation
103 Gate insulation film
104 Polycrystalline silicon film
105 Wiring layer
106 p-type impurity region
107 Silicon nitride film
108 Sidewall spacer
108a Side wall spacer
108b Side wall spacer
109 Impurity region
110 Liner membrane
111 Interlayer insulation film
112 opening
113 Shared contacts
120 elements
121 elements
122 Source region
123 Drain region
124 Gate electrode
125 source contact
126 Drain contact
127 Source region
128 Drain region
129 Gate electrode
130 Drain contact
131a Side wall spacer
131b Side wall spacer
132 Wiring layer
201 Semiconductor layer
202 Insulating film for separation
205a PMIS transistor
205b PMIS transistor
206a NMIS transistor
206b NMIS transistor
207a NMIS transistor
207b NMIS transistor
208 Sidewall spacer
208a Side wall spacer
208b Side wall spacer
209 Gate electrode
210 Gate electrode
211 Wiring layer
212 Source area
213 Shared contact
214 Gate electrode
215 Gate electrode
216 Wiring layer
217 source region
218 Shared contact
219 Gate electrode
220 Drain contact
221 p-type impurity region
222 Drain region
223 liner film
224 interlayer insulation film
301 Silicon substrate
302 Silicon oxide film
303 Silicon nitride film
304 photoresist layer
305 groove
306a Separation insulating film
306b Separation insulating film
307 photoresist
308 Gate insulation film
309 Wiring layer
310 Impurity region
311 Sidewall spacer
311a Sidewall spacer
311b Side wall spacer
312 Impurity region
313 Liner membrane
314 Interlayer insulating film
315 Contact opening
316 opening
317 contact
318 Shared contact

Claims (13)

A semiconductor layer having a plurality of active regions including a first active region and a second active region;
An isolation insulating film that surrounds the sides of the plurality of active regions and at least a part of which is provided higher than the semiconductor layer;
A first element provided in the first active region and having a first electrode;
A first wiring layer, part of which is the first electrode and the other part of which extends over the part of the insulating film for isolation;
A portion provided on the side of the first wiring layer and located on the side of the other part of the first wiring layer is located at a boundary between the isolation insulating film and the second active region. A first sidewall spacer in contact;
A second element having a first impurity diffusion layer provided in the second active region and formed in a self-aligned manner using the first sidewall spacer as a mask;
A second impurity diffusion layer provided in a region interposed between the first impurity diffusion layer and the isolation insulating film in the second active region;
An interlayer insulating film provided above the semiconductor layer and the isolation insulating film;
A first shared contact provided over a part of the first impurity diffusion layer, a part of the first sidewall spacer, and a part of the first wiring layer; A semiconductor device provided. The semiconductor device according to claim 1,
In the boundary, the height of the upper surface of the semiconductor layer in the second active region is lower by 10 nm or more and 30 nm or less than the height of the upper surface of the isolation insulating film. The semiconductor device according to claim 1 or 2,
A semiconductor device, wherein an end of the first sidewall spacer in contact with the first wiring layer is provided on the boundary. The semiconductor device according to any one of claims 1 to 3,
The first element is a first MIS transistor for loading,
The second element is a second MIS transistor load having a gate electrode on the second active region,
A first driver MIS transistor provided in one of the plurality of active regions and having a gate electrode which is a part of the first wiring layer;
A second driver MIS transistor provided in one of the plurality of active regions and having a gate electrode;
And the gate electrode of the second MIS transistor for load, has as part of the above gate electrode of the second MIS transistor driver, another part on the portion of the insulating film for isolation A second wiring layer extending to
The second wiring layer is provided on a side of the second wiring layer, and a portion of the second wiring layer positioned on the side of the other part is in contact with a boundary between the isolation insulating film and the semiconductor layer. Side wall spacers,
A semiconductor device further comprising: a second shared contact provided above a part of the first active region, a part of the second sidewall spacer, and the second extension. . A semiconductor layer;
An isolation insulating film that surrounds the active region made of the semiconductor layer and at least a part of the upper surface of which is higher than the upper surface of the semiconductor layer;
A wiring layer formed on the part of the isolation insulating film;
A sidewall spacer provided on a side of the wiring layer, at least a part of the bottom surface of which is in contact with a boundary between the isolation insulating film and the active region;
An impurity diffusion layer formed in the active region;
An interlayer insulating film provided above the semiconductor layer;
An opening formed in the interlayer insulating film and reaching the impurity diffusion layer;
A contact formed in the opening,
The opening is formed over a part of each of the wiring layer, the sidewall spacer, and the impurity diffusion layer,
The semiconductor device, wherein the wiring layer and the impurity diffusion layer are electrically connected by the contact. Forming an isolation insulating film that surrounds the sides of the first active region and the second active region, which are part of the semiconductor layer, and at least a part of the upper surface of which is higher than the upper surface of the semiconductor layer ; (A) and
Partially extends over said first active region, a step (b) other part of which forms a first wiring layer extending over said portion of said isolation insulating film,
(C) performing ion implantation into the second active region using the first wiring layer as a mask;
On the side surface of the first wiring layer, a first sidewall spacer is in contact with the boundary between the isolation insulating film and the semiconductor layer on the other part of the side of the first wiring layer. (D) forming into,
(E) performing ion implantation into the second active region using the first wiring layer and the first sidewall spacer as a mask;
Forming an interlayer insulating film covering the semiconductor layer and the isolation insulating film (f);
A portion of the interlayer insulating film that extends above a part of the second active region, a part of the first sidewall spacer, and the other part of the first wiring layer is removed. A step (g) of forming the first opening,
And a step (h) of forming a first shared contact by filling the first opening with a conductor. In the manufacturing method of the semiconductor device according to claim 6,
In the step (g), a method for manufacturing a semiconductor device, wherein dry etching of the interlayer insulating film is selectively performed on the first sidewall spacer to form the first opening. In the manufacturing method of the semiconductor device according to claim 6 or 7,
In the step (a), the upper surface of the isolation insulating film is formed higher by 10 nm or more and 30 nm or less than the upper surface of the semiconductor layer. In the manufacturing method of the semiconductor device according to any one of claims 6 to 8,
In the step (g), a part of the interlayer insulating film is removed to form a gate electrode contact opening and a source / drain opening,
In the step (h), a method of manufacturing a semiconductor device, wherein the opening for the gate electrode and the opening for the source / drain are filled with a conductor. In the manufacturing method of the semiconductor device as described in any one of Claims 6-9,
In the step (a), the isolation insulating film surrounds the sides of the third active region and the fourth active region, which are part of the semiconductor layer,
In the step (b), a gate electrode is formed on the third active region as a part of the first wiring layer,
Further, a part of the gate electrode is located above the second active region and a part of the gate electrode located above the fourth active region, and the other part is the part of the isolation insulating film . Forming a second wiring layer extending upward ;
In the step (c), ion implantation is performed on the first active region using the second wiring layer as a mask,
In the step (d), a second sidewall spacer is disposed on the side surface of the second wiring layer, and the isolation insulating film and the semiconductor are disposed on the other part of the second wiring layer. Formed to touch the boundary with the layer,
In the step (e), ions are implanted into the first active region using the second wiring layer and the second sidewall spacer as a mask,
In the step (g), in the interlayer insulating film, above the first active region, a part of the second sidewall spacer, and the other part of the second wiring layer. Forming a second opening by removing the spanning region;
In the step (h), the second shared contact is formed by filling the second opening. In the manufacturing method of the semiconductor device according to claim 10,
Before the step (a), the method further includes a step (i) of forming a stopper film covering the semiconductor layer.
In the step (a), after removing a part of the stopper film and a part of the semiconductor layer to form a groove and then filling the groove with an insulator, at least the first shared contact and the first A method of manufacturing a semiconductor device, comprising: forming a photoresist covering the shared contact, and etching the insulating film using the photoresist as a mask to form the isolation insulating film. In the manufacturing method of the semiconductor device according to claim 11,
The semiconductor layer has an SRAM cell region in which the first shared contact and the second shared contact are provided, and a peripheral region which is a region excluding the SRAM cell region,
In the step (a), a method of manufacturing a semiconductor device, wherein a part of the insulating film in the peripheral region is removed by performing the etching. A step (a) of forming an isolation insulating film surrounding an active region made of a part of a semiconductor layer and having an upper surface higher than the upper surface of the active region;
Forming a wiring layer on the isolation insulating film (b);
Forming a side wall spacer on the side surface of the wiring layer, wherein at least a part of the bottom surface is in contact with a boundary between the isolation insulating film and the active region; and
(D) forming an impurity diffusion layer by ion-implanting the active region using the sidewall spacer as a mask;
A step (e) of forming an interlayer insulating film above the semiconductor layer after the step (d);
Forming an opening reaching the impurity diffusion layer in the interlayer insulating film (f);
Forming a contact in the opening (g),
In the step (f), the opening over the wiring layer, the sidewall spacer, and a part of the impurity diffusion layer is formed,
In the step (g), the wiring layer and the impurity diffusion layer are electrically connected by the contact.

Images