JP2009016448A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a production yield of a semiconductor apparatus having a structure in which a single contact electrode is formed at a plurality of wiring spots. <P>SOLUTION: The semiconductor apparatus includes a gate electrode GE3 which extends in the first direction A of the main surface of a semiconductor substrate 1 to be formed on the main surface via a gate insulating film GZ1 and has a side wall spacer 5 on the side wall thereof, a source/drain region p1J which reaches a first portion J that is a lower side portion thereof, and a silicon nitride film 6 and a silicon oxide film 7 which are formed in order to cover the main surface of the semiconductor substrate 1 and have different etching speeds. On the first portion J, the gate electrode GE3 is not covered with the side wall spacer 5. The upper surface and side face of the gate electrode GE3 and the source/drain region p1J are covered with a silicide layer 4J, thus electrically connected to each other, and a node contact electrode NC2 is electrically connected to the silicide layer 4J. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device configured by connecting a plurality of field effect transistors.

  Along with the development of an advanced information society, an integrated circuit for operation, a storage element, and a system-on-chip in which a plurality of semiconductor elements formed on a semiconductor substrate are integrated to constitute a functional circuit ( There is a demand for higher performance in semiconductor devices such as SoC (System on Chip).

  Conventionally, high performance of semiconductor devices has been achieved by realizing high integration by miniaturization of semiconductor elements such as MIS (Metal Insulator Semiconductor) type field effect transistors integrated on a semiconductor substrate. In particular, as the circuit configuration becomes more complex, the wiring for connecting individual elements has become more or less complicated, and the development of microfabrication technology and multilayer wiring technology has been realized. From such a background, simplification of wiring is desired for higher integration of semiconductor devices aimed at higher performance in the future.

  By the way, SRAM (Static Random Access Memory), which is a semiconductor device as a static memory element, has high utility value as a main memory device in various arithmetic devices because of its high speed of writing and reading. However, since 6 elements are required per cell for storing 1-bit information, it is not suitable for integration. At present, the place where the storage capacity requirement is relatively low, or the writing / reading speed is the top priority. Limited to certain applications. For such a semiconductor device, there is a strong demand for simplification of wiring that can achieve high integration without changing the essential circuit configuration.

  Therefore, the same potential in the circuit configuration, and the connection between the adjacent node and the wiring in the arrangement on the semiconductor substrate is shared by the same contact electrode to simplify the wiring, so-called shared contact. Techniques have been devised and disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2007-27348 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2004-165317 (Patent Document 2).

A technique in which the above-described shared contact technique is applied to an SRAM is disclosed in JP-A-2006-339480 (Patent Document 3) and the like.
JP 2007-27348 A JP 2004-165317 A JP 2006-339480 A

  However, in the semiconductor device having the shared contact electrode as described above, the present inventors have found the following problems.

  The inventors of the present invention analyzed the cause of a decrease in the yield of SoC having shared contact electrodes in the production process of the SRAM using a test element (TEG: Test Element Group) formed by the same process. As a result, it has been clarified that the error rate contributing to the defect of the shared contact electrode portion is high, which is a factor in the decrease in the yield of the semiconductor device. Furthermore, when the present inventors analyzed the defective shared contact electrode part in detail, the following knowledge was acquired. Hereinafter, a description will be given with reference to FIGS.

  The present inventors have examined an SRAM having a structure disclosed in Patent Document 3. FIG. 14 is a plan view of the main part (for one cell) in the SRAM. For the sake of convenience, the wiring made of the conductor film is indicated by hatching, and the contact electrode portion is indicated by a cross diagonal line.

  Here, the configuration will be briefly described in comparison with an actual SRAM element for one cell. An SRAM circuit which is a static memory element includes field effect transistors Qn1 to Qn4, Qp1 and Qp2 formed in a p-type well pw and an n-type well nw on a semiconductor substrate 1. An n-channel field effect transistor (hereinafter simply referred to as an n-type transistor) formed in left and right p-type wells pw sandwiching the n-type well nw and having gate electrodes GE1 and GE4 connected to the word contact electrode WC1 Qn1 and Qn4 are equivalent in consideration of objectivity in circuit configuration. These function as access transistors (or driver transistors) that control reading and writing of data.

  Apart from the above, n-type transistors Qn2, Qn3 formed in the p-type well pw and p-channel field effect transistors (hereinafter simply referred to as p-type transistors) Qp1, Qp2 formed in the n-type well nw are statically connected. A so-called flip-flop circuit having a function of holding data statically is configured. The source / drain regions n1, n2, p1, and p2 or the gate electrodes GE2 and GE3 each have a desired contact electrode (for example, a contact electrode HC1 with a high potential line) to constitute an SRAM circuit.

  Here, the gate electrode GE2 of the p-type transistor Qp2 formed in the n-type well nw has the same potential as the source / drain region p2 of the other p-type transistor Qp1 in terms of circuit configuration. In the semiconductor device of this structure studied by the present inventors, the gate / electrode region GE2 is extended in the first direction A and further extended in the second direction B intersecting A. These are extended to the vicinity of each other by the shared contact electrode SC1. A similar shared contact electrode SC2 is also connected between the gate electrode GE3 of the p-type transistor Qp1 and the source / drain region p1 of the p-type transistor Qp2, which is equivalent to the above configuration and circuit configuration. As a result, the contact electrode / wiring structure can be simplified, which is advantageous for integration. On the other hand, the present inventors have found a problem that the connection failure of the shared contact electrodes SC1 and SC2 causes a decrease in the manufacturing yield of the semiconductor device.

  FIG. 15 is a cross-sectional view of the main part when the cross section taken along the line aa in FIG. 14 is viewed in the direction of the arrow, which is shown in order to explain the configuration of the shared contact electrodes SC1 and SC2 in detail.

  The n-type well nw formed on the semiconductor substrate 1 is insulated and separated by a groove-shaped separation portion 2 made of an insulating film such as a silicon oxide film. A plurality of gate electrodes GE2, GE3, GEx are formed on the main surface of the semiconductor substrate 1 so as to extend in the first direction A and at a distance in the second direction. Each includes a gate insulating film GZ1 made of, for example, a silicon oxide film or the like between the main surface of the semiconductor substrate 1. In addition, a source / drain region p1 made of a p-type semiconductor region is formed in the lateral lower portion of the gate electrodes GE2, GE3, and GEx. Then, contact electrodes HC1 and SC2 that are connected to the respective electrodes are formed. Here, in order to form a normal ohmic connection with the contact electrodes such as the contact electrodes HC1 and SC2, generally, the surface of the source / drain region p1 and the gate electrodes GE2 and GE3 constituting the transistor is A silicide layer 4 which is a compound of silicon and metal atoms is formed.

  Further, in order to insulate and separate the silicide layer 4 between the source / drain region p1 and the gate electrodes GE2 to GEx, sidewall spacers 5 made of, for example, a silicon oxide film are provided on the side walls of the gate electrodes GE2 to GEx. It has.

  According to the technique studied by the present inventors, the contact electrodes HC1, SC2, etc. are so-called SACs (two types of insulating films (here, a silicon nitride film 6 and a silicon oxide film 7) having different etching rates). A groove for a contact electrode is formed by Self Align Contact technology. At this time, the present inventors have found the following problems in forming the shared contact electrode SC2.

  That is, in order to reduce the memory cell, it is desirable to design the planar size of the contact electrode as small as possible, but it is difficult to reduce the planar size of the shared contact electrode SC2. This is because, in the SAC process, when the size of the shared contact electrode SC2 is small, the contact area between the shared contact electrode SC2 and the silicide layer 4J formed in the source / drain region p1J is small due to the influence of the sidewall insulating film 5 and the alignment error. This is because resistance is likely to increase and contact failure is likely to occur. In fact, the present inventors have confirmed by the above-described TEG test that phenomena such as increased resistance and poor contact are likely to occur in the shared contact electrode SC1 and the like. As a result, these cause the manufacturing yield of the semiconductor device to be hindered. As described above, in the shared contact technology that the present inventors have examined introduction for the purpose of realizing high integration of the semiconductor memory element by simplifying the wiring structure, the reduction of the planar size and the improvement of the manufacturing yield are achieved. The problem of having a trade-off relationship was found.

  Therefore, an object of the present invention is to provide a technique for improving the manufacturing yield in a semiconductor device having a structure in which a single contact electrode is formed at a plurality of different wiring locations.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A first conductor film extending in a first direction of a main surface of the semiconductor substrate, formed on the main surface of the semiconductor substrate via a first insulating film, and having a second insulating film on a side wall; A semiconductor device having a semiconductor region that reaches a first portion that is a lower side of a conductor film, and a third insulating film and a fourth insulating film that are sequentially formed so as to cover the main surface of the semiconductor substrate and that have different etching rates. In the first portion, the first conductor film is not covered with the second insulating film, and the upper surface, the side surface, and the semiconductor region of the first conductor film are covered with the second conductor film to be electrically connected. In addition, the conductive portion of the third conductor film is electrically connected to the second conductor film.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, in a semiconductor device having a structure in which a single contact electrode is formed at a plurality of different wiring locations, the manufacturing yield can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, for the purpose of simplifying the wiring, a technique for improving the manufacturing yield of an SRAM as a semiconductor device having a structure in which a single contact electrode is formed at a plurality of different wiring locations will be exemplified.

  FIG. 1 is a plan view of one cell that holds 1-bit information in the SRAM exemplified in the first embodiment. Using this, the basic circuit configuration of the SRAM cell exemplified in the first embodiment will be described. In the plan view, for the sake of convenience, the wiring made of the conductive film is indicated by diagonal lines, and the contact electrode portion is indicated by a cross diagonal line.

  Generally, an SRAM element cell uses two circuit configurations that output a logical negation with respect to a digital input, and connects input and output nodes to each other, thereby making input information static (static). It is composed of a so-called flip-flop circuit having a function of holding. That is, field effect transistors are used in a complementary manner, similar to the logic configuration of integrated circuits constituting many current semiconductor devices. Therefore, on the semiconductor substrate 1, bipolar transistors such as an n-channel field effect transistor (hereinafter simply referred to as an n-type transistor) and a p-channel field effect transistor (hereinafter simply referred to as a p-type transistor) are provided in one cell. Need to form.

  The n-type transistor is formed in the p-type well, and the p-type transistor is formed in the n-type well. Here, the well is a diffusion region which is formed on the main surface of the semiconductor substrate 1 and formed for making various semiconductor elements including a field effect transistor. In addition, a semiconductor region or portion where the majority carrier is an electron is referred to as n-type, and a semiconductor region or portion where the same carrier is a hole is referred to as p-type. In the first embodiment, for the semiconductor substrate 1, for example, a p-type semiconductor material whose base material is single crystal silicon is used.

  As shown in FIG. 1, in the SRAM cell exemplified in the first embodiment, it is necessary to use n-channel / p-channel bipolar transistors in a complementary manner, so that the main surface of the semiconductor substrate 1 has a p-type well. The pw and the n-type well nw are alternately formed along the first direction A. A plurality of field effect transistors Qn1 to Qn4, Qp1 (first field effect transistor) and Qp2 (second field effect transistor) are formed in each well pw, nw.

  The basic configuration of the field effect transistors Qn1 to Qn4, Qp1, and Qp2 exemplified in the first embodiment will be described in detail below.

  First, the first conductor film extending in the first direction A of the semiconductor substrate 1 is used as the gate electrodes GE1 to GE4. As the first conductor film as the gate electrodes GE1 to GE4, for example, a conductor film mainly composed of polycrystalline silicon is used. As will be described in detail later using a cross-sectional view, a gate insulating film (first insulating film) GZ1 is formed between the gate electrodes GE1 to GE4 and the semiconductor substrate 1.

  Next, the semiconductor regions extending in the second direction B, which is the direction intersecting the first direction A, are defined as source / drain regions n1, n2, p1, and p2. In particular, the n-type transistors Qn1 to Qn4 formed in the p-type well pw have source / drain regions n1 and n2 by n-type semiconductor regions, and the p-type transistors Qp1 and Qp2 formed in the n-type well nw are p-type. It has source / drain regions p1 and p2 by a semiconductor region. A field effect transistor is configured by using the gate electrodes GE1 to GE4 and the source / drain regions n1, n2, p1, and p2 as three terminals.

  Hereinafter, functions of the individual transistors Qn1 to Qn4, Qp1, and Qp2 constituting the SRAM will be described in detail.

  Here, the configuration in the p-type well pw formed on both sides of the n-type well nw is equivalent in the left and right p-type wells pw in consideration of the objectivity in the circuit configuration. First, the n-type transistors Qn1 to Qn4 formed in the p-type well pw will be described. Among these, there are n-type transistors Qn1 and Qn4 having the gate electrode GE1 or GE4 electrically connected to the word contact electrode WC1 connected to the word line. These function as an access transistor or a driver transistor that controls reading and writing of data to and from a data holding area in the SRAM. Each source / drain region n1, n2 is electrically connected to a bit contact electrode BC1 and a node contact electrode NC1 connected to the bit line.

  The other n-type transistor Qn2 or Qn3 formed in the p-type well pw is electrically connected to the n-type transistor Qn1 or Qn4 by sharing the source / drain region n1 or n2, respectively. The n-type transistor Qn2 or Qn3 is electrically connected to a low potential contact electrode LC1 connected to a constant voltage on the low potential (mainly ground) side of the entire circuit in one source / drain region n1 or n2. Yes.

  Further, the n-type transistors Qn2 and Qn3 having the low potential contact electrode LC1 and the gate electrodes GE2 and GE3 extending in the first direction A are shared so that the p-type transistors Qp1 and Qp2 having opposite polarities are used. Is formed in the n-type semiconductor region. That is, these two sets of field effect transistors having different polarities (Qn2 and Qp2, and Qn3 and Qp1) are connected by sharing a gate electrode (GE2 and GE3, respectively), thereby making a logical negation with respect to the gate input. Two complementary circuit configurations for output are realized in one cell of the SRAM element on the semiconductor substrate 1. One of the source / drain regions p2, p1 of the p-type transistors Qp1, Qp2 is electrically connected to a high potential contact electrode HC1 connected to a constant voltage on the high potential (mainly power supply voltage) side applied to the entire circuit. .

  In order to hold these data, the two sets of complementary circuit configurations are obtained by connecting the gate electrode GE2 (or GE3) serving as an input of one complementary circuit configuration and the node serving as an output. Input data can be held statically.

  Here, as a qualitative interpretation of the circuit function of the SRAM, the p-type transistors Qp1 and Qp2 connected to the high potential contact electrode HC1 can be viewed as load elements. Then, a node where a voltage has dropped from the high potential contact electrode HC1 via the p-type transistors Qp1 and Qp2 which are loads becomes an output node. That is, when viewed on the basis of a complementary circuit configuration composed of the n-type transistor Qn3 and the p-type transistor Qp1, the common gate electrode GE3 (input node) and the p-type transistor Qp2 (load) have a high potential contact electrode HC1 and By electrically connecting the source / drain region p1 (output node) on the unconnected side, a circuit configuration for statically holding data can be realized.

  At this time, as described above, the arrangement of the SRAM elements exemplified in the first embodiment on the semiconductor substrate 1 extends the gate electrodes GE1 to GE4 in the first direction A, and the source / drain regions n1, n2, p1 and p2 are characterized by extending in a second direction B intersecting the first direction A. Therefore, it is structurally easy to provide the first portion J to be connected by bringing the gate electrode GE3 to be electrically connected and the p-type source / drain region p1 close to each other.

  Here, according to the technique examined by the present inventors (see FIGS. 14 and 15), the semiconductor region which is the p-type source / drain region p1 extending in the second direction B is formed on the side of the gate electrode GE3. It is formed so as to reach the bottom, and is connected by the shared contact electrode SC2. However, according to further studies by the present inventors, in the shared contact electrode SC2 straddling the gate electrode GE3 having the sidewall insulating film and the source / drain region p1, resistance is likely to increase and contact failure is liable to occur, resulting in a decrease in yield. I know it will invite.

  Therefore, in the SRAM cell having the structure exemplified in the first embodiment, a configuration in which the gate electrode GE3 and the source / drain region p1 are electrically connected in the first portion J will be described in detail below.

  In order to describe the configuration in the vicinity of the first portion J that connects the gate electrode GE3 extending in the first direction A and the source / drain region p1 extending in the second direction B, the aa line in FIG. FIG. 2 is a cross-sectional view of the main part when the cross-sectional view of FIG.

  The n-type well nw formed on the main surface of the semiconductor substrate 1 forms an active region 3 that is insulated and isolated by a trench-type isolation portion 2 made of an insulating film mainly composed of, for example, a silicon oxide film. A desired semiconductor element is formed in the active region 3. In the first embodiment, the isolation portion 2 is a groove type so-called STI (Shallow Trench Isolation), but may have a field oxide film structure.

  In the active region 3, a plurality of gates made of the first conductor film are extended through the gate insulating film GZ <b> 1 made of the first insulating film so as to extend in the first direction A and be separated from each other in the second direction B. Electrodes GE2, GE3, and GEx are formed. For example, a silicon oxide film or the like is used as the first insulating film for forming the gate insulating film GZ1. In addition, as the first conductor film for forming the gate electrodes GE2, GE3, GEx, for example, a polycrystalline silicon film or the like is used. The gate electrode GEx located at the end in the figure constitutes a transistor not involved in the SRAM element 1 cell, and is omitted in FIG.

  Similarly, in the active region 3, a source / drain region p1 which is a p-type semiconductor region is formed on the main surface of the semiconductor substrate 1 on the lower side of the gate electrodes GE2, GE3 and GEx. Here, the source / drain for supplying carriers to the channel of the miniaturized field effect transistor has a lower concentration and a shallower junction than the source / drain region p1 directly connected to the contact electrode in accordance with the design rule. Is done. Therefore, an actual field effect transistor has a so-called extension region p11 which is a p-type semiconductor region having a low concentration and a shallow junction so as to extend from the source / drain region p1 to the vicinity of the channel region.

  The p-type transistors Qp2 and Qpx are formed by the gate electrodes GE2, GE3 and GEx formed through the gate insulating film GZ1 and the source / drain region p1 having the extension region p11 as described above. The p-type transistor Qpx is not involved in the configuration of the SRAM element 1 cell and is omitted in FIG. A silicide layer 4 is formed on the surface of each of the electrodes GE2, GE3, GEx, or the source / drain region p1 to form a normal ohmic contact with a contact electrode (described in detail later). The silicide layer 4 is, for example, a compound layer of a metal such as cobalt (Co), tungsten (W), or nickel (Ni) and silicon (Si), cobalt silicide, tungsten silicide, or nickel silicide. And so on.

  Each gate electrode GE2, GE3, GEx has a sidewall spacer (second insulating film) 5 so as to cover the sidewall. Here, the sidewall spacer 5 exemplified in the first embodiment is made of two layers of silicon oxide films 51 and 52, but there is no qualitative difference only in the formation stage. As a configuration, it is necessary that the gate electrodes GE2, GE3, and GEx are covered with an insulating film, and the effect of the first embodiment is not limited by the two layers of silicon oxide films 51 and 52. Alternatively, it may be formed of only the silicon oxide film 52, may be formed of the silicon oxide film 51 and the silicon nitride film 52, or may be formed of three or more insulating films.

  In the first embodiment, the gate electrode GE3, which is a common input node of the n-type / p-type transistors (Qn3 and Qp1) of one complementary configuration circuit in the SRAM, and the n-type / p-type of the other complementary configuration circuit. The silicide layer 4J described above is used to electrically connect the source / drain region p1J of the p-type transistor, which is the output node of the p-type transistors (Qn2 and Qp2).

  First, in the extending second direction B, the source / drain region p1J reaches the first portion J that is the lower side of the gate electrode GE3. Further, in this first portion J, the side wall spacer 5 is not formed on the side wall of the gate electrode GE3. Then, the upper surface of the gate electrode GE3 formed using silicon as a base material, the side surface of the first portion J where the side wall spacer 5 is not formed, and the silicon is also formed using the base material. Each upper surface of the source / drain region p1J reaching the lower side of the gate electrode GE3 in the first portion J is integrally covered with a silicide layer (second conductor film) 4J. The silicide layer 4J electrically connects the gate electrode GE3 and the source / drain region p1J.

  The semiconductor substrate 1 having the configuration as described above on the main surface includes a silicon nitride film (third insulating film) 6, a silicon oxide film (fourth insulating film) 7, a silicon oxide film 8, and a cap insulating film 9 in this order. Covered by. Here, it is an important structural requirement in the first embodiment that the lower silicon nitride film 6 and the silicon oxide film 7 have different etching rates for a specific etching process. Within the range, the material is not limited. The reason will be described in detail in a later manufacturing method.

  Then, the contact electrodes (conductive portions) HC1 and NC2 of the third conductor film are electrically connected to the silicide layers 4 and 4J so as to penetrate these insulating films 6 to 9. As the third conductor film, for example, a metal film mainly composed of tungsten (W) is used. In particular, in the silicide layer 4 covering the source / drain region p1 of the p-type transistor Qp2, for example, a high potential contact electrode HC1 connected to a power supply voltage or the like is formed to cover from the gate electrode GE3 to the source / drain region p1J. In the silicide layer 4J, for example, a node contact electrode NC2 connected to the node contact electrode NC1 to the n-type transistor Qn1 which is an access transistor is formed.

  Thus, the gate electrode GE3 and the source / drain region p1J are directly electrically connected by the silicide layer 4J. Therefore, if the node contact electrode NC2 can be normally formed in any region of the silicide layer 4J, the gate electrode GE3 and the source / drain region p1J can be made conductive. That is, unlike the method examined by the present inventors, it is not necessary to form the shared contact electrode so as to straddle the upper surface of the gate electrode separated by the sidewall spacer 5 and the source / drain region. As a result, the contact failure that is a problem when using the shared contact electrode is unlikely to occur, and the manufacturing yield of a semiconductor device having a structure in which a single contact electrode is formed at a plurality of different wiring locations can be improved. .

  Next, a manufacturing method of the SRAM element having the structure exemplified in the first embodiment will be described. In particular, the first portion J has a feature in the step of forming a silicide layer 4J that directly connects the gate electrode GE3 and the source / drain region p1J, which will be described in detail. At this time, a generally known method is used as a manufacturing method of the field effect transistor, and a detailed description thereof is omitted here.

  3 to 12 show cross-sectional views in the process of the SRAM illustrating the manufacturing method according to the first embodiment, particularly in the process, which are equivalent to the cross-section taken along the line aa in FIG. This is the place.

  First, as shown in FIG. 3, an isolation portion 2 having an STI structure made of an insulating film mainly composed of, for example, a silicon oxide film is formed on the main surface of a p-type semiconductor substrate 1 by a generally known method. . Thereafter, an n-type well nw is formed by introducing an impurity element into a desired region, for example, by an ion implantation method, and the region isolated and isolated by the isolation portion 2 is defined as an active region 3.

  Thereafter, for example, a silicon oxide film or the like is formed as the subsequent gate insulating film (first insulating film) GZ1 by, eg, thermal oxidation. Thereafter, for example, a polycrystalline silicon film or the like is formed as the subsequent gate electrodes (first conductor films) GE2, GE3, and GEx by, for example, chemical vapor deposition (CVD). Thereafter, the first conductor film and the first conductor film are formed in a shape that extends in the first direction A of the main surface of the semiconductor substrate 1 and is arranged at a distance in a second direction B that intersects the first direction A. By processing the insulating film, the gate electrodes GE2, GE3, GEx, and the gate insulating film GZ1 are patterned. In this case, a series of processes such as depositing a photoresist film (not shown), performing exposure using a desired mask pattern, performing development, and performing anisotropic etching using the remaining photoresist film as an etching mask, for example, is performed. The above-mentioned deposited film is processed by a commonly known photolithography process.

  Thereafter, a p-type impurity is introduced into a portion where the main surface of the semiconductor substrate 1 is exposed by, for example, ion implantation using the gate electrodes GE2, GE3, GEx formed up to the previous step as an ion implantation mask. This becomes a so-called extension region p11 which is a shallow junction for injecting carriers into the channel layer later from the source / drain regions of the field effect transistor. The implantation concentration is determined by electric characteristics required for a field effect transistor to be formed later, and is generally lower than the p-type region as the source / drain region. Thereafter, the above-described structure formed on the main surface of the semiconductor substrate 1 is covered with a silicon oxide film 51 or the like by, for example, a CVD method.

  Next, as shown in FIG. 4, a silicon oxide film 52 or the like having a thickness that completely covers the gate electrodes GE2, GE3, GEx, etc. formed up to the previous step is formed by, for example, a CVD method. Thereafter, the silicon oxide films 52 and 51 covering the main surface of the semiconductor substrate 1 are etched back to form sidewall spacers (second insulating films) 5 having a shape covering the side walls of the gate electrodes GE2, GE3 and GEx. To do.

  In the method for manufacturing the semiconductor device exemplified in the first embodiment, a part of the sidewall spacer 5 is selectively removed. In particular, the side wall spacer 5 that covers the first portion J that is to be electrically connected to the source / drain region of the transistor having the gate electrode GE2 later, which is the side wall of the gate electrode GE3 formed to join the wirings. Is selectively removed. Here, a photoresist film R1 is applied to the main surface of the semiconductor substrate 1, and the photoresist film R1 is processed so as to expose the first portion J by a commonly known photolithography method. Thereafter, as shown in FIG. 5, the exposed portion of the sidewall spacer 5 is selectively removed using the photoresist film R1 as an etching mask.

  Here, in the method of manufacturing the semiconductor device exemplified in the first embodiment, the gate insulating film GZ1 under the gate electrode GE3 of the first portion J from which the sidewall spacer 5 has been removed is partially removed. In FIG. 6, the principal part sectional drawing to which the 1st part J was expanded is shown. In this way, the gate insulating film GZ1 is partially removed so as to recede from the edge of the gate electrode GE3 where the sidewall spacer 5 is removed. This is to prevent the silicide layer to be formed later from interfering with the electrical connection between the gate electrode GE3 and the source / drain region under the side thereof. The specific configuration and effect will be described later. 8 will be described in detail.

  Subsequently, as shown in FIG. 7, the main region of the semiconductor substrate 1 in the exposed region is formed by ion implantation using, for example, the gate electrodes GE2, GE3, GEx and the sidewall spacer 5 covering the sidewalls as an ion implantation mask. A p-type impurity is introduced into the surface. Thereby, the source / drain region p1 is formed, and the basic configuration of the p-type transistors Qp2 and Qpx is completed. The source / drain region p1 is formed to have a deeper junction and a higher impurity concentration than the aforementioned extension region p11 for electrical connection with a contact electrode to be formed later.

  At this time, the upper surfaces of the gate electrodes GE2, GE3, GEx, the side surfaces of the gate electrode GE3, and the source / drain regions p1 are exposed on the main surface of the semiconductor substrate 1. Further, as described above, the gate electrodes GE2, GE3, GEx, and the source / drain regions p1 are formed of a material mainly composed of silicon. Therefore, in this step, the silicide layer 4 is formed in the exposed region. In this method, a metal film such as Co, W, or Ni is deposited on the main surface of the semiconductor substrate 1 by, for example, a sputtering method, and then subjected to heat treatment to be silicided at the interface between silicon and metal, and then desired. After the thickness is reached, the excess metal film is removed and the silicide layer 4 is formed.

  Here, the semiconductor device manufacturing method exemplified in the first embodiment is characterized in that the silicide layer 4J formed in the gate electrode GE3 and the source / drain region p1J reaching the first portion J below the side thereof. It is the composition. FIG. 8 shows an enlarged cross-sectional view of the main part in the vicinity of the first portion J. By the previous process, the gate insulating film GZ1 under the gate electrode GE3 located in the boundary region between the source / drain region p1J and the gate electrode GE3 is partially retracted when viewed from the gate electrode GE3. Thereby, the silicide layer 4J can realize a normal electrical connection without being obstructed by any insulating film in the first portion J. Therefore, the gate electrode GE3 and the source / drain region p1J having the same potential in the SRAM element can be directly electrically connected. As a result, it is not necessary to use a shared contact electrode or the like that is likely to cause a contact failure, and the manufacturing yield of the semiconductor device can be improved.

Here, the amount of removal of the gate insulating film GZ1 in the first portion J for obtaining the above effects normally is based on the following conditions. In other words, the gate insulation is set so that the retraction amount k of the gate insulating film GZ1 viewed from the edge of the gate electrode GE3 before forming the silicide layer 4J is more than half the film thickness t of the silicide layer 4J to be formed later. The film GZ1 is selectively removed. This is because, according to the study by the present inventors, the silicide layer 4J formed by the heat treatment is silicided by substantially the same amount above and below the surface of the original silicon layer (here, the side surface of the gate electrode GE3). It is clear that it will be done. That is, half of the film thickness t of the formed silicide layer 4J is a region formed to penetrate inward from the side surface of the gate electrode GE3, and the retreating amount k of the gate insulating film GZ1 is the film thickness of the silicide layer 4J. If the length is not less than half the length of t, the silicide layer 4J is not prevented from being electrically connected to the gate insulating film GZ1. Further, for the normal electrical conduction of the silicide layer 4J itself, it is desirable that the thickness t of the silicide layer 4J is larger than the thickness t _ox of the gate insulating film GZ1. Needless to say, the silicide layer 4J should be formed in the source / drain region p1J on the semiconductor substrate 1 in order to prevent leakage current.

  The step of removing the gate insulating film GZ1 in the first portion J is performed after the sidewall spacer 5 on the side wall of the gate electrode GE3 is partially removed and before the silicide layers 4 and 4J are formed. For example, it may be in the process of locally removing the sidewall spacer 5 described above, or in the process of cleaning the semiconductor substrate 1 before forming the silicide layers 4 and 4J.

  Thereafter, as shown in FIG. 9, a silicon nitride film (third insulating film) 6, a silicon oxide film (fourth insulating film) 7, a silicon oxide film 8, and a cap insulating film 9 are formed on the main surface of the semiconductor substrate 1. Are sequentially formed by, for example, a CVD method. Here, the laminated structure of the silicon nitride film 6 and the silicon oxide film 7 which are the lower layers is significant when the contact electrodes are formed in a self-aligning manner, and details will be described later. Subsequently, a photoresist film R2 is applied and processed by a photolithography method so that only the portions where contact electrodes are to be formed are exposed.

  Subsequently, as shown in FIG. 10, the cap insulating film 9, the silicon oxide film 8, and the silicon oxide film 7 are selectively removed from the laminated insulating film formed in the previous process using the photoresist film R <b> 2 as an etching mask. By doing so, holes H1 and H2, which will later form contact electrodes, are drilled. Here, the etching is effectively stopped in the lowermost silicon nitride film 6 by applying the conditions that the etching rate is particularly high for the silicon oxide film and the etching rate is low for the silicon nitride film.

  Thereafter, as shown in FIG. 11, the silicon nitride film 6 exposed at the bottoms of the holes H1 and H2 is removed under the condition that the silicon nitride film has a high etching rate. Thereafter, the photoresist film R2 is removed. Thereby, the holes H1 and H2 leading to the silicide layers 4 and 4J where the contact electrodes are to be formed can be formed. As described above, by using two types of insulating films with different etching rates, it is possible to drill holes in minute locations by the so-called SAC method in which contact holes are formed in a self-aligned manner. .

  Subsequently, as shown in FIG. 12, for example, W or the like is deposited so as to fill the holes H1 and H2, and W outside the holes H1 and H2 is removed, so that the source / drain region p1 of the p-type transistor Qp2 is formed. The electrically connected high potential contact electrode HC1 and the node contact electrode (third conductor film) NC2 electrically connected to the upper surface of the gate electrode GE3 can be formed. Thereafter, a desired wiring layer is formed.

  As described above, in the technology related to the semiconductor device exemplified in the first embodiment, the gate electrode GE3 and the source / drain region p1J, which are wirings at different locations, are covered with the silicide layer 4J, thereby providing electrical Realized the connection. As a result, the common contact electrode can be electrically connected to the common potential portion without using the shared contact electrode that has had problems such as poor contact. As a result, according to the technique exemplified in the first embodiment, the manufacturing yield of the semiconductor device can be improved.

(Embodiment 2)
In the first embodiment, the method of realizing the electrical connection between the gate electrode GE3 and the source / drain region p1J not by the shared contact electrode but by the silicide layer 4J is exemplified. At this time, an example is shown in which the electrical connection to the potential common portion in the SRAM circuit can be made by a normal contact electrode.

  On the other hand, the second embodiment exemplifies a technique for forming a shared contact electrode at a location where an integral electrical connection is made possible by the silicide layer 4J.

  The SRAM cell illustrated in the second embodiment has the same basic configuration as the SRAM cell having the structure described in the first embodiment with reference to FIG. 1, and detailed description thereof is omitted here. To do. FIG. 13 shows a cross-sectional view of the main part corresponding to the aa line in FIG. 1, as in the first embodiment.

  In the second embodiment, different structures of contact electrodes to the silicide layer 4J connecting the gate electrode GE3 and the source / drain region p1J are illustrated. The contact electrode is a so-called shared contact electrode SC3 formed in a region straddling the gate electrode GE3 and the source / drain region p1J.

  In the technique exemplified in the second embodiment, the side wall spacer 5 on the side wall of the gate electrode GE3 is partially removed, and the shared contact electrode SC3 is formed in that region. Therefore, compared with the technique studied by the present inventors, there is a low possibility of causing an increase in resistance value or a contact failure due to a reduction in the contact area. Rather, by using the shared contact electrode SC3, the silicide layer has a wider area. It becomes possible to provide an electrical connection to 4J. As a result, the manufacturing yield of the semiconductor device can be improved.

  In addition, if the shared contact electrode SC3 that has been used in the past is used in the same place, the conventional manufacturing process can be performed without introducing new element arrangement, circuit design, etc. in the contact electrode formation process in the second embodiment. It can be used as a manufacturing process of a semiconductor device with a high yield.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to the semiconductor industry required for information processing, for example, in personal computers and mobile devices.

It is a principal part top view of the semiconductor device which is one embodiment of this invention. It is sectional drawing in the aa line of the top view shown in FIG. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; It is principal part sectional drawing which expanded the sectional view shown in FIG. FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; It is principal part sectional drawing to which the sectional view shown in FIG. 7 was expanded. FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. It is a principal part top view of the semiconductor device which the present inventors examined. It is sectional drawing in the aa line of the top view shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation part 3 Active region 4 Silicide layer 4J Silicide layer (2nd conductor film)
5 Sidewall spacer (second insulating film)
51, 52 Silicon oxide film 6 Silicon nitride film (third insulating film)
7 Silicon oxide film (4th insulating film)
8 silicon oxide film 9 cap insulating film A first direction B second direction pw p-type well nw n-type well Qn1 to Qn4 n-type field effect transistor Qp1 p-type field effect transistor (first field effect transistor)
Qp2 p-type field effect transistor (second field effect transistor)
Qpx p-type field effect transistor J 1st part GE1 to GE4, GEx Gate electrode (first conductor film)
GZ1 Gate insulating film (first insulating film)
WC1 Word contact electrode BC1 Bit contact electrode NC1, NC2 Node contact electrode (third conductor film)
LC1 Low potential contact electrode HC1 High potential contact electrode SC1 to SC3 Shared contact electrode n1, n2, p1, p1J, p2 Source / drain region (semiconductor region)
The film thickness of the retraction amount t silicide layer of k gate insulating film t _ox gate insulating film with a thickness of p11 extension regions R1, R2 photoresist film H1, H2 hole

Claims (5)

(A) a first conductor film formed via a first insulating film so as to extend in the first direction of the main surface of the semiconductor substrate;
(B) a semiconductor region formed on the main surface of the semiconductor substrate so as to reach a lower portion of the side wall of the first conductor film;
(C) a second insulating film provided on a portion of the side wall of the first conductor film excluding the first portion reached by the semiconductor region;
(D) covering the upper surface of the semiconductor region, and the first conductor film covering a side wall portion of the first portion and an upper surface portion adjacent to the side wall portion; and the semiconductor region and the pattern of the first conductor film. A second conductor film to be electrically connected;
(E) a third insulating film and a fourth insulating film, which are sequentially deposited on the main surface of the semiconductor substrate so as to cover the first conductor film and the second insulating film, and have different etching rates for the same etching conditions;
(F) a hole drilled in the third and fourth insulating films so as to reach the second conductor film;
(G) a third conductor film embedded in the hole and electrically connected to the second conductor film;
The third conductor film is electrically connected to any one of the upper surface of the first conductor film, the upper surface of the semiconductor region, or a region straddling them among the second conductor films. Semiconductor device. The semiconductor device according to claim 1,
The first conductor film also serves as the gate electrode of the first field effect transistor in any part of the extending first direction,
The semiconductor region also serves as a source / drain region of the second field effect transistor,
The semiconductor device, wherein the first field effect transistor and the second field effect transistor are elements constituting a static semiconductor memory element. (A) forming a first insulating film and a first conductor film in order on the main surface of the semiconductor substrate;
(B) processing the first conductor film and the first insulating film into a shape extending in the first direction of the main surface of the semiconductor substrate;
(C) forming a second insulating film so as to cover the side wall of the first conductor film;
(D) a step of selectively removing a part of the second insulating film formed in the step (c);
(E) forming a semiconductor region by introducing impurities into a region not covered with the first conductor film and the second insulating film;
(F) so as to cover the side surface of the first conductor film, the upper surface of the first conductor film, and the surface of the semiconductor region where the second insulating film is removed by the step (d); Forming a second conductor film so as to be electrically connected to the first conductor film and the semiconductor region;
(G) a step of sequentially forming a third insulating film and a fourth insulating film having different etching rates so as to cover the main surface of the semiconductor substrate;
(H) The fourth insulating film and the third insulating film are etched in order to form a hole exposing the second conductor film, and then electrically connected to the second conductor film in the hole. Forming a third conductor film to be formed,
The third conductor film formed in the step (h) is electrically connected to any one of the upper surface of the first conductor film, the semiconductor region, or a region straddling the second conductor film. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed to be connected. In the manufacturing method of the semiconductor device according to claim 3,
(I) After the completion of the step (d) and before reaching the step (f), the first insulating film under the first conductive film at a position where the second insulating film is removed in the step (d). And a step of selectively removing so as to recede by a length equal to or more than half the film thickness of the second conductor film formed in the step (f) when viewed from the edge of the first conductor film. ,
The method of manufacturing a semiconductor device, wherein the second conductor film formed in the step (f) is thicker than the first insulating film formed in the step (a). In the manufacturing method of the semiconductor device according to claim 3 or 4,
The first conductor film is formed so as to double as the gate electrode of the first field effect transistor in any part of the extending first direction.
The semiconductor region is formed to serve as a source / drain region of the second field effect transistor,
The method of manufacturing a semiconductor device, wherein the first field effect transistor and the second field effect transistor are formed to be elements constituting a static semiconductor memory element.

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