JP5209224B2 - 半導体素子のボンディングパッド構造の製造方法 - Google Patents
半導体素子のボンディングパッド構造の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000000034 method Methods 0.000 title description 16
- 239000012212 insulator Substances 0.000 claims description 98
- 239000000758 substrate Substances 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- 239000000523 sample Substances 0.000 description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 11
- 239000010937 tungsten Substances 0.000 description 11
- 239000010410 layer Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000013068 control sample Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- 230000000644 propagated effect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
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Description
本発明に係るボンディングパッド構造を持つ第1試料を170個準備した。即ち、基板上に4層のアルミニウム配線を通常の工程で形成するとともに、島型絶縁体間の間隔が3.4μmの一体型メッシュ型タングステンプラグを各配線間に形成し、各配線を電気的に連結し、さらに最上部配線上に平坦化膜を形成した後、これをパターニングしてボンディングワイヤ領域を露出させた後、ウェッジ方法でワイヤをボンディングして試料を準備した。
実験例1と同一に形成した第1試料と第1及び第2対照試料について、ワイヤとボンディングパッドとして機能するアルミニウム配線間の接触が不良なのでワイヤが取れるパッドオープンと、ボンディング時配線膜が取れる配線オープンの発生頻度を各々測定した。パッドオープンと配線オープンとを測定した後、第1試料158個、第1対照試料140及び第2対照試料142個に対して、最上部アルミニウム配線膜下部の島型絶縁層又は層間絶縁膜で発生する亀裂の数を測定した。亀裂数の測定は各試料の平坦化膜と最上部アルミニウム配線膜とを適切な食刻液を使用して除去した後、走査電子顕微鏡を使用して測定した。
925I, 945I 島型絶縁体
930 下部一体型導電性プラグ
940 中間配線
950 上部一体型導電性プラグ
960 最上部配線
970 ワイヤボンディング領域
Claims (6)
- 半導体基板上に下部導電膜を形成する段階と、
前記下部導電膜上に、前記下部導電膜と電気的及び物理的に連結された板型導電膜を形成する段階と、
前記下部導電膜と前記板型導電膜との電気的及び物理的連結を維持したまま、前記下部導電膜の表面領域の一部が露出するまで前記板型導電膜を垂直方向に食刻して、前記板型導電膜の側辺を除いた内側に相互隔離された複数個のホールを形成する段階と、
前記ホールを埋め込む絶縁膜を形成する段階と、
前記板型導電膜上に形成されている絶縁膜を除去して前記複数個のホールにのみ絶縁膜が残るようにする段階と、
前記板型導電膜上に、前記板型導電膜と電気的及び物理的に連結された上部導電膜を形成する段階とを含み、
前記複数個のホールを形成する段階において、前記板型導電膜はその内部で隔離されず一体型となるように食刻されることを特徴とする半導体素子のボンディングパッド構造の製造方法。 - 半導体基板上に第1導電膜を形成する段階と、
前記第1導電膜上に、前記第1導電膜と電気的及び物理的に連結された第1連続的な導電膜を形成するが、前記第1連続的な導電膜を垂直方向に貫通しながら延びてその側壁が前記第1連続的な導電膜で取り囲まれた複数個の第1島型絶縁体を含む前記第1連続的な導電膜を形成する段階と、
前記第1連続的な導電膜上に、前記第1連続的な導電膜と電気的及び物理的に連結された第2導電膜を形成する段階を含み、
前記第1連続的な導電膜を形成する段階は、
前記第1導電膜上に、前記第1導電膜と電気的及び物理的に連結された板型導電膜を形成する段階と、
前記第1導電膜と前記板型導電膜との電気的及び物理的連結を維持したまま、前記第1導電膜の表面領域の一部が露出するまで前記板型導電膜を垂直方向に食刻して、前記板型導電膜の側辺を除いた内側に相互隔離された複数個のホールを形成する段階を含み、
前記第1島型絶縁体を形成する段階は、
前記ホールを埋め込む絶縁膜を形成する段階と、
前記板型導電膜上に形成されている絶縁膜を除去して前記複数個のホールにのみ絶縁膜が残るようにする段階とを含み、
前記複数個のホールを形成する段階において、前記板型導電膜はその内部で隔離されず一体型となるように食刻されることを特徴とする半導体素子のボンディングパッド構造の製造方法。 - 前記第1連続的な導電膜は、ワイヤボンディング領域を上部に有する中心部を備え、前記中心部に絶縁体が形成されることを特徴とする請求項2に記載の半導体素子のボンディングパッド構造の製造方法。
- 前記第2導電膜上に電気的に連結された第2連続的な導電膜を形成するが、前記第2連続的な導電膜を貫通しながら延びてその側壁が前記第2連続的な導電膜で取り囲まれた複数個の第2島型絶縁体を含む前記第2連続的な導電膜を形成する段階をさらに含むことを特徴とする請求項2に記載の半導体素子のボンディングパッド構造の製造方法。
- 前記第1島型絶縁体と前記第2島型絶縁体とは前記第2導電膜を間に介して重なり合うことを特徴とする請求項4に記載の半導体素子のボンディングパッド構造の製造方法。
- 前記第1島型絶縁体と前記第2島型絶縁体とは前記第2導電膜を貫通して一体となるように連結されることを特徴とする請求項5に記載の半導体素子のボンディングパッド構造の製造方法。
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KR19980059418 | 1998-12-28 | ||
KR1019990062154A KR100319896B1 (ko) | 1998-12-28 | 1999-12-24 | 반도체 소자의 본딩 패드 구조 및 그 제조 방법 |
KR1998P-59418 | 1999-12-24 | ||
KR1999P-62154 | 1999-12-24 |
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JP2007098534A Expired - Fee Related JP5209224B2 (ja) | 1998-12-28 | 2007-04-04 | 半導体素子のボンディングパッド構造の製造方法 |
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Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000195896A (ja) | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体装置 |
KR20020021123A (ko) * | 2000-04-12 | 2002-03-18 | 롤페스 요하네스 게라투스 알베르투스 | 반도체 디바이스 및 이의 제조 방법 |
JP3434793B2 (ja) | 2000-09-29 | 2003-08-11 | Necエレクトロニクス株式会社 | 半導体装置とその製造方法 |
KR100500416B1 (ko) * | 2000-11-15 | 2005-07-12 | 주식회사 하이닉스반도체 | 반도체 소자의 패드 제조 방법 |
KR100421043B1 (ko) * | 2000-12-21 | 2004-03-04 | 삼성전자주식회사 | 비정렬되고 소정 거리 이격된 섬형 절연체들의 배열을 갖는 도전막을 포함하는 집적 회로 본딩 패드 |
US7692315B2 (en) | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
JP2004095916A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
CN1601735B (zh) * | 2003-09-26 | 2010-06-23 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
JP4579621B2 (ja) * | 2003-09-26 | 2010-11-10 | パナソニック株式会社 | 半導体装置 |
US6960836B2 (en) * | 2003-09-30 | 2005-11-01 | Agere Systems, Inc. | Reinforced bond pad |
JP4759229B2 (ja) * | 2004-05-12 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2006024698A (ja) | 2004-07-07 | 2006-01-26 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100675275B1 (ko) * | 2004-12-16 | 2007-01-26 | 삼성전자주식회사 | 반도체 장치 및 이 장치의 패드 배치방법 |
JP4452217B2 (ja) | 2005-07-04 | 2010-04-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
JP4757660B2 (ja) * | 2006-02-27 | 2011-08-24 | エルピーダメモリ株式会社 | 半導体装置 |
DE112009004978B4 (de) | 2009-04-28 | 2020-06-04 | Mitsubishi Electric Corp. | Leistungshalbleitervorrichtung |
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JPS57172752A (en) * | 1981-04-16 | 1982-10-23 | Fujitsu Ltd | Semiconductor device |
JPS61239646A (ja) * | 1985-04-16 | 1986-10-24 | Nec Corp | 多層配線の形成方法 |
JP2916326B2 (ja) * | 1992-06-11 | 1999-07-05 | 三菱電機株式会社 | 半導体装置のパッド構造 |
US5248903A (en) * | 1992-09-18 | 1993-09-28 | Lsi Logic Corporation | Composite bond pads for semiconductor devices |
JPH06196525A (ja) * | 1992-12-24 | 1994-07-15 | Kawasaki Steel Corp | ボンディングパッドの構造 |
JPH06326150A (ja) * | 1993-05-12 | 1994-11-25 | Sony Corp | パッド構造 |
JP3432284B2 (ja) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | 半導体装置 |
JPH08162532A (ja) * | 1994-12-05 | 1996-06-21 | Sony Corp | 半導体装置の製造方法 |
JPH08213422A (ja) * | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | 半導体装置およびそのボンディングパッド構造 |
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH09162290A (ja) * | 1995-12-04 | 1997-06-20 | Ricoh Co Ltd | 半導体集積回路装置 |
KR100200700B1 (ko) * | 1996-02-29 | 1999-06-15 | 윤종용 | 다층 패드를 구비하는 반도체장치 및 그 제조방법 |
JP3482779B2 (ja) * | 1996-08-20 | 2004-01-06 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP2001085465A (ja) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | 半導体装置 |
-
1999
- 1999-12-24 KR KR1019990062154A patent/KR100319896B1/ko active IP Right Grant
- 1999-12-28 JP JP11375282A patent/JP2000195866A/ja active Pending
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Also Published As
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JP2007194663A (ja) | 2007-08-02 |
KR20000048406A (ko) | 2000-07-25 |
KR100319896B1 (ko) | 2002-01-10 |
JP2000195866A (ja) | 2000-07-14 |
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