JP2007194663A - 半導体素子のボンディングパッド構造 - Google Patents
半導体素子のボンディングパッド構造 Download PDFInfo
- Publication number
- JP2007194663A JP2007194663A JP2007098534A JP2007098534A JP2007194663A JP 2007194663 A JP2007194663 A JP 2007194663A JP 2007098534 A JP2007098534 A JP 2007098534A JP 2007098534 A JP2007098534 A JP 2007098534A JP 2007194663 A JP2007194663 A JP 2007194663A
- Authority
- JP
- Japan
- Prior art keywords
- conductive film
- bonding pad
- continuous
- conductive
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000012212 insulator Substances 0.000 claims abstract description 121
- 238000010586 diagram Methods 0.000 description 18
- 238000000034 method Methods 0.000 description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- 239000000523 sample Substances 0.000 description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 11
- 239000010937 tungsten Substances 0.000 description 11
- 239000010410 layer Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000013068 control sample Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000000644 propagated effect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】所定距離離隔された第1導電膜及び第2導電膜と、この第1導電膜及び第2導電膜の間に存在して所定距離離隔された第1導電膜及び第2導電膜を電気的に連結する連続的な第3導電膜及びこの連続的な第3導電膜内に存在して連続的な第3導電膜を貫通するように延びてその側壁が各々連続的な第3導電膜で取り囲まれた複数個の島型絶縁体とを含む。
【選択図】 図10
Description
本発明に係るボンディングパッド構造を持つ第1試料を170個準備した。即ち、基板上に4層のアルミニウム配線を通常の工程で形成するとともに、島型絶縁体間の間隔が3.4μmの一体型メッシュ型タングステンプラグを各配線間に形成し、各配線を電気的に連結し、さらに最上部配線上に平坦化膜を形成した後、これをパターニングしてボンディングワイヤ領域を露出させた後、ウェッジ方法でワイヤをボンディングして試料を準備した。
実験例1と同一に形成した第1試料と第1及び第2対照試料について、ワイヤとボンディングパッドとして機能するアルミニウム配線間の接触が不良なのでワイヤが取れるパッドオープンと、ボンディング時配線膜が取れる配線オープンの発生頻度を各々測定した。パッドオープンと配線オープンとを測定した後、第1試料158個、第1対照試料140及び第2対照試料142個に対して、最上部アルミニウム配線膜下部の島型絶縁層又は層間絶縁膜で発生する亀裂の数を測定した。亀裂数の測定は各試料の平坦化膜と最上部アルミニウム配線膜とを適切な食刻液を使用して除去した後、走査電子顕微鏡を使用して測定した。
925I, 945I 島型絶縁体
930 下部一体型導電性プラグ
940 中間配線
950 上部一体型導電性プラグ
960 最上部配線
970 ワイヤボンディング領域
Claims (23)
- 上下に所定距離離隔されたワイヤボンディング領域を含む上部の第1導電膜及び下部の第2導電膜と、
前記第1導電膜及び第2導電膜の間に存在し、前記所定距離離隔された第1導電膜及び第2導電膜を電気的に連結する連続的な第3導電膜と、
前記連続的な第3導電膜内に存在し、前記連続的な第3導電膜を貫通するように延びてその側壁が各々前記連続的な第3導電膜で取り囲まれた複数個の第1島型絶縁体とを具備することを特徴とする半導体素子のボンディングパッド構造。 - 前記第2導電膜と所定距離離隔された第4導電膜と、
前記第4導電膜と前記第2導電膜との間に存在し、前記第2導電膜を前記第4導電膜と電気的に連結する連続的な第5導電膜と、
前記連続的な第5導電膜内に存在し、前記連続的な第5導電膜を貫通するように延びてその側壁が各々前記連続的な第5導電膜で取り囲まれた複数個の第2島型絶縁体とをさらに含むことを特徴とする請求項1に記載の半導体素子のボンディングパッド構造。 - 前記第2導電膜内に存在し、前記第2導電膜を貫通するように延びてその側壁が各々前記第2導電膜で取り囲まれた複数個の第3島型絶縁体をさらに含むことを特徴とする請求項2に記載の半導体素子のボンディングパッド構造。
- 前記第1及び第2島型絶縁体は、前記第2導電膜を介した上部及び下部に重畳されることを特徴とする請求項2に記載の半導体素子のボンディングパッド構造。
- 前記第1及び第2島型絶縁体は、前記第2導電膜を介した上部及び下部で一つに連結されるように頂点部分が一致することを特徴とする請求項4に記載の半導体素子のボンディングパッド構造。
- 前記第1,第2及び第3島型絶縁体は、前記第2導電膜内の前記第3島型絶縁体を介した上部及び下部に前記第2及び第3島型絶縁体が重畳されることを特徴とする請求項3に記載の半導体素子のボンディングパッド構造。
- 前記第1及び第2島型絶縁体は、前記第2導電膜内の第3島型絶縁体を介した上部及び下部で一つに連結されるように頂点部分が一致することを特徴とする請求項6に記載の半導体素子のボンディングパッド構造。
- 前記所定距離離隔された第1及び第2導電膜は所定距離離隔された板型導電膜であることを特徴とする請求項1に記載の半導体素子のボンディングパッド構造。
- 前記連続的な第3導電膜は、第1導電膜でワイヤボンディング領域の下部に第4絶縁体を含み、前記第1島型絶縁体は前記第4絶縁体が形成されない部分にだけ存在することを特徴とする請求項1に記載の半導体素子のボンディングパッド構造。
- 前記島型絶縁体は円柱形、角柱形又はこれらの組合であることを特徴とする請求項1に記載の半導体素子のボンディングパッド構造。
- 上下に所定距離離隔した第1導電膜及び第2導電膜と、
前記第1導電膜及び第2導電膜間に存在し、前記所定距離離隔した第1導電膜及び第2導電膜を電気的に連結する連続的な第3導電膜と、
前記連続的な第3導電膜内に隣接した島型絶縁体がジグザグ状に配列され、前記連続的な第3導電膜を貫通しながら延びてその側壁が各々前記連続的な第3導電膜で取り囲まれた複数個の島型絶縁体とを含むことを特徴とする半導体素子のボンディングパッド構造。 - 所定距離離隔されて配置された下部配線、中間配線及びボンディングパッド領域として使用される上部配線と、
前記上部配線と中間配線との間に存在し、前記上部配線及び中間配線を電気的に連結する連続的な第1導電性プラグと、
前記連続的な第1導電性プラグ内に存在し、前記連続的な第1導電性プラグを貫通するように延びてその側壁が各々前記連続的な第1導電性プラグで取り囲まれた複数個の第1島型絶縁体と、
前記中間配線と前記下部配線との間に存在し、前記中間配線及び前記下部配線を電気的に連結する連続的な第2導電性プラグと、
前記連続的な第2導電性プラグ内に存在し、前記連続的な第2導電性プラグを貫通するように延びてその側壁が各々前記連続的な第2導電性プラグで取り囲まれた複数個の第2島型絶縁体と
を具備することを特徴とする半導体素子のボンディングパッド構造。 - 前記第1及び第2島型絶縁体は、前記第2導電膜を介して上部及び下部に重畳されることを特徴とする請求項12に記載の半導体素子のボンディングパッド構造。
- 前記第1及び第2島型絶縁体は、前記第2導電膜を介した上部及び下部で一つに連結されるように頂点部分が一致することを特徴とする請求項13に記載の半導体素子のボンディングパッド構造。
- 前記中間配線内に存在し、前記中間配線を貫通するように延びてその側壁が各々前記中間配線で取り囲まれた複数個の第3島型絶縁体をさらに含むことを特徴とする請求項12に記載の半導体素子のボンディングパッド構造。
- 前記第1,第2及び第3島型絶縁体は、前記第2導電膜内の前記第3島型絶縁体を介した上部及び下部に前記第2及び第3島型絶縁体が重畳されることを特徴とする請求項15に記載の半導体素子のボンディングパッド構造。
- 前記第1及び第2島型絶縁体は、前記第2導電膜内の第3島型絶縁体を介した上部及び下部で一つに連結されるように頂点部分が一致することを特徴とする請求項16に記載の半導体素子のボンディングパッド構造。
- 前記下部配線、中間配線及び上部配線は各々板型配線であることを特徴とする請求項12に記載の半導体素子のボンディングパッド構造。
- 前記連続的な第1及び第2導電性プラグは、各々前記第1及び第2導電性プラグにおいて前記上部配線の前記ワイヤボンディング領域の下部を除いた部分にだけ存在することを特徴とする請求項12に記載の半導体素子のボンディングパッド構造。
- 前記島型絶縁体は円柱形、角柱形又はこれらの組み合せであることを特徴とする請求項12に記載の半導体素子のボンディングパッド構造。
- 上下に所定距離離隔して配置された下部配線、中間配線及びボンディングパッド領域として用いられる上部配線と、
前記上部配線と中間配線との間に存在し、前記上部配線及び中間配線を電気的に連結する連続的な第1導電性プラグと、
前記連続的な第1導電性プラグ内に隣接した島型絶縁体がジグザグ状に配列され、前記連続的な第1導電性プラグを貫通しながら延びてその側壁が各々前記連続的な第1導電性プラグで取り囲まれた複数個の第1島型絶縁体と、
前記中間配線と前記下部配線との間に存在し、前記中間配線及び前記下部配線を電気的に連結する連続的な第2導電性プラグと、
前記連続的な第2導電性プラグ内に存在し、前記連続的な第2導電性プラグを貫通しながら延びてその側壁が各々前記連続的な第2導電性プラグで取り囲まれた複数個の第2島型絶縁体と
を含むことを特徴とする半導体素子のボンディングパッド構造。 - 前記第2島型絶縁体も前記連続的な第2導電性プラグ内に隣接した島型絶縁体がジグザグ状に配列されることを特徴とする請求項21に記載の半導体素子のボンディングパッド構造。
- 前記第1及び第2島型絶縁体は相互重なることを特徴とする請求項22に記載の半導体素子のボンディングパッド構造。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1998P-59418 | 1998-12-28 | ||
KR19980059418 | 1998-12-28 | ||
KR1999P-62154 | 1999-12-24 | ||
KR1019990062154A KR100319896B1 (ko) | 1998-12-28 | 1999-12-24 | 반도체 소자의 본딩 패드 구조 및 그 제조 방법 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11375282A Division JP2000195866A (ja) | 1998-12-28 | 1999-12-28 | 半導体素子のボンディングパッド構造及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007194663A true JP2007194663A (ja) | 2007-08-02 |
JP2007194663A5 JP2007194663A5 (ja) | 2010-08-12 |
JP5209224B2 JP5209224B2 (ja) | 2013-06-12 |
Family
ID=26634489
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11375282A Pending JP2000195866A (ja) | 1998-12-28 | 1999-12-28 | 半導体素子のボンディングパッド構造及びその製造方法 |
JP2007098534A Expired - Fee Related JP5209224B2 (ja) | 1998-12-28 | 2007-04-04 | 半導体素子のボンディングパッド構造の製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11375282A Pending JP2000195866A (ja) | 1998-12-28 | 1999-12-28 | 半導体素子のボンディングパッド構造及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
JP (2) | JP2000195866A (ja) |
KR (1) | KR100319896B1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000195896A (ja) | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体装置 |
EP1275152A2 (en) * | 2000-04-12 | 2003-01-15 | Koninklijke Philips Electronics N.V. | Bonding pad in semiconductor device |
JP3434793B2 (ja) | 2000-09-29 | 2003-08-11 | Necエレクトロニクス株式会社 | 半導体装置とその製造方法 |
KR100500416B1 (ko) * | 2000-11-15 | 2005-07-12 | 주식회사 하이닉스반도체 | 반도체 소자의 패드 제조 방법 |
KR100421043B1 (ko) * | 2000-12-21 | 2004-03-04 | 삼성전자주식회사 | 비정렬되고 소정 거리 이격된 섬형 절연체들의 배열을 갖는 도전막을 포함하는 집적 회로 본딩 패드 |
US7692315B2 (en) | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
JP2004095916A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4579621B2 (ja) * | 2003-09-26 | 2010-11-10 | パナソニック株式会社 | 半導体装置 |
CN1601735B (zh) | 2003-09-26 | 2010-06-23 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
US6960836B2 (en) * | 2003-09-30 | 2005-11-01 | Agere Systems, Inc. | Reinforced bond pad |
JP4759229B2 (ja) * | 2004-05-12 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2006024698A (ja) | 2004-07-07 | 2006-01-26 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100675275B1 (ko) * | 2004-12-16 | 2007-01-26 | 삼성전자주식회사 | 반도체 장치 및 이 장치의 패드 배치방법 |
JP4452217B2 (ja) | 2005-07-04 | 2010-04-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
JP4757660B2 (ja) * | 2006-02-27 | 2011-08-24 | エルピーダメモリ株式会社 | 半導体装置 |
JP5599388B2 (ja) | 2009-04-28 | 2014-10-01 | 三菱電機株式会社 | 電力用半導体装置 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57172752A (en) * | 1981-04-16 | 1982-10-23 | Fujitsu Ltd | Semiconductor device |
JPS61239646A (ja) * | 1985-04-16 | 1986-10-24 | Nec Corp | 多層配線の形成方法 |
JPH05343466A (ja) * | 1992-06-11 | 1993-12-24 | Mitsubishi Electric Corp | 半導体装置のパッド構造 |
JPH06196525A (ja) * | 1992-12-24 | 1994-07-15 | Kawasaki Steel Corp | ボンディングパッドの構造 |
JPH06204283A (ja) * | 1992-09-18 | 1994-07-22 | Lsi Logic Corp | 半導体用ボンドパッド |
JPH08162532A (ja) * | 1994-12-05 | 1996-06-21 | Sony Corp | 半導体装置の製造方法 |
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH09162290A (ja) * | 1995-12-04 | 1997-06-20 | Ricoh Co Ltd | 半導体集積回路装置 |
JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001085465A (ja) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | 半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06326150A (ja) * | 1993-05-12 | 1994-11-25 | Sony Corp | パッド構造 |
JP3432284B2 (ja) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | 半導体装置 |
JPH08213422A (ja) * | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | 半導体装置およびそのボンディングパッド構造 |
KR100200700B1 (ko) * | 1996-02-29 | 1999-06-15 | 윤종용 | 다층 패드를 구비하는 반도체장치 및 그 제조방법 |
-
1999
- 1999-12-24 KR KR1019990062154A patent/KR100319896B1/ko active IP Right Grant
- 1999-12-28 JP JP11375282A patent/JP2000195866A/ja active Pending
-
2007
- 2007-04-04 JP JP2007098534A patent/JP5209224B2/ja not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57172752A (en) * | 1981-04-16 | 1982-10-23 | Fujitsu Ltd | Semiconductor device |
JPS61239646A (ja) * | 1985-04-16 | 1986-10-24 | Nec Corp | 多層配線の形成方法 |
JPH05343466A (ja) * | 1992-06-11 | 1993-12-24 | Mitsubishi Electric Corp | 半導体装置のパッド構造 |
JPH06204283A (ja) * | 1992-09-18 | 1994-07-22 | Lsi Logic Corp | 半導体用ボンドパッド |
JPH06196525A (ja) * | 1992-12-24 | 1994-07-15 | Kawasaki Steel Corp | ボンディングパッドの構造 |
JPH08162532A (ja) * | 1994-12-05 | 1996-06-21 | Sony Corp | 半導体装置の製造方法 |
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH09162290A (ja) * | 1995-12-04 | 1997-06-20 | Ricoh Co Ltd | 半導体集積回路装置 |
JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001085465A (ja) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR100319896B1 (ko) | 2002-01-10 |
JP2000195866A (ja) | 2000-07-14 |
KR20000048406A (ko) | 2000-07-25 |
JP5209224B2 (ja) | 2013-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5209224B2 (ja) | 半導体素子のボンディングパッド構造の製造方法 | |
US6552438B2 (en) | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same | |
KR100267105B1 (ko) | 다층패드를구비한반도체소자및그제조방법 | |
US7741207B2 (en) | Semiconductor device with multilayered metal pattern | |
US5736791A (en) | Semiconductor device and bonding pad structure therefor | |
US6163074A (en) | Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein | |
JP4199846B2 (ja) | 半導体ウェーハ上の多層試験パッドおよびその形成方法 | |
JP4297682B2 (ja) | 半導体素子及びその製造方法 | |
TWI287267B (en) | Bonding pad structure of semiconductor device and method for fabricating the same | |
CN109935568A (zh) | 半导体器件及其制作方法 | |
JP3952260B2 (ja) | 集積回路のためのボンディングパッド | |
US6921976B2 (en) | Semiconductor device including an island-like dielectric member embedded in a conductive pattern | |
KR100382724B1 (ko) | 여러 종류의 콘택 스터드들을 포함하는 반도체 장치 제조방법 | |
JP3239843B2 (ja) | 半導体装置の製造方法 | |
JPH05175191A (ja) | 積層導電配線 | |
JP4579621B2 (ja) | 半導体装置 | |
JP2008098225A (ja) | 半導体装置 | |
JP2015002234A (ja) | 半導体装置及びその製造方法 | |
KR20070060340A (ko) | 반도체 소자의 퓨즈 및 그 형성방법 | |
JP2008066440A (ja) | 半導体装置およびその製造方法 | |
KR100471171B1 (ko) | 반도체 소자의 다층 본딩 패드 구조 및 그 제조 방법 | |
KR100725086B1 (ko) | 다층 배선 형성 공정에서의 패드층 형성방법 | |
US8330190B2 (en) | Semiconductor device | |
KR20010084438A (ko) | 퓨즈를 갖는 반도체 장치의 제조 방법 | |
KR20040085911A (ko) | 반도체소자의 테스트 패턴 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100624 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110104 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110329 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20111220 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120402 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120409 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20120502 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130221 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160301 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5209224 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |