JP5086709B2 - データ入出力エラー検出機能を有する半導体メモリ装置 - Google Patents

データ入出力エラー検出機能を有する半導体メモリ装置

Info

Publication number
JP5086709B2
JP5086709B2 JP2007171957A JP2007171957A JP5086709B2 JP 5086709 B2 JP5086709 B2 JP 5086709B2 JP 2007171957 A JP2007171957 A JP 2007171957A JP 2007171957 A JP2007171957 A JP 2007171957A JP 5086709 B2 JP5086709 B2 JP 5086709B2
Authority
JP
Japan
Prior art keywords
data
output
error detection
semiconductor memory
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007171957A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008071470A5 (enExample
JP2008071470A (ja
Inventor
相 植 尹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Publication of JP2008071470A publication Critical patent/JP2008071470A/ja
Publication of JP2008071470A5 publication Critical patent/JP2008071470A5/ja
Application granted granted Critical
Publication of JP5086709B2 publication Critical patent/JP5086709B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP2007171957A 2006-09-13 2007-06-29 データ入出力エラー検出機能を有する半導体メモリ装置 Active JP5086709B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060088740A KR100837802B1 (ko) 2006-09-13 2006-09-13 데이터 입출력 오류 검출 기능을 갖는 반도체 메모리 장치
KR10-2006-0088740 2006-09-13

Publications (3)

Publication Number Publication Date
JP2008071470A JP2008071470A (ja) 2008-03-27
JP2008071470A5 JP2008071470A5 (enExample) 2010-05-20
JP5086709B2 true JP5086709B2 (ja) 2012-11-28

Family

ID=39262462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007171957A Active JP5086709B2 (ja) 2006-09-13 2007-06-29 データ入出力エラー検出機能を有する半導体メモリ装置

Country Status (3)

Country Link
US (1) US7877675B2 (enExample)
JP (1) JP5086709B2 (enExample)
KR (1) KR100837802B1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008204085A (ja) * 2007-02-19 2008-09-04 Toshiba Corp 半導体記憶装置
KR100902051B1 (ko) * 2007-07-12 2009-06-15 주식회사 하이닉스반도체 오류 검사 코드 생성장치 및 방법
US7616133B2 (en) * 2008-01-16 2009-11-10 Micron Technology, Inc. Data bus inversion apparatus, systems, and methods
KR100951567B1 (ko) * 2008-02-29 2010-04-09 주식회사 하이닉스반도체 데이터 전달의 신뢰성을 보장하기 위한 반도체 메모리 장치
KR100954109B1 (ko) * 2008-08-29 2010-04-23 주식회사 하이닉스반도체 데이터 입력회로 및 이를 포함하는 반도체 메모리장치
KR100933806B1 (ko) * 2008-09-22 2009-12-24 주식회사 하이닉스반도체 반도체 메모리장치
KR101039862B1 (ko) * 2008-11-11 2011-06-13 주식회사 하이닉스반도체 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법
KR101062759B1 (ko) 2009-08-11 2011-09-06 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 데이터 독출 방법
KR101897515B1 (ko) 2012-08-28 2018-09-12 에스케이하이닉스 주식회사 집적회로
KR102035108B1 (ko) 2013-05-20 2019-10-23 에스케이하이닉스 주식회사 반도체 시스템
US9583218B1 (en) * 2014-01-24 2017-02-28 Altera Corporation Configurable register circuitry for error detection and recovery
KR20150142814A (ko) 2014-06-11 2015-12-23 에스케이하이닉스 주식회사 리페어 정보 제어 기능을 갖는 반도체 장치
US11403170B2 (en) * 2014-08-05 2022-08-02 Macronix International Co., Ltd. Method and device for monitoring data error status in a memory
US10908817B2 (en) * 2017-12-08 2021-02-02 Sandisk Technologies Llc Signal reduction in a microcontroller architecture for non-volatile memory
CN112712833B (zh) * 2019-10-25 2024-10-01 长鑫存储技术(上海)有限公司 写操作电路、半导体存储器和写操作方法
US12099746B2 (en) 2019-12-16 2024-09-24 Micron Technology, Inc. Interrupt signaling for a memory device
CN115129234B (zh) * 2021-03-26 2025-01-10 长鑫存储技术有限公司 数据传输电路、方法及存储装置
EP4198704A4 (en) * 2021-03-29 2024-05-15 Changxin Memory Technologies, Inc. DATA TRANSMISSION CIRCUIT AND METHOD AND STORAGE DEVICE
CN115775588B (zh) * 2021-09-08 2025-10-14 长鑫存储技术有限公司 一种数据路径检测方法、装置、设备及存储介质
US12182414B2 (en) 2021-09-08 2024-12-31 Changxin Memory Technologies, Inc. Method and apparatus for detecting data path, and storage medium

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57169867A (en) 1981-04-14 1982-10-19 Nec Corp Detector for picture memory error
JPH02143991A (ja) * 1988-11-25 1990-06-01 Hitachi Ltd 半導体記憶装置
JP2554179B2 (ja) * 1989-11-20 1996-11-13 株式会社日立製作所 導通試験方法
JPH05158810A (ja) 1991-12-10 1993-06-25 Fujitsu Ltd 誤り検出回路
US6178532B1 (en) * 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices
JP2002175697A (ja) 2000-12-06 2002-06-21 Toshiba Corp 半導体記憶装置及びこれを用いた情報処理装置
US6742146B2 (en) * 2001-02-14 2004-05-25 Emc Corporation Techniques for providing data within a data storage system
JP4059473B2 (ja) * 2001-08-09 2008-03-12 株式会社ルネサステクノロジ メモリカード及びメモリコントローラ
CA2366397A1 (en) 2001-12-31 2003-06-30 Tropic Networks Inc. An interface for data transfer between integrated circuits
US6898648B2 (en) 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
JP2003273840A (ja) * 2002-03-15 2003-09-26 Mitsubishi Heavy Ind Ltd 通信インターフェース装置
CN100356342C (zh) * 2003-11-18 2007-12-19 株式会社瑞萨科技 信息处理装置

Also Published As

Publication number Publication date
KR100837802B1 (ko) 2008-06-13
KR20080024413A (ko) 2008-03-18
US7877675B2 (en) 2011-01-25
JP2008071470A (ja) 2008-03-27
US20080082900A1 (en) 2008-04-03

Similar Documents

Publication Publication Date Title
JP5086709B2 (ja) データ入出力エラー検出機能を有する半導体メモリ装置
JP4948952B2 (ja) 直列入／出力インターフェスを有するマルチポートメモリ素子
JP2009211797A (ja) 半導体素子
KR100972555B1 (ko) 데이터 출력회로 및 데이터 출력방법
US8270229B2 (en) Semiconductor memory apparatus
JP4936746B2 (ja) 半導体装置
JP2010118137A (ja) 半導体メモリ装置及びその動作方法
JP2009048751A (ja) エラー修正コード（ｅｃｃ）回路テストモード
KR100557517B1 (ko) 반도체 기억 장치의 테스트 방법 및 반도체 기억 장치의테스트 회로
CN101009141B (zh) 半导体存储设备
US20110211397A1 (en) Pipe latch circuit and method for operating the same
KR101097447B1 (ko) 데이터 전송 장치
JP4426468B2 (ja) メモリエミュレーションモジュールを用いて高速でテストできるエンベデッドｍｃｕ、及びそのテスト方法
US7802154B2 (en) Method and apparatus for generating high-frequency command and address signals for high-speed semiconductor memory device testing
JP5760226B2 (ja) モジュール制御回路、半導体モジュール、及び半導体モジュールの制御方法
US8050135B2 (en) Semiconductor memory device
KR20160105655A (ko) 오류 검출 회로 및 이를 이용하는 반도체 장치
US8483005B2 (en) Internal signal generator for use in semiconductor memory device
US8473831B2 (en) Semiconductor memory apparatus and data read method of the same
JP4766272B2 (ja) 半導体集積回路装置およびそれへのモード設定方法
US20040090837A1 (en) Semiconductor memory device and test method of the same
US11830572B2 (en) Pipe latch circuit, operating method thereof, and semiconductor memory device including the same
KR100930412B1 (ko) 반도체 메모리 장치
KR20180068346A (ko) 반도체 장치 및 그의 동작 방법
KR20070068057A (ko) 반도체 메모리 장치를 위한 입력 데이터 생성 장치

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100401

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100401

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100922

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120417

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120426

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120726

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120816

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120907

R150 Certificate of patent or registration of utility model

Ref document number: 5086709

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150914

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250