JP2008071470A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008071470A5 JP2008071470A5 JP2007171957A JP2007171957A JP2008071470A5 JP 2008071470 A5 JP2008071470 A5 JP 2008071470A5 JP 2007171957 A JP2007171957 A JP 2007171957A JP 2007171957 A JP2007171957 A JP 2007171957A JP 2008071470 A5 JP2008071470 A5 JP 2008071470A5
- Authority
- JP
- Japan
- Prior art keywords
- data
- output
- error detection
- semiconductor memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2006-0088740 | 2006-09-13 | ||
| KR1020060088740A KR100837802B1 (ko) | 2006-09-13 | 2006-09-13 | 데이터 입출력 오류 검출 기능을 갖는 반도체 메모리 장치 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008071470A JP2008071470A (ja) | 2008-03-27 |
| JP2008071470A5 true JP2008071470A5 (enExample) | 2010-05-20 |
| JP5086709B2 JP5086709B2 (ja) | 2012-11-28 |
Family
ID=39262462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007171957A Active JP5086709B2 (ja) | 2006-09-13 | 2007-06-29 | データ入出力エラー検出機能を有する半導体メモリ装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7877675B2 (enExample) |
| JP (1) | JP5086709B2 (enExample) |
| KR (1) | KR100837802B1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008204085A (ja) * | 2007-02-19 | 2008-09-04 | Toshiba Corp | 半導体記憶装置 |
| KR100902051B1 (ko) * | 2007-07-12 | 2009-06-15 | 주식회사 하이닉스반도체 | 오류 검사 코드 생성장치 및 방법 |
| US7616133B2 (en) * | 2008-01-16 | 2009-11-10 | Micron Technology, Inc. | Data bus inversion apparatus, systems, and methods |
| KR100951567B1 (ko) * | 2008-02-29 | 2010-04-09 | 주식회사 하이닉스반도체 | 데이터 전달의 신뢰성을 보장하기 위한 반도체 메모리 장치 |
| KR100954109B1 (ko) * | 2008-08-29 | 2010-04-23 | 주식회사 하이닉스반도체 | 데이터 입력회로 및 이를 포함하는 반도체 메모리장치 |
| KR100933806B1 (ko) * | 2008-09-22 | 2009-12-24 | 주식회사 하이닉스반도체 | 반도체 메모리장치 |
| KR101039862B1 (ko) * | 2008-11-11 | 2011-06-13 | 주식회사 하이닉스반도체 | 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법 |
| KR101062759B1 (ko) | 2009-08-11 | 2011-09-06 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 데이터 독출 방법 |
| KR101897515B1 (ko) | 2012-08-28 | 2018-09-12 | 에스케이하이닉스 주식회사 | 집적회로 |
| KR102035108B1 (ko) | 2013-05-20 | 2019-10-23 | 에스케이하이닉스 주식회사 | 반도체 시스템 |
| US9583218B1 (en) * | 2014-01-24 | 2017-02-28 | Altera Corporation | Configurable register circuitry for error detection and recovery |
| KR20150142814A (ko) | 2014-06-11 | 2015-12-23 | 에스케이하이닉스 주식회사 | 리페어 정보 제어 기능을 갖는 반도체 장치 |
| US11403170B2 (en) * | 2014-08-05 | 2022-08-02 | Macronix International Co., Ltd. | Method and device for monitoring data error status in a memory |
| US10908817B2 (en) * | 2017-12-08 | 2021-02-02 | Sandisk Technologies Llc | Signal reduction in a microcontroller architecture for non-volatile memory |
| CN112712833B (zh) * | 2019-10-25 | 2024-10-01 | 长鑫存储技术(上海)有限公司 | 写操作电路、半导体存储器和写操作方法 |
| US12099746B2 (en) * | 2019-12-16 | 2024-09-24 | Micron Technology, Inc. | Interrupt signaling for a memory device |
| CN115129234B (zh) * | 2021-03-26 | 2025-01-10 | 长鑫存储技术有限公司 | 数据传输电路、方法及存储装置 |
| EP4198704A4 (en) * | 2021-03-29 | 2024-05-15 | Changxin Memory Technologies, Inc. | DATA TRANSMISSION CIRCUIT AND METHOD AND STORAGE DEVICE |
| CN115775588B (zh) * | 2021-09-08 | 2025-10-14 | 长鑫存储技术有限公司 | 一种数据路径检测方法、装置、设备及存储介质 |
| US12182414B2 (en) | 2021-09-08 | 2024-12-31 | Changxin Memory Technologies, Inc. | Method and apparatus for detecting data path, and storage medium |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57169867A (en) | 1981-04-14 | 1982-10-19 | Nec Corp | Detector for picture memory error |
| JPH02143991A (ja) * | 1988-11-25 | 1990-06-01 | Hitachi Ltd | 半導体記憶装置 |
| JP2554179B2 (ja) * | 1989-11-20 | 1996-11-13 | 株式会社日立製作所 | 導通試験方法 |
| JPH05158810A (ja) | 1991-12-10 | 1993-06-25 | Fujitsu Ltd | 誤り検出回路 |
| US6178532B1 (en) * | 1998-06-11 | 2001-01-23 | Micron Technology, Inc. | On-chip circuit and method for testing memory devices |
| JP2002175697A (ja) | 2000-12-06 | 2002-06-21 | Toshiba Corp | 半導体記憶装置及びこれを用いた情報処理装置 |
| US6742146B2 (en) * | 2001-02-14 | 2004-05-25 | Emc Corporation | Techniques for providing data within a data storage system |
| JP4059473B2 (ja) * | 2001-08-09 | 2008-03-12 | 株式会社ルネサステクノロジ | メモリカード及びメモリコントローラ |
| CA2366397A1 (en) | 2001-12-31 | 2003-06-30 | Tropic Networks Inc. | An interface for data transfer between integrated circuits |
| US6898648B2 (en) | 2002-02-21 | 2005-05-24 | Micron Technology, Inc. | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing |
| JP2003273840A (ja) * | 2002-03-15 | 2003-09-26 | Mitsubishi Heavy Ind Ltd | 通信インターフェース装置 |
| CN100356342C (zh) * | 2003-11-18 | 2007-12-19 | 株式会社瑞萨科技 | 信息处理装置 |
-
2006
- 2006-09-13 KR KR1020060088740A patent/KR100837802B1/ko not_active Expired - Fee Related
- 2006-12-28 US US11/646,359 patent/US7877675B2/en active Active
-
2007
- 2007-06-29 JP JP2007171957A patent/JP5086709B2/ja active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008071470A5 (enExample) | ||
| JP5086709B2 (ja) | データ入出力エラー検出機能を有する半導体メモリ装置 | |
| TW557570B (en) | Semiconductor memory device | |
| JP2012507763A5 (enExample) | ||
| TW425546B (en) | Semiconductor memory device and method of controlling the same | |
| CN101149963B (zh) | 多端口存储设备 | |
| TWI464742B (zh) | 半導體記憶體之測試模式信號產生器以及產生測試模式信號的方法 | |
| TWI237828B (en) | Write path scheme in synchronous DRAM | |
| JP2017220272A (ja) | メモリマクロおよび半導体集積回路装置 | |
| JP2013508731A5 (enExample) | ||
| JP2011071995A5 (ja) | カウンタ回路 | |
| CN102467978A (zh) | 半导体装置的输入/输出电路和方法及具有其的系统 | |
| JP2009211797A (ja) | 半導体素子 | |
| CN100407109C (zh) | 数据转换电路和半导体装置 | |
| JP2007280596A5 (enExample) | ||
| KR101161744B1 (ko) | 반도체 메모리 장치 | |
| JP2007200529A (ja) | 半導体メモリ装置 | |
| KR101097447B1 (ko) | 데이터 전송 장치 | |
| US9299399B2 (en) | Semiconductor devices including pipe latch units and system including the same | |
| KR20170126270A (ko) | 데이터 출력 회로 및 그를 포함하는 반도체 메모리 장치 | |
| KR102151574B1 (ko) | 반도체 메모리 장치 및 그의 동작방법 | |
| JP2008004218A5 (enExample) | ||
| US8520466B2 (en) | Internal command generation circuit | |
| US8612841B2 (en) | Error code pattern generation circuit and semiconductor memory device including the same | |
| JP4956295B2 (ja) | 半導体記憶装置 |