CA2366397A1 - An interface for data transfer between integrated circuits - Google PatentsAn interface for data transfer between integrated circuits
- Publication number
- CA2366397A1 CA2366397A1 CA 2366397 CA2366397A CA2366397A1 CA 2366397 A1 CA2366397 A1 CA 2366397A1 CA 2366397 CA2366397 CA 2366397 CA 2366397 A CA2366397 A CA 2366397A CA 2366397 A1 CA2366397 A1 CA 2366397A1
- Grant status
- Patent type
- Prior art keywords
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
An interface is provided for transmitting data between integrated circuits comprising an input buffer associated with one circuit for receiving and storing data cells for transmission to another circuit, a data bus for transmitting data cells stored in the buffer from one circuit to another circuit in response to a departure request, a controller for controlling the transmission of code associated with each data cell enabling errors in the data to be detected, and a second bus, separate from the data bus, for transmitting the associated code from one circuit to the other.
1. An interface for transmitting data from a first circuit to a second circuit, comprising a data bus, transmitting means for transmitting data onto the data bus, and receiving means for receiving data from the data bus, the data bus including a plurality of channels, wherein each channel comprises a first plurality of parallel bus lines, a first converter for receiving parallel data from the parallel bus lines and converting the parallel data to a serial data stream, a serial bus line coupled to the output of the of the first converter for carrying the serial data stream, a second converter for receiving the serial data stream from the serial bus line and converting the serial data stream into a parallel data flow, a second plurality of parallel bus lines for carrying the parallel data from, the second converter to said receiving means, wherein the first converter is adapted to transmit the serial data stream at a higher rate than the rate at which data is transmitted on one of said first plurality of parallel bus lines.
2. An interface as claimed in claim 1, wherein the first converter is arranged to transmit the serial data stream onto said serial bus line at a rate which is substantially equal to or greater than the net rate of transfer of parallel data over said first plurality of parallel bus lines.
3. An interface as claimed in claim 1, wherein each of said plurality of channels further comprises a third converter, a first group of parallel bus lines for carrying parallel data from said transmitting means to said third converter and a second group of parallel bus lines for carrying parallel data from said third converter to said first converter, and wherein said converter is adapted to convert the parallel data received from said transmitter for transmission on said second group of parallel bus lines, wherein the number of bus lines contained in said second group is less than the number of bus lines contained in said first group.
4. An interface as claimed in claim 1, wherein each of said plurality of channels further comprises a detector for detecting a predetermined pattern transmitted on said channel, a register for receiving data transmitted on said channel, writing means for writing data into said register in response to said detector detecting said pattern, further detection means for detecting when all of said registers contain data and reading means for reading data from each of said registers in response to said further detection means.
5. An interface as claimed in claim 1, further comprising a control bus for transmitting control signals from said first circuit to said second circuit, and further transmitting means for transmitting a code associated with data transmitted on said data bus, for enabling errors in said data to be detected.
6. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and associated code for detecting an error in said data, a first bus for transmitting data stored in said storage means from said first device to said second device, and a second bus for transmitting code stored in said storage means from said first device to said second device.
7. An interface as claimed in claim 6, further comprising generating means associated with said second device for generating and transmitting a signal to said first device requesting data from said storage means, and control means responsive to said request for outputting requested data and associated code from said storage means onto said first and second buses, respectively.
8. An interface as claimed in claim 7, wherein said control means is adapted to transmit a plurality of segments of a data cell, and a plurality of segments of associated code onto said first and second buses in successive time frames.
9. An interface as claimed in claim 8, wherein said control means is adapted to place each of a first segment of data and a first segment of associated code onto a respective first and second bus in the same time frame.
10. An interface as claimed in claim 7 or 8, wherein said control means is adapted to transmit the associated code on said second bus in no more time frames than required to transmit the associated data cell on said first bus.
11. An interface as claimed in claim 10, wherein said control means is adapted to transmit the associated code on said second bus in the same number of time frames required to transmit the associated data cell on said first bus.
12. An interface as claimed in any one of claims 8 to 11, wherein each segment of a data cell has the same length.
13. An interface as claimed in any one of claims 8 to 12, wherein each segment of associated code has the same length.
14. An interface as claimed in any one of claims 8 to 13, further including receiving means for receiving data and code from said first and second buses and timing control means for controlling the timing of transmission of data and associated code from said receiving means for further processing.
15. An interface as claimed in claim 14, wherein said receiving means comprises buffer means for storing data and associated code and said timing control means is arranged to output data and associated code only after data and associated code is stored in said buffer means.
16. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and a first bus for transmitting data stored in said storage means from said first device to said second device, generating means for generating a signal indicating the arrival of data in said storage means, and a second bus for transmitting said signal from said first device to said second device.
17. An interface as claimed in claim 16, wherein said generating means is adapted to generate and transmit a signal on said second bus indicating that a subsequent signal on said second bus will contain information associated with the arrival of data, and is further adapted to generate and transmit on said second bus in a subsequent time frame a further signal identifying a part of said storage means in which said data is stored.
18. An interface as claimed in claim 17, comprising control means for placing a plurality of segments of a data cell onto said first bus in a plurality of successive time frames and wherein said first control means is arranged to place said first and second signals on said second bus within a time period of no more than the period defined by the number of time frames required for transmitting a data cell on said first bus.
19. An interface as claimed in any one of claims 16 to 18, further comprising data departure control means associated with said second device for controlling the departure of data from said storage means in response to said arrival signal.
20. An interface as claimed in claim 19, wherein said departure control means includes generating means for generating a signal identifying a part of said storage means from which data is to be output, and wherein said interface further comprises a third bus for transmitting said generated signal to a controller associated with said first device for controlling the output of data from said storage means.
21. An interface as claimed in any one of claims 16 to 20, comprising second storage means for storing data and a data bus for transmitting data stored in said second storage means from said second device to said first device, generating means associated with said first device for generating a signal requesting data from said second storage means and for transmitting said signal from said first device to said second device on said second bus.
22. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and a first bus for transmitting data stored in said storage means from said first device to said second device, generating means for generating a signal requesting data from said storage means and a second bus for transmitting said signal from said second device to said first device.
23. An interface as claimed in claim 22, wherein said generating means is adapted to generate and transmit a first signal on said second bus indicating that a subsequent signal on said second bus will contain information associated with a data request, and is further adapted to generate and transmit on said second bus in a subsequent time frame, a further signal identifying a part of said storage means in which said data is stored.
24. An interface as claimed in claims 22 or 23, further comprising second storage means associated with said second device and generating means for generating a signal indicating the arrival of data in said second storage means and arranged to transmit said arrival signal from said second device to said first device on said second bus.
25. An interface as claimed in claim 24, wherein said generating means is adapted to generate and transmit a signal on said second bus indicating that a subsequent signal on said second bus will contain information associated with the arrival of data in said second storage means, and is further adapted to generate and transmit on said second bus in a subsequent time frame a further signal identifying a part of said second storage means in which said data is stored.
26. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and a first bus for transmitting data stored in said storage means from said first device to said second device, generating means associated with said second device for generating a signal requesting a synchronization pattern and a second bus for transmitting said signal from said second device to said first device, and a synchronization pattern generator associated with said first device for generating a synchronization pattern in response to said signal and for transmitting said synchronization pattern on said first bus.
Priority Applications (1)
|Application Number||Priority Date||Filing Date||Title|
|CA 2366397 CA2366397A1 (en)||2001-12-31||2001-12-31||An interface for data transfer between integrated circuits|
Applications Claiming Priority (4)
|Application Number||Priority Date||Filing Date||Title|
|CA 2366397 CA2366397A1 (en)||2001-12-31||2001-12-31||An interface for data transfer between integrated circuits|
|US10247472 US7751418B2 (en)||2001-12-31||2002-09-20||Apparatus and method for controlling data transmission|
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|US12718992 US8625627B2 (en)||2001-12-31||2010-03-07||Apparatus and method for controlling data transmission|
|Publication Number||Publication Date|
|CA2366397A1 true true CA2366397A1 (en)||2003-06-30|
Family Applications (1)
|Application Number||Title||Priority Date||Filing Date|
|CA 2366397 Abandoned CA2366397A1 (en)||2001-12-31||2001-12-31||An interface for data transfer between integrated circuits|
Country Status (2)
|US (2)||US7751418B2 (en)|
|CA (1)||CA2366397A1 (en)|
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|WO2002001574A1 (en)||Semiconductor memory device|