CA2366397A1 - An interface for data transfer between integrated circuits - Google PatentsAn interface for data transfer between integrated circuits Download PDF
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- CA2366397A1 CA2366397A1 CA 2366397 CA2366397A CA2366397A1 CA 2366397 A1 CA2366397 A1 CA 2366397A1 CA 2366397 CA2366397 CA 2366397 CA 2366397 A CA2366397 A CA 2366397A CA 2366397 A1 CA2366397 A1 CA 2366397A1
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- 230000004044 response Effects 0 abstract claims 5
- 239000000872 buffers Substances 0 abstract claims 4
- 230000001276 controlling effects Effects 0 abstract claims 4
- 238000003860 storage Methods 0 claims 25
- 230000001702 transmitter Effects 0 claims 1
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
An interface is provided for transmitting data between integrated circuits comprising an input buffer associated with one circuit for receiving and storing data cells for transmission to another circuit, a data bus for transmitting data cells stored in the buffer from one circuit to another circuit in response to a departure request, a controller for controlling the transmission of code associated with each data cell enabling errors in the data to be detected, and a second bus, separate from the data bus, for transmitting the associated code from one circuit to the other.
1. An interface for transmitting data from a first circuit to a second circuit, comprising a data bus, transmitting means for transmitting data onto the data bus, and receiving means for receiving data from the data bus, the data bus including a plurality of channels, wherein each channel comprises a first plurality of parallel bus lines, a first converter for receiving parallel data from the parallel bus lines and converting the parallel data to a serial data stream, a serial bus line coupled to the output of the of the first converter for carrying the serial data stream, a second converter for receiving the serial data stream from the serial bus line and converting the serial data stream into a parallel data flow, a second plurality of parallel bus lines for carrying the parallel data from, the second converter to said receiving means, wherein the first converter is adapted to transmit the serial data stream at a higher rate than the rate at which data is transmitted on one of said first plurality of parallel bus lines.
2. An interface as claimed in claim 1, wherein the first converter is arranged to transmit the serial data stream onto said serial bus line at a rate which is substantially equal to or greater than the net rate of transfer of parallel data over said first plurality of parallel bus lines.
3. An interface as claimed in claim 1, wherein each of said plurality of channels further comprises a third converter, a first group of parallel bus lines for carrying parallel data from said transmitting means to said third converter and a second group of parallel bus lines for carrying parallel data from said third converter to said first converter, and wherein said converter is adapted to convert the parallel data received from said transmitter for transmission on said second group of parallel bus lines, wherein the number of bus lines contained in said second group is less than the number of bus lines contained in said first group.
4. An interface as claimed in claim 1, wherein each of said plurality of channels further comprises a detector for detecting a predetermined pattern transmitted on said channel, a register for receiving data transmitted on said channel, writing means for writing data into said register in response to said detector detecting said pattern, further detection means for detecting when all of said registers contain data and reading means for reading data from each of said registers in response to said further detection means.
5. An interface as claimed in claim 1, further comprising a control bus for transmitting control signals from said first circuit to said second circuit, and further transmitting means for transmitting a code associated with data transmitted on said data bus, for enabling errors in said data to be detected.
6. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and associated code for detecting an error in said data, a first bus for transmitting data stored in said storage means from said first device to said second device, and a second bus for transmitting code stored in said storage means from said first device to said second device.
7. An interface as claimed in claim 6, further comprising generating means associated with said second device for generating and transmitting a signal to said first device requesting data from said storage means, and control means responsive to said request for outputting requested data and associated code from said storage means onto said first and second buses, respectively.
8. An interface as claimed in claim 7, wherein said control means is adapted to transmit a plurality of segments of a data cell, and a plurality of segments of associated code onto said first and second buses in successive time frames.
9. An interface as claimed in claim 8, wherein said control means is adapted to place each of a first segment of data and a first segment of associated code onto a respective first and second bus in the same time frame.
10. An interface as claimed in claim 7 or 8, wherein said control means is adapted to transmit the associated code on said second bus in no more time frames than required to transmit the associated data cell on said first bus.
11. An interface as claimed in claim 10, wherein said control means is adapted to transmit the associated code on said second bus in the same number of time frames required to transmit the associated data cell on said first bus.
12. An interface as claimed in any one of claims 8 to 11, wherein each segment of a data cell has the same length.
13. An interface as claimed in any one of claims 8 to 12, wherein each segment of associated code has the same length.
14. An interface as claimed in any one of claims 8 to 13, further including receiving means for receiving data and code from said first and second buses and timing control means for controlling the timing of transmission of data and associated code from said receiving means for further processing.
15. An interface as claimed in claim 14, wherein said receiving means comprises buffer means for storing data and associated code and said timing control means is arranged to output data and associated code only after data and associated code is stored in said buffer means.
16. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and a first bus for transmitting data stored in said storage means from said first device to said second device, generating means for generating a signal indicating the arrival of data in said storage means, and a second bus for transmitting said signal from said first device to said second device.
17. An interface as claimed in claim 16, wherein said generating means is adapted to generate and transmit a signal on said second bus indicating that a subsequent signal on said second bus will contain information associated with the arrival of data, and is further adapted to generate and transmit on said second bus in a subsequent time frame a further signal identifying a part of said storage means in which said data is stored.
18. An interface as claimed in claim 17, comprising control means for placing a plurality of segments of a data cell onto said first bus in a plurality of successive time frames and wherein said first control means is arranged to place said first and second signals on said second bus within a time period of no more than the period defined by the number of time frames required for transmitting a data cell on said first bus.
19. An interface as claimed in any one of claims 16 to 18, further comprising data departure control means associated with said second device for controlling the departure of data from said storage means in response to said arrival signal.
20. An interface as claimed in claim 19, wherein said departure control means includes generating means for generating a signal identifying a part of said storage means from which data is to be output, and wherein said interface further comprises a third bus for transmitting said generated signal to a controller associated with said first device for controlling the output of data from said storage means.
21. An interface as claimed in any one of claims 16 to 20, comprising second storage means for storing data and a data bus for transmitting data stored in said second storage means from said second device to said first device, generating means associated with said first device for generating a signal requesting data from said second storage means and for transmitting said signal from said first device to said second device on said second bus.
22. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and a first bus for transmitting data stored in said storage means from said first device to said second device, generating means for generating a signal requesting data from said storage means and a second bus for transmitting said signal from said second device to said first device.
23. An interface as claimed in claim 22, wherein said generating means is adapted to generate and transmit a first signal on said second bus indicating that a subsequent signal on said second bus will contain information associated with a data request, and is further adapted to generate and transmit on said second bus in a subsequent time frame, a further signal identifying a part of said storage means in which said data is stored.
24. An interface as claimed in claims 22 or 23, further comprising second storage means associated with said second device and generating means for generating a signal indicating the arrival of data in said second storage means and arranged to transmit said arrival signal from said second device to said first device on said second bus.
25. An interface as claimed in claim 24, wherein said generating means is adapted to generate and transmit a signal on said second bus indicating that a subsequent signal on said second bus will contain information associated with the arrival of data in said second storage means, and is further adapted to generate and transmit on said second bus in a subsequent time frame a further signal identifying a part of said second storage means in which said data is stored.
26. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and a first bus for transmitting data stored in said storage means from said first device to said second device, generating means associated with said second device for generating a signal requesting a synchronization pattern and a second bus for transmitting said signal from said second device to said first device, and a synchronization pattern generator associated with said first device for generating a synchronization pattern in response to said signal and for transmitting said synchronization pattern on said first bus.
Priority Applications (1)
|Application Number||Priority Date||Filing Date||Title|
|CA 2366397 CA2366397A1 (en)||2001-12-31||2001-12-31||An interface for data transfer between integrated circuits|
Applications Claiming Priority (4)
|Application Number||Priority Date||Filing Date||Title|
|CA 2366397 CA2366397A1 (en)||2001-12-31||2001-12-31||An interface for data transfer between integrated circuits|
|US10/247,472 US7751418B2 (en)||2001-12-31||2002-09-20||Apparatus and method for controlling data transmission|
|CA 2407966 CA2407966A1 (en)||2001-12-31||2002-10-11||An apparatus and method for controlling data transmission|
|US12/718,992 US8625627B2 (en)||2001-12-31||2010-03-07||Apparatus and method for controlling data transmission|
|Publication Number||Publication Date|
|CA2366397A1 true CA2366397A1 (en)||2003-06-30|
Family Applications (1)
|Application Number||Title||Priority Date||Filing Date|
|CA 2366397 Abandoned CA2366397A1 (en)||2001-12-31||2001-12-31||An interface for data transfer between integrated circuits|
Country Status (2)
|US (2)||US7751418B2 (en)|
|CA (1)||CA2366397A1 (en)|
Families Citing this family (92)
|Publication number||Priority date||Publication date||Assignee||Title|
|US7177658B2 (en)||2002-05-06||2007-02-13||Qualcomm, Incorporated||Multi-media broadcast and multicast service (MBMS) in a wireless communications system|
|US7051127B2 (en) *||2002-05-10||2006-05-23||Hewlett-Packard Development Company, L.P.||Method and apparatus for selectively providing data pre-emphasis based upon data content history|
|US8194770B2 (en)||2002-08-27||2012-06-05||Qualcomm Incorporated||Coded MIMO systems with selective channel inversion applied per eigenmode|
|US7324429B2 (en)||2002-10-25||2008-01-29||Qualcomm, Incorporated||Multi-mode terminal in a wireless MIMO system|
|US8218609B2 (en)||2002-10-25||2012-07-10||Qualcomm Incorporated||Closed-loop rate control for a multi-channel communication system|
|US7002900B2 (en)||2002-10-25||2006-02-21||Qualcomm Incorporated||Transmit diversity processing for a multi-antenna communication system|
|US20040081131A1 (en)||2002-10-25||2004-04-29||Walton Jay Rod||OFDM communication system with multiple OFDM symbol sizes|
|US8170513B2 (en)||2002-10-25||2012-05-01||Qualcomm Incorporated||Data detection and demodulation for wireless communication systems|
|US8570988B2 (en)||2002-10-25||2013-10-29||Qualcomm Incorporated||Channel calibration for a time division duplexed communication system|
|US8208364B2 (en)||2002-10-25||2012-06-26||Qualcomm Incorporated||MIMO system with multiple spatial multiplexing modes|
|US7986742B2 (en)||2002-10-25||2011-07-26||Qualcomm Incorporated||Pilots for MIMO communication system|
|US8134976B2 (en)||2002-10-25||2012-03-13||Qualcomm Incorporated||Channel calibration for a time division duplexed communication system|
|US8169944B2 (en)||2002-10-25||2012-05-01||Qualcomm Incorporated||Random access for wireless multiple-access communication systems|
|US8320301B2 (en)||2002-10-25||2012-11-27||Qualcomm Incorporated||MIMO WLAN system|
|US7680944B1 (en) *||2003-02-28||2010-03-16||Comtrol Corporation||Rapid transport service in a network to peripheral device servers|
|US7903685B2 (en) *||2003-06-03||2011-03-08||Starent Networks Llc||System and method for reformatting data|
|US8694869B2 (en) *||2003-08-21||2014-04-08||QUALCIMM Incorporated||Methods for forward error correction coding above a radio link control layer and related apparatus|
|US7318187B2 (en)||2003-08-21||2008-01-08||Qualcomm Incorporated||Outer coding methods for broadcast/multicast content and related apparatus|
|US8804761B2 (en) *||2003-08-21||2014-08-12||Qualcomm Incorporated||Methods for seamless delivery of broadcast and multicast content across cell borders and/or between different transmission schemes and related apparatus|
|US9473269B2 (en)||2003-12-01||2016-10-18||Qualcomm Incorporated||Method and apparatus for providing an efficient control channel structure in a wireless communication system|
|US20070110229A1 (en) *||2004-02-25||2007-05-17||Ternarylogic, Llc||Ternary and Multi-Value Digital Signal Scramblers, Descramblers and Sequence of Generators|
|US7643632B2 (en) *||2004-02-25||2010-01-05||Ternarylogic Llc||Ternary and multi-value digital signal scramblers, descramblers and sequence generators|
|JP4260688B2 (en) *||2004-06-09||2009-04-30||富士通株式会社||Data transmission device, data transmission / reception system, data transmission device control method, and data transmission / reception system control method|
|KR100567309B1 (en) *||2004-06-15||2006-04-04||삼성전자주식회사||Method for increasing bus usage efficiency by using received data header error check|
|JP4384668B2 (en)||2004-09-13||2009-12-16||パナソニック株式会社||Automatic retransmission request control system and retransmission method in MIMO-OFDM system|
|US7444582B1 (en) *||2004-10-27||2008-10-28||Marvell International Ltd.||Architecture and control of reed-solomon error-correction decoding|
|US7545272B2 (en)||2005-02-08||2009-06-09||Therasense, Inc.||RF tag on test strips, test strip vials and boxes|
|KR20060095225A (en) *||2005-02-28||2006-08-31||삼성전자주식회사||Apparatus for transmitting hs-dsch in w-cdma system|
|CN1832391A (en) *||2005-03-11||2006-09-13||松下电器产业株式会社||Adaptive retransmit method and equipment in multi-antenna communication system|
|US7466749B2 (en)||2005-05-12||2008-12-16||Qualcomm Incorporated||Rate selection with margin sharing|
|US8358714B2 (en)||2005-06-16||2013-01-22||Qualcomm Incorporated||Coding and modulation for multiple data streams in a communication system|
|US8090897B2 (en)||2006-07-31||2012-01-03||Google Inc.||System and method for simulating an aspect of a memory circuit|
|US8359187B2 (en)||2005-06-24||2013-01-22||Google Inc.||Simulating a different number of memory circuit devices|
|US7609567B2 (en)||2005-06-24||2009-10-27||Metaram, Inc.||System and method for simulating an aspect of a memory circuit|
|WO2007002324A2 (en)||2005-06-24||2007-01-04||Metaram, Inc.||An integrated memory core and memory interface circuit|
|US9507739B2 (en)||2005-06-24||2016-11-29||Google Inc.||Configurable memory circuit system and method|
|US8060774B2 (en)||2005-06-24||2011-11-15||Google Inc.||Memory systems and memory modules|
|US10013371B2 (en)||2005-06-24||2018-07-03||Google Llc||Configurable memory circuit system and method|
|US8041881B2 (en)||2006-07-31||2011-10-18||Google Inc.||Memory device with emulated characteristics|
|US9171585B2 (en)||2005-06-24||2015-10-27||Google Inc.||Configurable memory circuit system and method|
|US7379316B2 (en)||2005-09-02||2008-05-27||Metaram, Inc.||Methods and apparatus of stacking DRAMs|
|EP1924018B1 (en) *||2005-10-11||2013-01-09||Panasonic Corporation||Transmitting apparatus and transmitting method|
|US7424664B2 (en) *||2005-10-17||2008-09-09||Faraday Technology Corp.||Duplicate detection circuit for receiver|
|KR101150611B1 (en) *||2005-10-21||2012-06-08||삼성전자주식회사||Apparatus and method for transmitting and receving of packet data using harq in a wireless communication system|
|US7770088B2 (en) *||2005-12-02||2010-08-03||Intel Corporation||Techniques to transmit network protocol units|
|US7730382B2 (en) *||2005-12-02||2010-06-01||Beceem Communications Inc.||Method and system for managing memory in a communication system using hybrid automatic repeat request (HARQ)|
|KR100672313B1 (en) *||2005-12-12||2007-01-24||엘지전자 주식회사||The display apparatus having electronic album function and method thereof|
|US8089795B2 (en)||2006-02-09||2012-01-03||Google Inc.||Memory module with memory stack and interface with enhanced capabilities|
|US9632929B2 (en)||2006-02-09||2017-04-25||Google Inc.||Translating an address associated with a command communicated between a system and memory circuits|
|US9542352B2 (en)||2006-02-09||2017-01-10||Google Inc.||System and method for reducing command scheduling constraints of memory circuits|
|US7697529B2 (en)||2006-02-28||2010-04-13||Cisco Technology, Inc.||Fabric channel control apparatus and method|
|KR100913904B1 (en) *||2006-04-14||2009-08-26||삼성전자주식회사||Method and apparatus for performing automatic retransmission request in mobile telecommunication system|
|US20080028136A1 (en)||2006-07-31||2008-01-31||Schakel Keith R||Method and apparatus for refresh management of memory modules|
|US8327104B2 (en)||2006-07-31||2012-12-04||Google Inc.||Adjusting the timing of signals associated with a memory system|
|US7386656B2 (en)||2006-07-31||2008-06-10||Metaram, Inc.||Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit|
|US7724589B2 (en)||2006-07-31||2010-05-25||Google Inc.||System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits|
|US8077535B2 (en)||2006-07-31||2011-12-13||Google Inc.||Memory refresh apparatus and method|
|US8209479B2 (en)||2007-07-18||2012-06-26||Google Inc.||Memory circuit system and method|
|US8244971B2 (en)||2006-07-31||2012-08-14||Google Inc.||Memory circuit system and method|
|US8796830B1 (en)||2006-09-01||2014-08-05||Google Inc.||Stackable low-profile lead frame package|
|KR100837802B1 (en)||2006-09-13||2008-06-13||주식회사 하이닉스반도체||Semiconductor Memory Apparatus with Error Detection of Data Input and Output|
|US20080082763A1 (en)||2006-10-02||2008-04-03||Metaram, Inc.||Apparatus and method for power management of memory circuits by a system or component thereof|
|US8055833B2 (en)||2006-10-05||2011-11-08||Google Inc.||System and method for increasing capacity, performance, and flexibility of flash storage|
|US8397013B1 (en)||2006-10-05||2013-03-12||Google Inc.||Hybrid memory module|
|US8130560B1 (en)||2006-11-13||2012-03-06||Google Inc.||Multi-rank partial width memory modules|
|US8705344B2 (en)||2006-11-14||2014-04-22||Cisco Technology, Inc.||Graceful failover of a principal link in a fiber-channel fabric|
|JP4455613B2 (en) *||2007-05-28||2010-04-21||株式会社東芝||Communication terminal|
|US7830880B2 (en) *||2007-08-21||2010-11-09||Cisco Technology, Inc.||Selective build fabric (BF) and reconfigure fabric (RCF) flooding|
|US8080874B1 (en)||2007-09-14||2011-12-20||Google Inc.||Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween|
|US8111566B1 (en)||2007-11-16||2012-02-07||Google, Inc.||Optimal channel design for memory devices for providing a high-speed memory interface|
|US8081474B1 (en)||2007-12-18||2011-12-20||Google Inc.||Embossed heat spreader|
|US8438328B2 (en)||2008-02-21||2013-05-07||Google Inc.||Emulation of abstracted DIMMs using abstracted DRAMs|
|JP2009239449A (en) *||2008-03-26||2009-10-15||Nec Electronics Corp||Precise synchronization type network device, network system, and frame transfer method|
|US7701977B2 (en) *||2008-04-10||2010-04-20||Lsi Corporation||Method and apparatus to align and standardize packet based parallel interfaces|
|IL192140D0 (en) *||2008-06-12||2009-02-11||Ethos Networks Ltd||Method and system for transparent lan services in a packet network|
|US8386722B1 (en)||2008-06-23||2013-02-26||Google Inc.||Stacked DIMM memory interface|
|US8335894B1 (en)||2008-07-25||2012-12-18||Google Inc.||Configurable memory system with interface circuit|
|US20100077211A1 (en) *||2008-09-24||2010-03-25||Apple Inc.||Bit-error rate tester with pattern generation|
|CN102349261B (en) *||2009-03-12||2014-06-04||富士通株式会社||Communication device and packet synchronization method|
|EP2441007A1 (en)||2009-06-09||2012-04-18||Google, Inc.||Programming of dimm termination resistance values|
|JP2011023897A (en) *||2009-07-14||2011-02-03||Toshiba Corp||Semiconductor integrated device|
|US8472437B2 (en) *||2010-02-15||2013-06-25||Texas Instruments Incorporated||Wireless chip-to-chip switching|
|US8972995B2 (en) *||2010-08-06||2015-03-03||Sonics, Inc.||Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads|
|KR101763426B1 (en) *||2010-08-20||2017-07-31||삼성전자주식회사||Device and method for controlling external device|
|US8396178B1 (en) *||2010-08-31||2013-03-12||Siklu Communication ltd.||Distributing clock associated with a wired data connection over wireless interfaces using frequency correction at the transmitter side|
|CN103229155B (en)||2010-09-24||2016-11-09||德克萨斯存储系统股份有限公司||high-speed memory system|
|US9680650B2 (en) *||2013-08-23||2017-06-13||Qualcomm Incorporated||Secure content delivery using hashing of pre-coded packets|
|EP3079324A4 (en) *||2013-12-31||2016-12-07||Huawei Tech Co Ltd||Scrambling method and scrambling apparatus|
|DE102014210505A1 (en) *||2014-06-03||2015-12-03||Robert Bosch Gmbh||Transmission unit with test function|
|US9785570B2 (en) *||2015-03-09||2017-10-10||Samsung Electronics Co., Ltd.||Memory devices and modules|
|US9872068B2 (en) *||2015-07-24||2018-01-16||Nxp Usa, Inc.||Interconnecting system, video signal transmitter and video signal receiver for transmitting an N-symbol data signal|
|US9871988B2 (en) *||2015-07-24||2018-01-16||Nxp Usa, Inc.||Interconnecting system, video signal transmitter and video signal receiver for transmitting an N-symbol data signal|
Family Cites Families (7)
|Publication number||Priority date||Publication date||Assignee||Title|
|JP3156623B2 (en) *||1997-01-31||2001-04-16||日本電気株式会社||Fiber Channel fabric|
|US7012896B1 (en) *||1998-04-20||2006-03-14||Alcatel||Dedicated bandwidth data communication switch backplane|
|US6351466B1 (en) *||1998-05-01||2002-02-26||Hewlett-Packard Company||Switching systems and methods of operation of switching systems|
|JP3214490B2 (en) *||1999-01-06||2001-10-02||日本電気株式会社||Packet-switched network|
|US6671271B1 (en) *||1999-06-03||2003-12-30||Fujitsu Network Communications, Inc.||Sonet synchronous payload envelope pointer control system|
|JP3732989B2 (en) *||2000-01-12||2006-01-11||富士通株式会社||Packet switch device and scheduling control method|
|US7221678B1 (en) *||2001-10-01||2007-05-22||Advanced Micro Devices, Inc.||Method and apparatus for routing packets|
Also Published As
|Publication number||Publication date|
|DE60122019T2 (en)||Method and devices for data transfer|
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|KR100860883B1 (en)||Communication interface for an electronic device|
|US8223796B2 (en)||Graphics multi-media IC and method of its operation|
|US8042743B2 (en)||IC card comprising a main device and an additional device|
|US5778195A (en)||PC card|
|CA2236188C (en)||Firmware controlled transmit datapath for high-speed packet switches|
|DE50204684D1 (en)||Arrangement and method for data transmission in a multiple input multiple output radio communication system|
|EP1213657A2 (en)||Dual interface serial bus|
|EP1101329B1 (en)||Bridge module|
|WO2000039679A3 (en)||Method and apparatus for balancing workloads among paths in a multi-path computer system|
|TW200420096A (en)||Providing routing information in a communication system|
|SG131736A1 (en)||Terminal device and method of controlling transmission in the terminal device|
|WO2008021530A3 (en)||Network direct memory access|
|WO2005106625A3 (en)||Selecting input/output devices to control power consumption of a computer system|
|CA2405695A1 (en)||Method for controlling an elevator|
|WO2002058330A3 (en)||Digital baseband system|
|NZ534192A (en)||Device and method for restricting content access and storage|
|TW511085B (en)||High-speed memory system|
|WO2001065807A3 (en)||Method for facilitating electronic communications|
|WO2003071412A3 (en)||Network data storage-related operations|
|CA2497446A1 (en)||Redundancy in voice and data communications systems|
|WO2006023993A3 (en)||Data storage system|
|EP0855643A4 (en)||Terminal apparatus|