JP5063135B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims description 58
- 150000004767 nitrides Chemical class 0.000 claims description 41
- 125000006850 spacer group Chemical group 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000000126 substance Substances 0.000 claims description 21
- 238000005498 polishing Methods 0.000 claims description 19
- 239000002002 slurry Substances 0.000 claims description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021485 fumed silica Inorganic materials 0.000 claims description 4
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims 3
- 239000000725 suspension Substances 0.000 claims 3
- 238000002347 injection Methods 0.000 claims 2
- 239000007924 injection Substances 0.000 claims 2
- 239000002245 particle Substances 0.000 claims 2
- 239000006061 abrasive grain Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 14
- 230000002093 peripheral effect Effects 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 230000006641 stabilisation Effects 0.000 description 9
- 238000011105 stabilization Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 238000000635 electron micrograph Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- -1 spacer nitride Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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Description
図3A〜図3Fは、本発明の第1の実施形態に係る半導体素子の製造方法を説明するための断面図である。
次いで、窒化膜23を平坦化停止膜として平坦化させる第2平坦化処理を行う。これは、高選択性スラリー(high selectivity slurry)を用いた化学的機械的研磨処理である。ここで、高選択性スラリーは、6pH〜8pHの範囲のCeO2、第1酸化膜:窒化膜の選択比を50〜100:1として行う。このとき、厚さ20Å〜200Åの範囲の窒化膜23が除去される。
図4A及び図4Bは、本発明の第2の実施形態に係る半導体素子の微細パターンの形成方法を説明するための断面図である。
22、32 ポリシリコン膜(第1ハードマスク層)
23、33 窒化膜(第1パッド層)
24、34 第1酸化膜(第2パッド層)
25 フォトレジストパターン
26、36 スペーサ
27、37 第2酸化膜(第2ハードマスク層)
Claims (13)
- 被エッチング層上に、第1ハードマスク、第1パッド層、及び第2パッド層の順に積層された複数のエッチングマスクパターンを形成する第1ステップと、
前記エッチングマスクパターンの両側壁に、前記第1パッド層と同じ物質からなるスペーサを形成する第2ステップと、
前記エッチングマスクパターン間を埋め込むまで、全面に、前記第1ハードマスクとは異なり、且つ、前記第2パッド層と同じ物質からなる第2ハードマスクを形成する第3ステップと、
前記第1パッド層が露出するまで、前記第2ハードマスクを平坦化させる第4ステップと、
前記第1パッド層及び前記スペーサを除去する第5ステップと、
残留する前記第1ハードマスク及び第2ハードマスクをエッチングバリアとして、前記被エッチング層をエッチングする第6ステップと
を含むことを特徴とする半導体素子の製造方法。 - 前記第2ハードマスクを平坦化させる前記第4ステップが、
前記第2パッド層の一部が残留する範囲で平坦化処理を行う第1平坦化ステップと、
該第1平坦化ステップの後に、前記第1パッド層を平坦化停止膜として平坦化処理を行う第2平坦化ステップと
を含むことを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記第2パッド層が、酸化膜又はHDP(High Density Plasma)酸化膜で形成され、
前記第1パッド層が、窒化膜で形成されることを特徴とする請求項2に記載の半導体素子の製造方法。 - 前記第1平坦化ステップが、低選択性スラリーを用いた化学的機械的研磨を行うステップであり、
前記第2平坦化ステップが、高選択性スラリーを用いた化学的機械的研磨を行うステップであることを特徴とする請求項2に記載の半導体素子の製造方法。 - 前記低選択性スラリーを用いた前記化学的機械的研磨が、研磨粒子としてヒュームドシリカを含み、懸濁液の水素イオン濃度が10pH〜14pHの範囲のスラリーを用いて、スラリーの注入割合が150mL/min〜250mL/minの範囲で行われ、
前記高選択性スラリーを用いた前記化学的機械的研磨が、研磨粒子としてCeO 2 を含み、懸濁液の水素イオン濃度が6pH〜8pHの範囲であり、第2パッド層:第1パッド層の選択比が50〜100:1であるスラリーを用いて行われることを特徴とする請求項4に記載の半導体素子の製造方法。 - 前記第1ハードマスクが、ポリシリコン膜で形成され、
前記第2ハードマスクが、酸化膜で形成されることを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記第1パッド層及び前記スペーサを除去する前記第5ステップが、リン酸(H3PO4)を用いて、10分〜30分間行われる洗浄処理と、5分〜30分間行われるhot−SC1(NH4OH:H2O2:H2O)洗浄処理とを含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記窒化膜が、20Å〜200Åの範囲の厚さで除去されることを特徴とする請求項3に記載の半導体素子の製造方法。
- 被エッチング層上に、第1ハードマスク、第1パッド層、及び第2パッド層の順に積層された複数のエッチングマスクパターンを形成する第1ステップと、
前記エッチングマスクパターンの両側壁に、前記第1パッド層と同じ物質からなるスペーサを形成する第2ステップと、
前記エッチングマスクパターン間を埋め込むまで、全面に、前記第1ハードマスクとは異なり、且つ、前記第2パッド層と同じ物質からなる第2ハードマスクを形成する第3ステップと、
前記第2パッド層が露出するまで、前記第2ハードマスクを平坦化させる第4ステップと、
前記第1パッド層が露出するまで、前記第2パッド層及び前記第2ハードマスクの一部を除去する第5ステップと、
前記第1パッド層及び前記スペーサを除去する第6ステップと、
残留する前記第1ハードマスク及び前記第2ハードマスクをエッチングバリアとして、前記被エッチング層をエッチングする第7ステップと
を含むことを特徴とする半導体素子の製造方法。 - 前記第2ハードマスクを平坦化させる前記第4ステップが、研磨粒子としてヒュームドシリカを含み、懸濁液の水素イオン濃度が10pH〜14pHの範囲のスラリーを用いて、スラリーの注入割合が150mL/min〜250mL/minの範囲で、化学的機械的研磨により行われることを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記第2パッド層が、酸化膜又はHDP酸化膜で形成され、
前記第1パッド層が、窒化膜で形成されることを特徴とする請求項9に記載の半導体素子の製造方法。 - 前記第1パッド層、前記第2パッド層、及び前記スペーサを除去する前記第5及び第6ステップが、同じチャンバ内で同時に行われることを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記第1ハードマスクが、ポリシリコン膜で形成され、
前記第2ハードマスクが、酸化膜で形成されることを特徴とする請求項9に記載の半導体素子の製造方法。
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