JP2010087298A - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 80
- 238000012545 processing Methods 0.000 claims abstract description 34
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 238000013461 design Methods 0.000 claims description 49
- 238000005530 etching Methods 0.000 description 59
- 239000007789 gas Substances 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 8
- 238000005259 measurement Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】 下地膜100上に第一の膜101及び第二の膜102を順に形成し、第二の膜102を加工して第二のパターン104を形成し、第二のパターン104をマスクに第一の膜101を加工して第一のパターン105を形成し、第二のパターン104を除去した後、下地膜上及び第一のパターン105上に第三の膜106を堆積し、第三の膜106を加工して第一のパターン105側壁に第三の側壁パターン107を形成し、第一のパターン105を除去した後、第三の側壁パターン107をマスクに下地膜を加工し、下地膜にパターン108を形成する半導体装置の製造方法において、下地膜100に形成するパターン108の寸法が下地膜100に形成するパターン108のスペース寸法よりも小さくなるように、下地膜にパターン108を形成することを特徴とする。
【選択図】図1
Description
101:第一の膜
102:レジスト膜(第二の膜)
104:レジストパターン(第二のパターン)
105:第一のパターン
106:第三の膜
107:第三の側壁パターン
110:第四のパターン
l1:マスクパターン寸法
l2:レジストパターン(第二のパターン)寸法
l3:第一のパターン寸法
l4:第三の膜の膜厚
l5:第三の側壁パターン寸法
l8:第四のパターン寸法
Claims (5)
- 下地膜上に第一の膜及び第二の膜を順に形成する工程と、
前記第二の膜を加工して第二のパターンを形成する工程と、
前記第二のパターンをマスクに前記第一の膜を加工して第一のパターンを形成する工程と、
前記第二のパターンを除去した後、前記下地膜上及び前記第一のパターン上に第三の膜を堆積する工程と、
前記第三の膜を加工して前記第一のパターン側壁に第三の側壁パターンを形成する工程と、
前記第一のパターンを除去した後、前記第三の側壁パターンをマスクに前記下地膜を加工し、前記下地膜にパターンを形成する工程と、
を備えた半導体装置の製造方法において、
前記下地膜に形成するパターンの寸法が前記下地膜に形成するパターンのスペース寸法よりも小さくなるように、前記下地膜にパターンを形成することを特徴とする半導体装置の製造方法。 - 下地膜上に第一の膜及び第二の膜を順に形成する工程と、
前記第二の膜を加工して第二のパターンを形成する工程と、
前記第二のパターンをマスクに前記第一の膜を加工して第一のパターンを形成する工程と、
前記第二のパターンを除去した後、前記下地膜上及び前記第一のパターン上に第三の膜を堆積する工程と、
前記第三の膜を加工して前記第一のパターン側壁に第三の側壁パターンを形成する工程と、
前記側壁パターン間に露出する前記下地膜上に第四のパターンを埋め込み形成する工程と、
前記第三の側壁パターンを除去した後、前記第一及び前記第四のパターンをマスクに前記下地膜を加工し、前記下地膜にパターンを形成する工程と、
を備えた半導体装置の製造方法において、
前記下地膜に形成するパターンの寸法が前記下地膜に形成するパターンのスペース寸法よりも大きくなるように、前記下地膜にパターンを形成することを特徴とする半導体装置の製造方法。 - 前記第一のパターンを形成する工程の前に前記第二のパターンをスリミングする工程を更に備えたことを特徴とする請求項1または2記載の半導体装置の製造方法。
- 下地膜上に第一の膜及び第二の膜を順に形成する工程と、
前記第二の膜を加工して第二のパターンを形成する工程と、
前記第二のパターンをマスクに前記第一の膜を加工して第一のパターンを形成する工程と、
前記第二のパターンを除去した後、前記下地膜上及び前記第一のパターン上に第三の膜を堆積する工程と、
前記第三の膜を加工して前記第一のパターン側壁に第三の側壁パターンを形成する工程と、
前記第一のパターンを除去した後、前記第三の側壁パターンをマスクに前記下地膜を加工し、前記下地膜にパターンを形成する工程と、
を備えた半導体装置の製造方法における前記下地膜に形成するパターンの設計パターンの作成方法において、
前記下地膜に形成するパターンの寸法が前記下地膜に形成するパターンのスペース寸法よりも小さくなるように、前記設計パターンを作成することを特徴とする半導体装置の製造方法。 - 下地膜上に第一の膜及び第二の膜を順に形成する工程と、
前記第二の膜を加工して第二のパターンを形成する工程と、
前記第二のパターンをマスクに前記第一の膜を加工して第一のパターンを形成する工程と、
前記第二のパターンを除去した後、前記下地膜上及び前記第一のパターン上に第三の膜を堆積する工程と、
前記第三の膜を加工して前記第一のパターン側壁に第三の側壁パターンを形成する工程と、
前記側壁パターン間に露出する前記下地膜上に第四のパターンを埋め込み形成する工程と、
前記第三の側壁パターンを除去した後、前記第一及び前記第四のパターンをマスクに前記下地膜を加工し、前記下地膜にパターンを形成する工程と、
を備えた半導体装置の製造方法における前記下地膜に形成するパターンの設計パターンの作成方法において、
前記下地膜に形成するパターンの寸法が前記下地膜に形成するパターンのスペース寸法よりも大きくなるように、前記設計パターンを作成することを特徴とする半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2008255635A JP2010087298A (ja) | 2008-09-30 | 2008-09-30 | 半導体装置の製造方法 |
US12/549,691 US20100081283A1 (en) | 2008-09-30 | 2009-08-28 | Method for manufacturing semiconductor device |
KR1020090092180A KR20100036985A (ko) | 2008-09-30 | 2009-09-29 | 반도체 장치를 제조하기 위한 방법 |
KR1020110118038A KR20110138201A (ko) | 2008-09-30 | 2011-11-14 | 반도체 장치를 제조하기 위한 방법 |
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JP (1) | JP2010087298A (ja) |
KR (2) | KR20100036985A (ja) |
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KR101855939B1 (ko) * | 2011-09-23 | 2018-05-09 | 엘지전자 주식회사 | 영상표시장치의 동작 방법 |
Citations (5)
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JPH03108329A (ja) * | 1989-09-21 | 1991-05-08 | Nec Corp | Mos型電界効果トランジスタの製造方法 |
JP2006303022A (ja) * | 2005-04-18 | 2006-11-02 | Toshiba Corp | 半導体装置の製造方法 |
JP2007235133A (ja) * | 2006-02-27 | 2007-09-13 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
WO2007133442A1 (en) * | 2006-05-10 | 2007-11-22 | Lam Research Corporation | Pitch reduction |
JP2007335763A (ja) * | 2006-06-16 | 2007-12-27 | Toshiba Corp | 半導体装置及びその製造方法 |
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EP0394597A1 (en) * | 1989-04-28 | 1990-10-31 | International Business Machines Corporation | Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns |
US6063688A (en) * | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
US6867116B1 (en) * | 2003-11-10 | 2005-03-15 | Macronix International Co., Ltd. | Fabrication method of sub-resolution pitch for integrated circuits |
JP4936659B2 (ja) * | 2004-12-27 | 2012-05-23 | 株式会社東芝 | 半導体装置の製造方法 |
US7393789B2 (en) * | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US8158333B2 (en) * | 2006-04-11 | 2012-04-17 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
JP4996155B2 (ja) * | 2006-07-18 | 2012-08-08 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2008233383A (ja) * | 2007-03-19 | 2008-10-02 | Toshiba Corp | パターン作成方法、パターン作成プログラム、マスクの製造方法、および半導体装置の製造方法 |
US8232212B2 (en) * | 2008-07-11 | 2012-07-31 | Applied Materials, Inc. | Within-sequence metrology based process tuning for adaptive self-aligned double patterning |
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JPH03108329A (ja) * | 1989-09-21 | 1991-05-08 | Nec Corp | Mos型電界効果トランジスタの製造方法 |
JP2006303022A (ja) * | 2005-04-18 | 2006-11-02 | Toshiba Corp | 半導体装置の製造方法 |
JP2007235133A (ja) * | 2006-02-27 | 2007-09-13 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
WO2007133442A1 (en) * | 2006-05-10 | 2007-11-22 | Lam Research Corporation | Pitch reduction |
JP2009536787A (ja) * | 2006-05-10 | 2009-10-15 | ラム リサーチ コーポレーション | ピッチの低減 |
JP2007335763A (ja) * | 2006-06-16 | 2007-12-27 | Toshiba Corp | 半導体装置及びその製造方法 |
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KR20100036985A (ko) | 2010-04-08 |
US20100081283A1 (en) | 2010-04-01 |
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