JP5047475B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 49
- 229920005591 polysilicon Polymers 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 238000003860 storage Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000010955 niobium Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000007796 conventional method Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
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- B02C18/00—Disintegrating by knives or other cutting or tearing members which chop material into fragments
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Food Science & Technology (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Description
図1に示されているように、半導体基板10の上部に活性領域を定義する素子分離膜20を形成する。
以後、前記感光膜パターン(図示せず)を除去する。
(a)半導体基板の上部に、不純物を含み、コンタクトプラグと連結されるためのポリシリコン層を形成する段階と、
(b)素子分離領域に予定された部分の前記ポリシリコン層と所定の厚さの半導体基板をエッチングしてトレンチを形成する段階と、
(c)前記トレンチが埋め込まれるよう素子分離用絶縁膜を形成した後、前記ポリシリコン層が露出されるまで前記素子分離用絶縁膜を平坦化して素子分離膜を形成する段階と、
(d)前記素子分離膜及び前記ポリシリコン層上にゲート用エッチング停止膜を形成する段階と、
(e)ゲート予定領域の前記ゲート用エッチング停止膜、前記ポリシリコン層及び所定の厚さの前記半導体基板をエッチングしてゲート用トレンチを形成し、前記ポリシリコン層をビットラインコンタクト予定領域のポリシリコン層と貯蔵電極コンタクト予定領域のポリシリコン層とに分離する段階と、
(f)前記ゲート用トレンチを含む全体表面の上部にゲート酸化膜を形成したあと、前記ゲート用トレンチを埋め込むゲート電極層及びハードマスク層を順次形成する段階と、
(g)前記ゲート用エッチング停止膜が露出されるまで全体の表面を平坦化エッチングしてゲートを形成する段階と
を含み、
(h)前記ポリシリコン層に熱処理を行う段階が、前記(a)段階の後、且つ、前記(d)段階の前の段階間の何れかに含まれる
ことを特徴とする。
図5〜図13は、本発明の実施の形態に係る半導体素子の製造方法を示す断面図等である。
以後、後続する工程でソース/ドレイン領域(図示せず)を形成するため不純物を含むプラグ用ポリシリコン層180−1に熱処理工程(図示せず)を更に行なうことができる。
以後、ゲート用エッチング停止膜117の上部に感光膜(図示せず)を塗布し、これを露光及び現像してゲート予定領域を露出する第2の感光膜パターン119を形成する。
次に、ゲート165を含む全体表面の上部に第1の絶縁膜163を形成する。
以後、ビットラインマスク(図示せず)をエッチングマスクとして前記ビットラインコンタクトプラグ用ポリシリコン層(図示せず)をエッチングしてビットラインコンタクト予定領域のプラグ用ポリシリコン層180−1と連結されるビットラインコンタクトプラグ167を形成する。
以後、貯蔵電極コンタクト予定領域の第2の絶縁膜169、第1の絶縁膜163及びゲート用エッチング停止膜117を順次エッチングして貯蔵電極コンタクトホール(図示せず)を形成する。
以後、第2の絶縁膜169が露出されるまで全体表面の上部をエッチバックやCMP方法でエッチングし、貯蔵電極コンタクト予定領域のプラグ用ポリシリコン層180−1と連結される貯蔵電極コンタクトプラグ173を形成する。
以後、キャパシタ用下部電極層パターン183を含む全体表面の上部にキャパシタ用誘電膜185及びキャパシタ用上部電極層187を順次積層してキャパシタ(図示せず)を形成する。
以後、半導体素子の製造工程は従来の技術と同一であってもよい。
113 第1の感光膜パターン
115 トレンチ
117 ゲート用エッチング停止膜
119 第2の感光膜パターン
120 素子分離膜
130 ゲート酸化膜
150 ゲート電極層
160 ハードマスク層
163 第1の絶縁膜
165 ゲート
167 ビットラインコンタクトプラグ
169 第2の絶縁膜
173 貯蔵電極コンタクトプラグ
180、180−1 プラグ用ポリシリコン層
183 キャパシタ用下部電極層パターン
185 キャパシタ用誘電膜
187 キャパシタ用上部電極層
Claims (7)
- (a)半導体基板の上部に、不純物を含み、コンタクトプラグと連結されるためのポリシリコン層を形成する段階と、
(b)素子分離領域に予定された部分の前記ポリシリコン層と所定の厚さの半導体基板をエッチングしてトレンチを形成する段階と、
(c)前記トレンチが埋め込まれるよう素子分離用絶縁膜を形成した後、前記ポリシリコン層が露出されるまで前記素子分離用絶縁膜を平坦化して素子分離膜を形成する段階と、
(d)前記素子分離膜及び前記ポリシリコン層上にゲート用エッチング停止膜を形成する段階と、
(e)ゲート予定領域の前記ゲート用エッチング停止膜、前記ポリシリコン層及び所定の厚さの前記半導体基板をエッチングしてゲート用トレンチを形成し、前記ポリシリコン層をビットラインコンタクト予定領域のポリシリコン層と貯蔵電極コンタクト予定領域のポリシリコン層とに分離する段階と、
(f)前記ゲート用トレンチを含む全体表面の上部にゲート酸化膜を形成したあと、前記ゲート用トレンチを埋め込むゲート電極層及びハードマスク層を順次形成する段階と、
(g)前記ゲート用エッチング停止膜が露出されるまで全体の表面を平坦化エッチングしてゲートを形成する段階と
を含み、
(h)前記ポリシリコン層に熱処理を行う段階が、前記(a)段階の後、且つ、前記(d)段階の前の段階間の何れかに含まれる
ことを特徴とする半導体素子の製造方法。 - 前記(a)段階の不純物は燐(P)又は砒素(As)であることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記(a)段階は、
半導体基板の上部にポリシリコン層を形成する段階と、
前記ポリシリコン層に前記不純物を注入する段階とを含むことを特徴とする請求項2に記載の半導体素子の製造方法。 - 前記(a)段階は、
Siソースガスと前記不純物のソースガスを利用して前記ポリシリコン層を形成する段階を含むことを特徴とする請求項2に記載の半導体素子の製造方法。 - 前記ゲート電極層は、ゲートポリシリコン層及びゲート金属層を含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ゲート金属層はタングステン(W)、コバルト(Co)、タンタル(Ta)、モリブデン(Mo)、ハフニウム(Hf)、ニオブ(Nb)、バナジウム(V)、ジルコニウム(Zr)、前記それぞれの金属シリサイド及びこれらの組合せでなる群から選択されたいずれか一つの物質を含むことを特徴とする請求項5に記載の半導体素子の製造方法。
- 前記(g)段階の後、前記ゲートを含む全体表面の上部に第1の絶縁膜を形成する段階と、
前記ビットラインコンタクト予定領域に、当該ビットラインコンタクト予定領域の前記ポリシリコン層と連結されるビットラインコンタクトプラグを形成する段階と、
前記ビットラインコンタクトプラグを含む全体表面の上部に第2の絶縁膜を形成する段階と、
前記貯蔵電極コンタクト予定領域に、当該貯蔵電極コンタクト予定領域の前記ポリシリコン層と連結される貯蔵電極コンタクトプラグを形成する段階と、
全体表面の上部にキャパシタ用下部電極層を形成してパターニングし、前記貯蔵電極コンタクトプラグの上部にキャパシタ用下部電極層パターンを形成する段階と、
全体表面の上部にキャパシタ用誘電層及びキャパシタ用上部電極層を順次蒸着してキャパシタを形成する段階と
を更に含むことを特徴とする請求項1に記載の半導体素子の製造方法。
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KR101374335B1 (ko) * | 2007-09-10 | 2014-03-17 | 삼성전자주식회사 | 국부적으로 두꺼운 유전막을 갖는 리세스 채널트랜지스터의 제조방법 및 관련된 소자 |
JP2009182114A (ja) | 2008-01-30 | 2009-08-13 | Elpida Memory Inc | 半導体装置およびその製造方法 |
CN101572224B (zh) * | 2008-04-30 | 2011-05-04 | 中芯国际集成电路制造(北京)有限公司 | 多晶硅浮栅的制作方法以及半导体器件的制作方法 |
KR101051577B1 (ko) | 2009-06-30 | 2011-07-22 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 형성 방법 |
US8507996B2 (en) * | 2009-09-22 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Block contact plugs for MOS devices |
KR101095802B1 (ko) * | 2010-01-07 | 2011-12-21 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
KR101164974B1 (ko) * | 2010-12-15 | 2012-07-12 | 에스케이하이닉스 주식회사 | 매립게이트를 구비한 반도체 장치 제조방법 |
KR102188883B1 (ko) * | 2013-12-13 | 2020-12-14 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
CN108257957A (zh) * | 2016-12-29 | 2018-07-06 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
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JPH06318680A (ja) * | 1993-05-10 | 1994-11-15 | Nec Corp | 半導体記憶装置およびその製造方法 |
JPH07161977A (ja) * | 1993-12-06 | 1995-06-23 | Hitachi Ltd | 半導体装置とその製造方法 |
KR0136995B1 (ko) * | 1994-09-08 | 1998-04-24 | 김주용 | 비휘발성메모리셀의제조방법 |
JP2751909B2 (ja) * | 1996-02-26 | 1998-05-18 | 日本電気株式会社 | 半導体装置の製造方法 |
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JP3295393B2 (ja) * | 1998-10-26 | 2002-06-24 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6204128B1 (en) * | 1998-10-26 | 2001-03-20 | Matsushita Electronics Corporation | Method for fabricating semiconductor device |
US6303448B1 (en) * | 1998-11-05 | 2001-10-16 | Taiwan Semiconductor Manufacturing Company | Method for fabricating raised source/drain structures |
KR100370129B1 (ko) * | 2000-08-01 | 2003-01-30 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
KR100574487B1 (ko) * | 2002-07-05 | 2006-04-27 | 주식회사 하이닉스반도체 | 반도체소자의 mos 트랜지스터 제조방법 |
KR100835505B1 (ko) * | 2002-07-18 | 2008-06-04 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100539276B1 (ko) * | 2003-04-02 | 2005-12-27 | 삼성전자주식회사 | 게이트 라인을 포함하는 반도체 장치 및 이의 제조 방법 |
KR20040102720A (ko) * | 2003-05-29 | 2004-12-08 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
JP2005019584A (ja) | 2003-06-25 | 2005-01-20 | Sony Corp | 半導体装置および半導体装置の製造方法 |
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TW200634897A (en) | 2006-10-01 |
JP2006261625A (ja) | 2006-09-28 |
TWI261295B (en) | 2006-09-01 |
CN100576505C (zh) | 2009-12-30 |
DE102005026315B4 (de) | 2010-11-25 |
US20060211229A1 (en) | 2006-09-21 |
US7332397B2 (en) | 2008-02-19 |
KR100596833B1 (ko) | 2006-07-04 |
DE102005026315A1 (de) | 2006-09-21 |
CN1835208A (zh) | 2006-09-20 |
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