CN108257957A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN108257957A
CN108257957A CN201611246125.8A CN201611246125A CN108257957A CN 108257957 A CN108257957 A CN 108257957A CN 201611246125 A CN201611246125 A CN 201611246125A CN 108257957 A CN108257957 A CN 108257957A
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atom
substrate
diffusion barrier
source
semiconductor structure
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林哲平
詹电鍼
詹书俨
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to CN201611246125.8A priority Critical patent/CN108257957A/zh
Priority to US15/854,769 priority patent/US10608086B2/en
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Abstract

本发明公开一种半导体结构及其制作方法。该半导体结构包含有一基底，包含有至少一主动区定义于该基底上，至少一埋入式位线位于该主动区内的该基底内，一源/漏极区域，位于该至少一埋入式位线旁的该基底中，一扩散阻障区，位于该源/漏极区域顶部，且该扩散阻障区包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组，一介电层，位于该基底上，以及一接触结构，位于该介电层中，与该源/漏极区域电连接。

Description

半导体结构及其制作方法
技术领域
本发明涉及一种半导体结构及其制作方法，尤其是涉及一种包含有扩散阻障区的动态随机存取存储器元件及其制作方法。
背景技术
动态随机存取存储器(dynamic random access memory，以下简称为DRAM)是一种主要的挥发性(volatile)存储器，且是很多电子产品中不可或缺的关键元件。DRAM由数目庞大的存储单元(memory cell)聚集形成一阵列区，用来存储数据，而每一存储单元则由一金属氧化半导体(metal oxide semiconductor，以下简称为MOS)晶体管与一电容(capacitor)串联组成。
电容是通过存储电极(storage node)与形成于电极接触洞(node contact)中的导电结构电连接，并与MOS晶体管的漏极形成一位存取的通路，用于达到存储或输出数据的目的。随着DRAM集成度的提升，必须要减低DRAM存储单元中被电容所占据的面积，而为了使电容的电容量维持一个可以接受的数值，现有技术是采用堆叠电容的技术(stackedcapacitor)。堆叠电容的使用除了可以提供高电容量之外，也可降低每一个DRAM存储单元之间的相互干扰，还可对此种基本堆叠电容作多种形式的变化以提高表面积。
发明内容
本发明提供一种半导体结构，包含有一基底，包含有至少一主动区定义于该基底上，至少一埋入式位线位于该主动区内的该基底内，一源/漏极区域，位于该至少一埋入式位线旁的该基底中，一扩散阻障区，位于该源/漏极区域顶部，且该扩散阻障区包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组，一介电层，位于该基底上，以及一接触结构，位于该介电层中，与该源/漏极区域电连接。
本发明另提供一种半导体结构的制作方法，包含以下步骤：首先，提供一基底，包含有至少一主动区定义于该基底上，然后形成至少一埋入式位线于该主动区内的该基底内，接着形成一源/漏极区域于该至少一埋入式位线旁的该基底中，接下来形成一扩散阻障区于该源/漏极区域顶部，且该扩散阻障区包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组，之后形成一介电层于该基底上，以及形成一接触结构于该介电层中，该接触结构与该源/漏极区域电连接。
本发明的特征在于，在与存储节点接触电连接的接触插塞，以及埋入式栅极(埋入式字符线)旁的源/漏极区域之间，额外形成形成一扩散阻障区。由于接触插塞可能包含掺杂磷原子的非晶硅层，因此在扩散阻障区内掺杂有例如碳原子等非三-五族原子，可以避免接触插塞内磷原子扩散至源/漏极区域内，进而影响电性。因此，本发明可以提升DRAM结构的良率与品质。
附图说明
图1～图9为本发明所提供的半导体元件的制作方法的一第一较佳实施例示意图，其中图1为上视图，而图2～图9则为剖视图。
主要元件符号说明
100 基底
102 存储区域(存储器区域)
104 周边区域
104D 晶体管元件
106 浅沟隔离结构
108 凹槽
110 晶体管
112 介电层
114 埋藏式栅极
116 绝缘层
118 源极/漏极区域
119 蚀刻停止层
120 第一绝缘层
126 凹槽
130 位线结构
132 位线接触插塞
134 位线
136 间隙壁
138 覆盖层
140 第二绝缘层
142 第二掩模图案
148 第二暴露部分
156 凹槽
158 扩散阻障区
160 存储节点接触
161 下半部
162 上半部
164 下电极
h 阶差
D1 第一方向
D2 第二方向
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的较佳实施例，并配合所附附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人皆应能理解其是指物件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本发明所公开的范围，在此容先叙明。
请参阅图1～图9，其为本发明所提供的半导体元件的制作方法的一第一较佳实施例示意图，其中图1为上视图，而图2～图9则为剖视图，图2为图1中沿着剖面线A-A’所得的剖视图。如图1与图2所示，本较佳实施例所提供的半导体元件的制作方法首先提供一基底100，基底100上至少定义有一存储区域102与一周边区域104，且存储区域102内形成有多个晶体管110。在本较佳实施例中，晶体管110较佳可包含动态随机存取存储器(dynamicrandom access memory，以下简称为DRAM)，但不限于此。
请参考图1与图2，在本发明的实施例中，晶体管110可通过以下步骤形成：首先，在存储区域102与周边区域104内形成多个浅沟隔离(shallow trench isolations，以下简称为STI)结构106，用以定义多个用以容置晶体管元件的主动区域，且用以提供这些主动区域之间的电性隔离。接下来，在基底100以及存储区域102内的STI结构106中形成多个凹槽108，并且在各凹槽108内形成覆盖其侧壁与底部的介电层112。之后在凹槽108内分别形成一埋入式栅极(buried gate)114，请注意此处的埋入式栅极也可以视为埋入式字符线(buried word line)，并且在形成埋入式栅极114之后，在各凹槽108内形成密封凹槽108的绝缘层116。之后，在埋入式栅极114两侧的基底100内形成源极/漏极区域118。值得注意的是，多个埋入式栅极114是沿一第一方向D1排列，并且每一个埋入式栅极114沿一第二方向D2延伸(图2中与纸面的垂直方向)，其中第一方向D1与第二方向D2彼此垂直。是以，在存储区域102内的基底100内形成上述晶体管110。然而，熟悉该项技术的人士应知，晶体管110可通过任何合适的制作工艺与步骤形成，故不限于此。熟悉该项技术的人士应知，为了缩短制作工艺时间与简化制作工艺，可在制作存储单元时结合周边电路的制作。因此可根据不同的要求，在完成晶体管110之后，更于周边区域104内形成具有适当功能的晶体管元件104D，随后可于基底100上形成一蚀刻停止层119，如图1所示。另外，熟悉该项技术的人士应知，晶体管110的源极/漏极区域118可与周边区域104内的晶体管元件104D的源极/漏极区域同时或分开制作，此处不予以赘述。
请继续参阅图1。在形成晶体管110以及晶体管元件104D之后，在基底100上形成一第一绝缘层120与多个形成于第一绝缘层内的位线结构130。第一绝缘层120包含有一第一绝缘材料，举例来说可以是氧化硅(SiO)，但不限于此。如图1所示，位线结构130可包含有位线接触插塞132、与位线接触插塞132实体与电连接的位线134、设置于位线134侧壁的间隙壁136、以及形成于位线134顶部的覆盖层138。如图1所示，每一个位线结构130沿第一方向D1延伸，并且多个位线结构130彼此之间沿第二方向D2排列。另外值得注意的是，位线结构130的间隙壁136以及覆盖层138包含一第二绝缘材料，且第二绝缘材料不同于第一绝缘材料。举例来说，第二绝缘材料较佳包含氮化硅(SiN)或氮碳化硅(SiCN)，但不限于此。
请参阅图3，请注意以下图3～图9是基于图2所绘示的剖面结构继续进行后续步骤所得的剖视图。在基底100上形成多个第一掩模图案(mask pattern，图未示)，接下来以第一掩模图案为保护层，进行一蚀刻步骤，移除部分的第一绝缘层120，形成多个凹槽126，各凹槽126的位置对应到各埋入式栅极114的位置。随后移除第一掩模图案。
请参阅图4。在形成凹槽126之后，在基底100上形成一第二绝缘层140，第二绝缘层140填满凹槽126并完全覆盖第一绝缘层120的表面与位线结构130的表面。值得注意的是，第二绝缘层120可包含第二绝缘材料，例如为氮化硅(Si3N4)，但不限于此。
请参阅图5。在形成第二绝缘层140之后，在存储区域102内形成一第二掩模图案142，且第二掩模图案142暴露出第二绝缘层140的部分表面。随后，移除被第二掩模图案140暴露出的第二绝缘层140部分表面，使第一绝缘层120形成多个第二暴露部分148，随后移除第二掩模图案142。此外，在本较佳实施例中，由于存储区域102内仅有部分的第二绝缘层140被移除，故存储区域102内的第二绝缘层140的顶部表面包含有一阶差(step height)h。
请参阅图6。接下来，移除第一绝缘层120的第二暴露部分148，并形成多个凹槽156，其中凹槽156暴露出源/漏极区域118，而此处所述的凹槽156即是后续步骤中，存储节点接触(storage node contact)或是与存储节点接触电连接的接触插塞的预定形成位置，也就是说，可能会先形成一接触插塞于凹槽156内，接着再形成存储节点接触电连接上述接触插塞，或是直接形成存储节点接触于凹槽156内。
接下来，如图7所示，先进行一原子注入或一等离子体注入步骤，在凹槽156的底部形成一扩散阻障区158，其中扩散阻障区158包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组。较佳而言，本发明中扩散阻障区所掺杂的原子不会包含有三-五族原子，例如硼原子等，以免影响整体DRAM结构的电性表现。而形成扩散阻障区158的目的，则是为了防止后续形成于扩散阻障区158上方的接触结构或非晶硅层等，其中所包含的原子(例如磷原子)扩散至源/漏极区域118中而影响电性。根据申请人的实验结果，在一基体中掺杂碳原子，可以有效降低磷原子的扩散。本发明中，在扩散阻障区158内所掺杂的原子浓度，较佳介于1*1013/平方厘米至4*1022/平方厘米之间。请注意，此处的扩散阻障区158位于源/漏极区域118的顶部，也就是与源/漏极区域118直接接触，但是由于扩散阻障区158包含有不同于源/漏极区域118内的掺杂原子，因此可视为不同于源/漏极区域118的另外一个区域。
接下来，请参阅图8至图9。在形成扩散阻障区158之后，在扩散阻障区158上再次形成一存储节点接触160，其中本实施例中，存储节点接触160包含有下半部161以及上半部162，下半部包含有一掺杂的非晶硅或多晶硅层，举例来说，可能主要包含有一掺杂磷(P)的非晶硅(amorphous silicon)层，而上半部162则包含有低阻值的一金属层，例如钨，此外，在下半部161以及上半部162之间，可能再额外形成一金属硅化物层(图未示)，但不限于此。上述形成的扩散阻障区158则是位于存储节点接触160的下半部161与源/漏极区域118之间，以达到防止存储节点接触160的下半部161中的磷原子扩散至源/漏极区域118内而影响电性。接下来如图9所示，在各存储节点接触160的上方再形成下电极164。本发明中，下电极164可作为DRAM结构中电容的下电极所使用。在本较佳实施例中，下电极164可通过现有的技术所形成，材质例如包含有金属或合金等导电材料。下电极164通过存储节点接触160，与源/漏极区域118电连接。此外，虽然本实施例中，直接在存储节点接触160上方形成下电极164，但是在其他的实施例中，在下电极164与存储节点接触160之间，可能包含有其他的接触结构，例如由导电层(材质例如为钨)以及阻障层(材质例如为氮化钛)组成的接触结构等，也属于本发明的涵盖范围内。随后，更可继续形成存储电极接触垫(landing pad)以及电容器的制作。此为本领域的现有技术，在此不多加赘述。
是以，请参考上述图1～图9，本较佳实施例是提供一种半导体结构，其中较重要的元件主要包含有基底100，基底100定义有至少存储区域102，且存储区域102内设置有多个晶体管110。至少一埋入式栅极(或埋入式位线)114位于存储区域102内的基底100内，至少一源/漏极区域118，位于埋入式栅极114旁的基底100中，一扩散阻障区158，位于源/漏极区域118顶部，且扩散阻障区158包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组，以及一至少存储节点接触160，位于第二绝缘层140中，与源/漏极区域118电连接。
综上所述，本发明的特征在于，在与存储节点接触电连接的接触插塞，以及埋入式栅极(埋入式字符线)旁的源/漏极区域之间，额外形成一扩散阻障区。由于接触插塞可能包含掺杂磷原子的非晶硅层，因此在扩散阻障区内掺杂有例如碳原子等非三-五族原子，可以避免接触插塞内磷原子扩散至源/漏极区域内，进而影响电性。因此，本发明可以提升DRAM结构的良率与品质。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (15)

1.一种半导体结构，包含有：
基底，包含有至少一主动区定义于该基底上；
至少一埋入式位线，位于该主动区内的该基底内；
源/漏极区域，位于该至少一埋入式位线旁的该基底中；
扩散阻障区，位于该源/漏极区域顶部，且该扩散阻障区包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组；
绝缘层，位于该基底上；以及
接触结构，位于该绝缘层中，与该源/漏极区域电连接。
2.如权利要求1所述的半导体结构，其中还包含至少一字符线，位于该主动区内的该基底上，并与该埋入式位线交错排列。
3.如权利要求1所述的半导体结构，其中该扩散阻障区的该掺杂原子的掺杂浓度介于1*1013/平方厘米至4*1022/平方厘米。
4.如权利要求1所述的半导体结构，还包含一金属硅化物，位于该接触结构之中。
5.如权利要求1所述的半导体结构，其中该接触结构是一存储节点接触(storage nodecontact)。
6.如权利要求1所述的半导体结构，其中该接触结构包含有掺杂的非晶硅层，以及金属层，位于该掺杂的非晶硅层上。
7.如权利要求6所述的半导体结构，其中该掺杂的非晶硅层包含有多个第二掺杂原子，且该第二掺杂原子包含有磷原子。
8.一种半导体结构的制作方法，包含有：
提供一基底，包含有至少一主动区定义于该基底上；
形成至少一埋入式位线于该主动区内的该基底内；
形成一源/漏极区域于该至少一埋入式位线旁的该基底中；
形成一扩散阻障区于该源/漏极区域顶部，且该扩散阻障区包含有多个掺杂原子，该些掺杂原子可选自碳原子、氮原子、锗原子、氧原子、氦原子以及氙原子的群组；
形成一绝缘层于该基底上；以及
形成一接触结构于该绝缘层中，该接触结构与该源/漏极区域电连接。
9.如权利要求8所述的制作方法，其中还包含形成至少一字符线于该主动区内的该基底上，并与该埋入式位线交错排列。
10.如权利要求8所述的制作方法，其中该扩散阻障区的该掺杂原子的掺杂浓度介于1*1013/平方厘米至4*1022/平方厘米。
11.如权利要求8所述的制作方法，还包含形成一金属硅化物于该接触结构之中。
12.如权利要求8所述的制作方法，其中该接触结构是一存储节点接触(storage nodecontact)。
13.如权利要求8所述的制作方法，其中该接触结构包含有掺杂的非晶硅层，以及金属层，位于该掺杂的非晶硅层上。
14.如权利要求13所述的制作方法，其中该掺杂的非晶硅层包含有多个第二掺杂原子，且该第二掺杂原子包含有磷原子。
15.如权利要求8所述的制作方法，其中形成该扩散阻障区的方法包含原子注入或等离子体注入。
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