JP4919738B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP4919738B2
JP4919738B2 JP2006235519A JP2006235519A JP4919738B2 JP 4919738 B2 JP4919738 B2 JP 4919738B2 JP 2006235519 A JP2006235519 A JP 2006235519A JP 2006235519 A JP2006235519 A JP 2006235519A JP 4919738 B2 JP4919738 B2 JP 4919738B2
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JP
Japan
Prior art keywords
layer
light
conductive layer
conductive
emitting
Prior art date
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Expired - Fee Related
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JP2006235519A
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English (en)
Japanese (ja)
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JP2008060324A5 (enExample
JP2008060324A (ja
Inventor
将文 森末
幸一郎 田中
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2006235519A priority Critical patent/JP4919738B2/ja
Priority to US11/896,031 priority patent/US7851250B2/en
Priority to CN201110081650XA priority patent/CN102208419B/zh
Priority to KR1020070088197A priority patent/KR101357684B1/ko
Priority to CN200710142266XA priority patent/CN101136312B/zh
Publication of JP2008060324A publication Critical patent/JP2008060324A/ja
Publication of JP2008060324A5 publication Critical patent/JP2008060324A5/ja
Priority to US12/777,580 priority patent/US8293593B2/en
Application granted granted Critical
Publication of JP4919738B2 publication Critical patent/JP4919738B2/ja
Expired - Fee Related legal-status Critical Current
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0221Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0241Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441Interconnections, e.g. scanning lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00Climate change mitigation technologies for sector-wide applications
    • Y02P80/30Reducing waste in manufacturing processes; Calculations of released waste quantities

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
JP2006235519A 2006-08-31 2006-08-31 半導体装置の作製方法 Expired - Fee Related JP4919738B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2006235519A JP4919738B2 (ja) 2006-08-31 2006-08-31 半導体装置の作製方法
US11/896,031 US7851250B2 (en) 2006-08-31 2007-08-29 Method for manufacturing semiconductor device and method for manufacturing display device
KR1020070088197A KR101357684B1 (ko) 2006-08-31 2007-08-31 반도체 장치의 제작 방법
CN200710142266XA CN101136312B (zh) 2006-08-31 2007-08-31 半导体器件的制造方法及显示器件的制造方法
CN201110081650XA CN102208419B (zh) 2006-08-31 2007-08-31 半导体器件的制造方法及显示器件的制造方法
US12/777,580 US8293593B2 (en) 2006-08-31 2010-05-11 Method for manufacturing semiconductor device and method for manufacturing display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006235519A JP4919738B2 (ja) 2006-08-31 2006-08-31 半導体装置の作製方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011277871A Division JP5409759B2 (ja) 2011-12-20 2011-12-20 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2008060324A JP2008060324A (ja) 2008-03-13
JP2008060324A5 JP2008060324A5 (enExample) 2009-07-23
JP4919738B2 true JP4919738B2 (ja) 2012-04-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006235519A Expired - Fee Related JP4919738B2 (ja) 2006-08-31 2006-08-31 半導体装置の作製方法

Country Status (4)

Country Link
US (2) US7851250B2 (enExample)
JP (1) JP4919738B2 (enExample)
KR (1) KR101357684B1 (enExample)
CN (2) CN101136312B (enExample)

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JP5184115B2 (ja) * 2008-01-31 2013-04-17 日東電工株式会社 配線回路基板およびその製造方法
KR100846877B1 (ko) 2008-04-10 2008-07-16 주식회사 세종테크 금속증착층을 갖는 광투과성 사출품의 투과표시패턴 형성방법
KR20090110099A (ko) * 2008-04-17 2009-10-21 삼성전자주식회사 박막 트랜지스터 표시판, 이의 제조 방법 및 이를 포함하는평판 표시 장치
KR20100067434A (ko) * 2008-12-11 2010-06-21 한국기계연구원 상이한 레이저 제거 최소 임계값을 이용한 미세 패턴 방법 및 이를 이용한 tft의 형성 방법.
TWI415283B (zh) * 2009-02-18 2013-11-11 Au Optronics Corp X射線感測器及其製作方法
EP2234100B1 (en) 2009-03-26 2016-11-02 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
CN102576737B (zh) 2009-10-09 2015-10-21 株式会社半导体能源研究所 半导体器件及其制造方法
KR102317763B1 (ko) 2009-11-06 2021-10-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
CN102648525B (zh) 2009-12-04 2016-05-04 株式会社半导体能源研究所 显示装置
JP2012064709A (ja) * 2010-09-15 2012-03-29 Sony Corp 固体撮像装置及び電子機器
CN102311095B (zh) * 2011-08-09 2013-11-06 吉林大学 一种在微流控芯片中制备多级金属微纳结构的方法
CN102489873B (zh) * 2011-11-16 2014-07-16 中国科学院上海光学精密机械研究所 在多孔玻璃内部制备三维微流通道的方法
KR101899481B1 (ko) * 2011-12-23 2018-09-18 삼성전자주식회사 전자 장치의 배선 형성 방법
CN103354243B (zh) 2013-06-28 2016-01-06 京东方科技集团股份有限公司 一种薄膜晶体管、其制备方法及相关装置
CN105334680A (zh) * 2014-08-15 2016-02-17 群创光电股份有限公司 阵列基板结构及接触结构
CN113128276A (zh) * 2019-12-31 2021-07-16 格科微电子(上海)有限公司 光学指纹器件的制造方法
CN113568225A (zh) * 2021-07-09 2021-10-29 西安中科微星光电科技有限公司 一种液晶光阀模组封装结构

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JPS6384789A (ja) 1986-09-26 1988-04-15 Semiconductor Energy Lab Co Ltd 光加工方法
US5708252A (en) 1986-09-26 1998-01-13 Semiconductor Energy Laboratory Co., Ltd. Excimer laser scanning system
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JPH06250211A (ja) 1993-02-23 1994-09-09 Hitachi Ltd 液晶表示基板とその製造方法
US6741494B2 (en) * 1995-04-21 2004-05-25 Mark B. Johnson Magnetoelectronic memory element with inductively coupled write wires
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JP4713818B2 (ja) * 2003-03-28 2011-06-29 パナソニック株式会社 有機トランジスタの製造方法、及び有機el表示装置の製造方法
KR101111995B1 (ko) 2003-12-02 2012-03-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터, 디스플레이 장치 및 액정 디스플레이장치, 그리고 그 제조방법
JP4712361B2 (ja) * 2003-12-02 2011-06-29 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法
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US7579224B2 (en) * 2005-01-21 2009-08-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film semiconductor device

Also Published As

Publication number Publication date
KR20080020579A (ko) 2008-03-05
CN101136312B (zh) 2011-05-25
US20080057605A1 (en) 2008-03-06
CN101136312A (zh) 2008-03-05
JP2008060324A (ja) 2008-03-13
US20100219413A1 (en) 2010-09-02
US7851250B2 (en) 2010-12-14
US8293593B2 (en) 2012-10-23
KR101357684B1 (ko) 2014-02-03
CN102208419B (zh) 2013-03-27
CN102208419A (zh) 2011-10-05

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