JP2008060324A - 半導体装置の作製方法及び表示装置の作製方法 - Google Patents
半導体装置の作製方法及び表示装置の作製方法 Download PDFInfo
- Publication number
- JP2008060324A JP2008060324A JP2006235519A JP2006235519A JP2008060324A JP 2008060324 A JP2008060324 A JP 2008060324A JP 2006235519 A JP2006235519 A JP 2006235519A JP 2006235519 A JP2006235519 A JP 2006235519A JP 2008060324 A JP2008060324 A JP 2008060324A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light
- conductive layer
- conductive
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Abstract
【解決手段】基板上に導電層を形成し、該導電層上に光透過層を形成し、該光透過層上からフェムト秒レーザを照射して、該導電層及び該光透過層を選択的に除去する工程を有する。なお、該導電層の端部は、該光透過層の端部より内側に配置されるように該導電層及び該光透過層を除去されていてもよい。また、フェムト秒レーザを照射する前に、該光透過層表面に撥液処理を行ってもよい。
【選択図】図1
Description
本実施の形態では、フェムト秒レーザを用いて開口部(コンタクトホール)を形成し、該開口部に液状の導電性材料を吐出することにより該開口部を覆う導電層を形成する方法について説明する。
本実施の形態では、実施の形態1の方法を用いた半導体装置の作製方法について、図3を用いて説明する。
本実施の形態では、薄膜トランジスタに接続される導電層を有する半導体装置の作製方法について、図4を用いて説明する。ここでは、半導体装置として液晶表示パネルを形成する。また、図4においては、液晶表示パネルの一画素の断面図を示して、以下説明する。
本実施例では、薄膜トランジスタに接続される導電層を有する半導体装置の作製方法について説明する。ここでは、導電層として画素電極を形成し、半導体装置として発光表示パネルを形成する。さらに、図8においては、発光表示パネルの一画素を示して、以下説明する。
本実施の形態では、半導体装置の代表例を、図12及び図13を用いて説明する。電気泳動素子とは、マイクロカプセルの中にプラスとマイナスに帯電した黒と白の粒子を閉じ込めた物を第1の導電層及び第2の導電層の間に配置し、第1の導電層及び第2の導電層に電位差を生じさせて黒と白の粒子を電極間で移動させて表示を行う素子である。
実施の形態3〜5によって作製される表示パネル(EL表示パネル、液晶表示パネル、電気泳動表示パネル)において、半導体層を非晶質半導体、又はSASで形成し、走査線側の駆動回路を基板上に形成する例を示す。
上記実施の形態や示される半導体装置を有する電子機器として、テレビジョン装置(単にテレビ、又はテレビジョン受信機ともよぶ)、デジタルカメラ、デジタルビデオカメラ、携帯電話装置(単に携帯電話機、携帯電話ともよぶ)、PDA等の携帯情報端末、携帯型ゲーム機、コンピュータ用のモニター、コンピュータ、カーオーディオ等の音響再生装置、家庭用ゲーム機等の記録媒体を備えた画像再生装置等が挙げられる。その具体例について、図19を参照して説明する。
721 導電層
722 光透過層
724 導電性材料
725 開口部
726 導電層
Claims (7)
- 基板上に導電層を形成し、
前記導電層上に光透過層を形成し、
前記光透過層上からフェムト秒レーザを照射して、前記導電層及び前記光透過層を選択的に除去することを特徴とする半導体装置の作製方法。 - 基板上に導電層を形成し、
前記導電層上に光透過層を形成し、
前記光透過層上からフェムト秒レーザを照射して、前記導電層及び前記光透過層を選択的に除去して前記導電膜及び前記光透過層に開口部を形成し、
前記開口部に液状の導電性材料を滴下することを特徴とする半導体装置の作製方法。 - 請求項1又は請求項2において、
前記導電層の端部は、前記光透過層の端部より内側に配置されるように前記導電層及び前記光透過層を除去することを特徴とする半導体装置の作製方法。 - 基板上に第1の導電層を形成し、
前記第1の導電層上に光透過層を形成し、
前記光透過層上からフェムト秒レーザを照射して、前記第1の導電層及び前記光透過層を選択的に除去して前記第1の導電膜及び前記光透過層に開口部を形成し、
前記開口部に液状の導電性材料を滴下して、前記第1の導電層と電気的に接続する第2の導電層を形成することを特徴とする半導体装置の作製方法。 - 請求項4において、
前記第1の導電層の端部は、前記光透過層の端部より内側に配置されるように前記第1の導電層及び前記光透過層を除去することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一項において、
前記光透過層表面に撥液処理を行うことを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項6のいずれか一項に記載の半導体装置の作製方法を用いることを特徴とする表示装置の作製方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006235519A JP4919738B2 (ja) | 2006-08-31 | 2006-08-31 | 半導体装置の作製方法 |
US11/896,031 US7851250B2 (en) | 2006-08-31 | 2007-08-29 | Method for manufacturing semiconductor device and method for manufacturing display device |
CN200710142266XA CN101136312B (zh) | 2006-08-31 | 2007-08-31 | 半导体器件的制造方法及显示器件的制造方法 |
KR1020070088197A KR101357684B1 (ko) | 2006-08-31 | 2007-08-31 | 반도체 장치의 제작 방법 |
CN201110081650XA CN102208419B (zh) | 2006-08-31 | 2007-08-31 | 半导体器件的制造方法及显示器件的制造方法 |
US12/777,580 US8293593B2 (en) | 2006-08-31 | 2010-05-11 | Method for manufacturing semiconductor device and method for manufacturing display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006235519A JP4919738B2 (ja) | 2006-08-31 | 2006-08-31 | 半導体装置の作製方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011277871A Division JP5409759B2 (ja) | 2011-12-20 | 2011-12-20 | 半導体装置の作製方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008060324A true JP2008060324A (ja) | 2008-03-13 |
JP2008060324A5 JP2008060324A5 (ja) | 2009-07-23 |
JP4919738B2 JP4919738B2 (ja) | 2012-04-18 |
Family
ID=39152163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006235519A Expired - Fee Related JP4919738B2 (ja) | 2006-08-31 | 2006-08-31 | 半導体装置の作製方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7851250B2 (ja) |
JP (1) | JP4919738B2 (ja) |
KR (1) | KR101357684B1 (ja) |
CN (2) | CN101136312B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100846877B1 (ko) | 2008-04-10 | 2008-07-16 | 주식회사 세종테크 | 금속증착층을 갖는 광투과성 사출품의 투과표시패턴 형성방법 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5184115B2 (ja) * | 2008-01-31 | 2013-04-17 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
KR20090110099A (ko) * | 2008-04-17 | 2009-10-21 | 삼성전자주식회사 | 박막 트랜지스터 표시판, 이의 제조 방법 및 이를 포함하는평판 표시 장치 |
KR20100067434A (ko) * | 2008-12-11 | 2010-06-21 | 한국기계연구원 | 상이한 레이저 제거 최소 임계값을 이용한 미세 패턴 방법 및 이를 이용한 tft의 형성 방법. |
TWI415283B (zh) * | 2009-02-18 | 2013-11-11 | Au Optronics Corp | X射線感測器及其製作方法 |
EP2234100B1 (en) | 2009-03-26 | 2016-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
CN102576737B (zh) | 2009-10-09 | 2015-10-21 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
EP2497115A4 (en) | 2009-11-06 | 2015-09-02 | Semiconductor Energy Lab | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR |
CN105609509A (zh) * | 2009-12-04 | 2016-05-25 | 株式会社半导体能源研究所 | 显示装置 |
JP2012064709A (ja) * | 2010-09-15 | 2012-03-29 | Sony Corp | 固体撮像装置及び電子機器 |
CN102311095B (zh) * | 2011-08-09 | 2013-11-06 | 吉林大学 | 一种在微流控芯片中制备多级金属微纳结构的方法 |
CN102489873B (zh) * | 2011-11-16 | 2014-07-16 | 中国科学院上海光学精密机械研究所 | 在多孔玻璃内部制备三维微流通道的方法 |
KR101899481B1 (ko) * | 2011-12-23 | 2018-09-18 | 삼성전자주식회사 | 전자 장치의 배선 형성 방법 |
CN103354243B (zh) * | 2013-06-28 | 2016-01-06 | 京东方科技集团股份有限公司 | 一种薄膜晶体管、其制备方法及相关装置 |
CN105334680A (zh) * | 2014-08-15 | 2016-02-17 | 群创光电股份有限公司 | 阵列基板结构及接触结构 |
CN113128276A (zh) * | 2019-12-31 | 2021-07-16 | 格科微电子(上海)有限公司 | 光学指纹器件的制造方法 |
CN113568225A (zh) * | 2021-07-09 | 2021-10-29 | 西安中科微星光电科技有限公司 | 一种液晶光阀模组封装结构 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06250211A (ja) * | 1993-02-23 | 1994-09-09 | Hitachi Ltd | 液晶表示基板とその製造方法 |
JP2004297011A (ja) * | 2003-03-28 | 2004-10-21 | Matsushita Electric Ind Co Ltd | 有機トランジスタの製造方法、及び有機el表示装置の製造方法 |
JP2005210083A (ja) * | 2003-12-02 | 2005-08-04 | Semiconductor Energy Lab Co Ltd | 薄膜トランジスタ、並びに表示装置、液晶表示装置及びそれらの作製方法 |
JP2006100324A (ja) * | 2004-09-28 | 2006-04-13 | Seiko Epson Corp | 膜パターンの形成方法 |
JP2006135289A (ja) * | 2004-11-05 | 2006-05-25 | Lg Phillips Lcd Co Ltd | 薄膜蝕刻方法及びこれを用いた液晶表示装置の製造方法 |
US20060163743A1 (en) * | 2005-01-21 | 2006-07-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same, and electric device |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708252A (en) | 1986-09-26 | 1998-01-13 | Semiconductor Energy Laboratory Co., Ltd. | Excimer laser scanning system |
JPS6384789A (ja) | 1986-09-26 | 1988-04-15 | Semiconductor Energy Lab Co Ltd | 光加工方法 |
US6149988A (en) | 1986-09-26 | 2000-11-21 | Semiconductor Energy Laboratory Co., Ltd. | Method and system of laser processing |
US6741494B2 (en) * | 1995-04-21 | 2004-05-25 | Mark B. Johnson | Magnetoelectronic memory element with inductively coupled write wires |
JP3236266B2 (ja) | 1998-10-27 | 2001-12-10 | 鹿児島日本電気株式会社 | パターン形成方法 |
JP3756041B2 (ja) * | 1999-05-27 | 2006-03-15 | Hoya株式会社 | 多層プリント配線板の製造方法 |
JP2002162652A (ja) * | 2000-01-31 | 2002-06-07 | Fujitsu Ltd | シート状表示装置、樹脂球状体、及びマイクロカプセル |
US6788368B2 (en) * | 2000-03-23 | 2004-09-07 | Daicel Chemical Industries, Ltd. | Transmission light-scattering layer sheet and liquid crystal display |
JP2003133070A (ja) * | 2001-10-30 | 2003-05-09 | Seiko Epson Corp | 積層膜の製造方法、電気光学装置、電気光学装置の製造方法、有機エレクトロルミネッセンス装置の製造方法、及び電子機器 |
JP4068942B2 (ja) | 2001-12-17 | 2008-03-26 | セイコーエプソン株式会社 | 電気光学装置及びその製造方法、並びに電子機器 |
US7148508B2 (en) * | 2002-03-20 | 2006-12-12 | Seiko Epson Corporation | Wiring substrate, electronic device, electro-optical device, and electronic apparatus |
JP2004062152A (ja) * | 2002-06-03 | 2004-02-26 | Sharp Corp | 双方向二端子素子を用いた表示装置およびその製造方法 |
JP2004055159A (ja) | 2002-07-16 | 2004-02-19 | Dainippon Screen Mfg Co Ltd | 有機el素子の製造方法および有機el表示装置 |
US7868957B2 (en) * | 2003-12-02 | 2011-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, display device and liquid crystal display device and method for manufacturing the same |
US7692378B2 (en) * | 2004-04-28 | 2010-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Display device including an insulating layer with an opening |
US8772783B2 (en) | 2004-10-14 | 2014-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
-
2006
- 2006-08-31 JP JP2006235519A patent/JP4919738B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-29 US US11/896,031 patent/US7851250B2/en not_active Expired - Fee Related
- 2007-08-31 KR KR1020070088197A patent/KR101357684B1/ko not_active IP Right Cessation
- 2007-08-31 CN CN200710142266XA patent/CN101136312B/zh not_active Expired - Fee Related
- 2007-08-31 CN CN201110081650XA patent/CN102208419B/zh not_active Expired - Fee Related
-
2010
- 2010-05-11 US US12/777,580 patent/US8293593B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06250211A (ja) * | 1993-02-23 | 1994-09-09 | Hitachi Ltd | 液晶表示基板とその製造方法 |
JP2004297011A (ja) * | 2003-03-28 | 2004-10-21 | Matsushita Electric Ind Co Ltd | 有機トランジスタの製造方法、及び有機el表示装置の製造方法 |
JP2005210083A (ja) * | 2003-12-02 | 2005-08-04 | Semiconductor Energy Lab Co Ltd | 薄膜トランジスタ、並びに表示装置、液晶表示装置及びそれらの作製方法 |
JP2006100324A (ja) * | 2004-09-28 | 2006-04-13 | Seiko Epson Corp | 膜パターンの形成方法 |
JP2006135289A (ja) * | 2004-11-05 | 2006-05-25 | Lg Phillips Lcd Co Ltd | 薄膜蝕刻方法及びこれを用いた液晶表示装置の製造方法 |
US20060163743A1 (en) * | 2005-01-21 | 2006-07-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same, and electric device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100846877B1 (ko) | 2008-04-10 | 2008-07-16 | 주식회사 세종테크 | 금속증착층을 갖는 광투과성 사출품의 투과표시패턴 형성방법 |
Also Published As
Publication number | Publication date |
---|---|
KR101357684B1 (ko) | 2014-02-03 |
CN101136312B (zh) | 2011-05-25 |
US7851250B2 (en) | 2010-12-14 |
JP4919738B2 (ja) | 2012-04-18 |
US8293593B2 (en) | 2012-10-23 |
US20100219413A1 (en) | 2010-09-02 |
CN102208419A (zh) | 2011-10-05 |
CN102208419B (zh) | 2013-03-27 |
US20080057605A1 (en) | 2008-03-06 |
KR20080020579A (ko) | 2008-03-05 |
CN101136312A (zh) | 2008-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4919738B2 (ja) | 半導体装置の作製方法 | |
JP5628949B2 (ja) | 半導体装置の作製方法 | |
US7994021B2 (en) | Method of manufacturing semiconductor device | |
JP5268304B2 (ja) | 半導体装置の作製方法 | |
JP5110830B2 (ja) | 半導体装置の作製方法 | |
JP5216276B2 (ja) | 半導体装置の作製方法 | |
US8158517B2 (en) | Method for manufacturing wiring substrate, thin film transistor, display device and television device | |
US7470604B2 (en) | Method for manufacturing display device | |
JP5110785B2 (ja) | 表示装置の作製方法 | |
JP5227563B2 (ja) | 半導体装置の作製方法 | |
JP5314857B2 (ja) | 半導体装置の作製方法 | |
KR20080037594A (ko) | 반도체 장치의 제작 방법 | |
KR20080018845A (ko) | 반도체장치의 제조방법 | |
JP2008033284A (ja) | 表示装置の作製方法 | |
JP4954836B2 (ja) | 半導体装置の作製方法 | |
JP5314842B2 (ja) | 半導体装置の作製方法 | |
JP5409759B2 (ja) | 半導体装置の作製方法 | |
JP2008034832A (ja) | 表示装置の作製方法 | |
JP5276811B2 (ja) | 半導体装置の作製方法 | |
JP2008176095A (ja) | パターン形成方法及び薄膜トランジスタの作製方法 | |
JP2008052268A (ja) | 表示装置の作製方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090605 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090605 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111027 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111115 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111221 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120131 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120131 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150210 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150210 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |