JP4896850B2 - 半導体装置のCu配線およびその製造方法 - Google Patents
半導体装置のCu配線およびその製造方法 Download PDFInfo
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Description
φ4インチのシリコンウェハー表面に、TaN層をDCマグネトロンスパッタリング法で厚みが50nmとなるように成膜し、次いで純Cu層(下記表1のNo.1)または下記表1に示す元素を含有する密着性Cu層(残部はCuおよび不可避不純物)をDCマグネトロンスパッタリング法で厚みが200nmとなるように成膜して積層体を得た。
上記実験例1において、TaN層の表面に、Pt,In,Ti,Nb,BまたはFeの含有量を調整した密着性Cu層(残部はCuおよび不可避不純物)を形成した以外は、上記実験例1と同じ条件で積層体を得た。
上記実験例1において、TaN層の表面に、Fe含有量を調整した密着性Cu層(残部はCuおよび不可避不純物)を形成した後、常圧で加熱(以下、常圧アニール処理ということがある)するか、加熱しつつ加圧(以下、高圧アニール処理ということがある)して積層体を得た。常圧アニール処理は、常圧(0.1MPa)のAr雰囲気中で、室温から500℃まで昇温速度5℃/分で加熱し、500℃で15分間保持した後、室温まで降温速度5℃/分で冷却して行なった。高圧アニール処理は、133×10-6Pa以下(1×10-6Torr以下)の真空で、150MPaに加圧し、室温から500℃まで昇温速度15℃/分で加熱し、500℃で15分間保持した後、室温まで降温速度10℃/分で冷却して行なった。
上記実験例1において、TaN層の表面にFeを1.88原子%含有する密着性Cu層(残部はCuおよび不可避不純物)を形成した後、上記実験例3のように常圧で加熱するか(常圧アニール処理)、加熱しつつ加圧(高圧アニール処理)して積層体を得た。
上記実験例1において、TaN層の表面に、Pt,In,Ti,Nb,BまたはFeの含有量を調整した密着性Cu層(残部はCuおよび不可避不純物)を50nm形成した後、純Cu層をDCマグネトロンスパッタリング法で厚みが200nmとなるように成膜して積層体を得た。
上記実験例1において、TaN層の表面に、Tiを1.79原子%含有する密着性Cu層(残部はCuおよび不可避不純物)を10〜50nm形成した後、純Cu層をDCマグネトロンスパッタリング法で厚みが200nmとなるように成膜して積層体Aを得た。また、純Cu層をDCマグネトロンスパッタリング法で成膜する代わりに、電解メッキ法で厚みが200nmとなるように成膜して積層体Bを得た。電解メッキは、電流密度17mA/cm2で行なった。
上記実験例1において、TaN層の表面に、Nbを2.35原子%含有する密着性Cu層(残部はCuおよび不可避不純物)を10〜50nm形成した後、純Cu層をDCマグネトロンスパッタリング法で厚みが200nmとなるように成膜し、次いで常圧で加熱(常圧アニール処理)するか、加熱しつつ加圧(高圧アニール処理)して積層体を得た。常圧アニール処理と高圧アニール処理は、上記実験例3で示した条件で行なった。
上記実験例1において、TaN層の表面に、Feを1.88原子%含有する密着性Cu層(残部はCuおよび不可避不純物)を50nm形成した後、純Cu層をDCマグネトロンスパッタリング法で厚みが200nmとなるように成膜し、次いで常圧で加熱(常圧アニール処理)するか、加熱しつつ加圧(高圧アニール処理)して積層体を得た。常圧アニール処理と高圧アニール処理は、上記実験例3で示した条件で行なった。
シリコンウェハー表面に形成した絶縁膜(TEOS膜:SiOF膜)に、直径0.12μm(120nm)、深さ0.55μm(550nm)、ピッチ450nmのビアを設けた評価素子(TEG)を用いた。このTEGの表面に、TaN層をDCマグネトロンスパッタリング法で上記実験例1と同じ条件で厚みが50nmとなるように成膜した後、Feを1.88原子%含有する密着性Cu層(残部はCuおよび不可避不純物)をスパッタリング法(CS法)またはロングスロースパッタリング法(LTS法)で厚みが500nmとなるように成膜した。
埋め込み率(%)=[(ビアに埋め込まれている密着性Cu層の断面積)/(ビアの断面積)]×100 ・・・(4)
上記実験例9において、TaN層の表面に、Tiを1.79原子%含有する密着性Cu層(残部はCuおよび不可避不純物)をスパッタリング法(CS法)で厚みが10〜50nmとなるように形成し、次いで純Cu層を電解メッキ法、スパッタリング法(CS法)、ロングスロースパッタリング法(LTS法)で厚みが500nmとなるように成膜した。
上記実験例1において、TaN層の表面に、V,Zr,Re,Ru,Hf,Ga,OsまたはTlの含有量を調整した密着性Cu層(残部はCuおよび不可避不純物)を形成した以外は、上記実験例1と同じ条件で積層体を得た。なお、Gaは融点が低いため、Ga元素からなる金属チップを製造することができない。そこで、Gaについては、Gaを5原子%または10原子%含有するCu合金チップ(残部は、不可避不純物)を作製し、ベースとなる純Cuターゲット(φ100mm)の表面に貼り付ける5mm角のCu合金チップを3〜6枚エロージョン位置付近に貼り付けたものをチップオンターゲットとして用いた。Cu合金チップの種類や枚数、貼付位置を変化させることで、密着性Cu層に含まれる組成を制御した。
上記実験例1において、TaN層の表面に、V,Zr,Re,Ru,HfまたはGaの含有量を調整した密着性Cu層(残部はCuおよび不可避不純物)を50nm形成した後、純Cu層をDCマグネトロンスパッタリング法で厚みが200nmとなるように成膜して積層体を得た。
Claims (4)
- 半導体基板上の絶縁膜に形成された配線溝または層間接続路に埋め込まれたCu配線であって、
前記Cu配線は、
(1)配線溝側または層間接続路側に形成されたTaNからなるバリア層と、
(2)Pt、B、Tl、RuおよびOsよりなる群から選ばれる1種以上の密着性向上元素を合計で0.05〜3.0原子%含有し、残部がCuおよび不可避不純物からなる配線本体部とで構成されていることを特徴とする半導体装置のCu配線。 - 前記配線溝または前記層間接続路は、幅が0.15μm以下で、この幅に対する深さの比(深さ/幅)が1以上である請求項1に記載のCu配線。
- 請求項1に記載の半導体装置のCu配線を製造する方法であって、
半導体基板上の絶縁膜に形成された配線溝または層間接続路の表面にTaN層を形成する工程と、
このTaN層の表面にスパッタリング法でPt、B、Tl、RuおよびOsよりなる群から選ばれる1種以上の密着性向上元素を合計で0.05〜3.0原子%含有し、残部がCuおよび不可避不純物からなるCu層を配線本体部として形成する工程を含むことを特徴とする半導体装置のCu配線の製造方法。 - 前記配線溝または前記層間接続路は、幅が0.15μm以下で、この幅に対する深さの比(深さ/幅)が1以上であり、前記Cu層を形成した後、加熱しつつ加圧してCu層をTaN層付き配線溝または層間接続路に押し込む請求項3に記載の製造方法。
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US12/515,538 US20100052171A1 (en) | 2006-11-28 | 2007-11-19 | Cu wire in semiconductor device and production method thereof |
PCT/JP2007/072417 WO2008065925A1 (en) | 2006-11-28 | 2007-11-19 | SEMICONDUCTOR DEVICE Cu WIRING AND METHOD FOR MANUFACTURING THE SAME |
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JP5384269B2 (ja) * | 2009-09-18 | 2014-01-08 | 東京エレクトロン株式会社 | Cu配線の形成方法 |
JP5213146B1 (ja) * | 2012-10-03 | 2013-06-19 | 田中電子工業株式会社 | 半導体装置接続用銅ロジウム合金細線 |
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US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
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US20060121307A1 (en) * | 2004-10-22 | 2006-06-08 | Tokyo Electron Limited | Film deposition method |
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