EP1433202A2 - Integration of barrier layer and seed layer - Google Patents

Integration of barrier layer and seed layer

Info

Publication number
EP1433202A2
EP1433202A2 EP02757668A EP02757668A EP1433202A2 EP 1433202 A2 EP1433202 A2 EP 1433202A2 EP 02757668 A EP02757668 A EP 02757668A EP 02757668 A EP02757668 A EP 02757668A EP 1433202 A2 EP1433202 A2 EP 1433202A2
Authority
EP
European Patent Office
Prior art keywords
seed layer
layer
copper
chamber
atomic percent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02757668A
Other languages
German (de)
French (fr)
Inventor
Hua Chung
Ling Chen
Jick Yu
Mei Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/965,373 external-priority patent/US6936906B2/en
Priority claimed from US09/965,369 external-priority patent/US20030057526A1/en
Priority claimed from US09/965,370 external-priority patent/US20030059538A1/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of EP1433202A2 publication Critical patent/EP1433202A2/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C30/00—Coating with metallic material characterised only by the composition of the metallic material, i.e. not characterised by the coating process
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • C23C14/5806—Thermal treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention generally relates to an apparatus and method of depositing a barrier layer and a seed layer over the barrier layer. More particularly, the present invention relates to an apparatus and method of depositing a barrier layer and depositing a seed layer comprising copper and another metal over the barrier layer.
  • VLSI very large scale integration
  • ULSI ultra large scale integration
  • the multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
  • the widths of vias, contacts and other features, as well as the dielectric materials between them decrease to sub-micron dimensions (e.g., less than 0.20 micrometers or less), whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increase.
  • Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free and seam-free sub-micron features having high aspect ratios.
  • copper and its alloys have become the metals of choice for sub- micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 ⁇ -cm compared to 3.1 ⁇ -cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
  • Copper metallization can be achieved by a variety of techniques.
  • a typical method generally comprises physical vapor depositing a barrier layer over a feature, physical vapor depositing a copper seed layer over the barrier layer, and then electroplating a copper conductive material layer over the copper seed layer to fill the feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
  • CMP chemical mechanical polishing
  • barrier layers become increasingly important to prevent copper diffusion. Tantalum nitride has been used as a barrier material to prevent the diffusion of copper into underlying layers.
  • tantalum nitride and other barrier layers are poor wetting agents for the deposition of copper thereon which may cause numerous problems. For example, during deposition of a copper seed layer over these barrier layers, the copper seed layer may agglomerate and become discontinuous, which may prevent uniform deposition of a copper conductive material layer (i.e. electroplating of a copper layer) over the copper seed layer.
  • the present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer.
  • the seed layer comprises a copper alloy seed layer deposited over the barrier layer.
  • the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
  • the seed layer comprises a copper alloy seed layer deposited over the barrier layer and a second seed layer deposited over the copper alloy seed layer.
  • the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof of.
  • the second seed layer may comprise a metal, such as undoped copper.
  • the seed layer comprises a first seed layer and a second seed layer.
  • the first seed layer may comprise a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
  • the second seed layer may comprise a metal, such as undoped copper.
  • Figure 1 is a schematic cross-sectional view of one embodiment of a processing system that may be used to form one or more barrier layers by atomic layer deposition.
  • Figure 2A is a schematic cross-sectional view of one embodiment of a substrate having a dielectric layer deposited thereon.
  • Figure 2B is a schematic cross-sectional view of one embodiment of a barrier layer formed over the substrate structure of Figure 2A.
  • Figures 3A-C illustrate one embodiment of alternating chemisorption of monolayers of a tantalum containing compound and a nitrogen containing compound on a portion of substrate at a stage of barrier layer formation.
  • Figure 4 is a schematic cross-sectional view of one embodiment of a process system capable of physical vapor deposition which may be used to deposit a copper alloy seed layer.
  • Figures 5A-C are schematic cross-sectional views of embodiments of depositing a seed layer over a barrier layer of Figure 2B.
  • Figure 6 is a schematic top-view diagram of one example of a multi-chamber processing system.
  • Figure 1 is a schematic cross-sectional view of one exemplary embodiment of a processing system 10 that may be used to form one or more barrier layers by atomic layer deposition in accordance with aspects of the present invention.
  • a processing system 10 may be used to form one or more barrier layers by atomic layer deposition in accordance with aspects of the present invention.
  • other processing systems may also be used.
  • the process system 10 generally includes a process chamber 100, a gas panel 130, a control unit 110, a power supply 106, and a vacuum pump 102.
  • the process chamber 100 generally houses a support pedestal 150, which is used to support a substrate such as a semiconductor wafer 190 within the process chamber 100.
  • the support pedestal 150 may be heated by an embedded heating element 170.
  • the pedestal 150 may be resistively heated by applying an electric current from an AC power supply to the heating element 170.
  • the wafer 190 is, in turn, heated by the pedestal 150, and may be maintained within a desired process temperature range, for example, between about 20°C and about 1000°C depending on the specific process.
  • a temperature sensor 172 such as a thermocouple, may be embedded in the wafer support pedestal 150 to monitor the pedestal temperature.
  • the measured temperature may be used in a feedback loop to control electric current applied to the heating element 170 from the power supply 106, such that the wafer temperature can be maintained or controlled at a desired temperature or within a desired temperature range suitable for a certain process application.
  • the pedestal 150 may also be heated using radiant heat (not shown) or other heating methods.
  • the vacuum pump 102 may be used to evacuate process gases from the process chamber 100 and may be used to help maintain a desired pressure or desired pressure within a pressure range inside the chamber 100.
  • An orifice 120 through a wall of the chamber 100 is used to introduce process gases into the process chamber 100.
  • the size of the orifice 120 conventionally depends on the size of the process chamber 100.
  • the orifice 120 is coupled to the gas panel 130 in part by a valve 125.
  • the gas panel 130 may be configured to receive and then provide a resultant process gas from two or more gas sources 135, 136 to the process chamber 100 through the orifice 120 and the valve 125.
  • the gas sources 135, 136 may store precursors in a liquid phase at room temperature, which are later heated when in the gas panel 130 to convert them to a vapor-gas phase for introduction into the chamber 100.
  • the gas sources 135, 136 may also be adapted to provide precursors through the use of a carrier gas.
  • the gas panel 130 may be further configured to receive and then provide a purge gas from a purge gas source 138 to the process chamber 100 through the orifice 120 and the valve 125.
  • a showerhead 160 may be coupled to the orifice 120 to deliver a process gas, purge gas, or other gas toward the wafer 190 on the support pedestal 150.
  • the showerhead 160 and the support pedestal 150 may serve as spaced apart electrodes for providing an electric field for igniting a plasma.
  • a RF power source 162 may be coupled to the showerhead 160, a RF power source 163 may be coupled to the support pedestal 150, or RF power sources 162, 163 may be coupled to the showerhead 160 and the support pedestal 150, respectively.
  • a matching network 164 may be coupled to the RF power sources 162, 163, which may be coupled to the control unit 110 to control the power supplied to the RF power sources 162, 163.
  • the control unit 110 such as a programmed personal computer, work station computer, and the like, may also be configured to control flow of various process gases through the gas panel 130 as well as the valve 125 during different stages of a wafer process sequence.
  • the control unit 110 comprises a central processing unit (CPU) 112, support circuitry 114, and memory 116 containing associated control software 113.
  • the control unit 110 may be configured to be responsible for automated control of other activities used in wafer processing—such as wafer transport, temperature control, chamber evacuation, among other activities, some of which are described elsewhere herein.
  • the control unit 110 may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors.
  • the CPU 112 may use any suitable memory 116, such as random access memory, read only memory, floppy disk drive, hard disk, or any other form of digital storage, local or remote.
  • Various support circuits may be coupled to the CPU 112 for supporting the system 10.
  • Software routines 113 as required may be stored in the memory 116 or executed by a second computer processor that is remotely located (not shown). Bi-directional communications between the control unit 110 and various other components of the wafer processing system 10 are handled through numerous signal cables collectively referred to as signal buses 118, some of which are illustrated in FIG. 1.
  • Figures 2A- 2B illustrate one exemplary embodiment of barrier layer formation for fabrication of an interconnect structure in accordance with one or more aspects of the present invention.
  • Figure 2A is a schematic cross-sectional view of one embodiment of a substrate 200 having a dielectric layer 202 deposited thereon.
  • the substrate 200 may be a silicon semiconductor wafer, or other material layer, which has been formed on the wafer.
  • the dielectric layer 202 may be an oxide, a silicon oxide, carbon-silicon-oxide, a fluoro-silicon, a porous dielectric, or other suitable dielectric formed and patterned to provide a contact hole or via 202H extending to an exposed surface portion 202T of the substrate 200.
  • the substrate 200 refers to any workpiece upon which film processing is performed, and a substrate structure 250 is used to denote the substrate 200 as well as other mate ⁇ al layers formed on the substrate 200, such as the dielectric layer 202. It is also understood by those with skill in the art that the present invention may be used in a dual damascene process flow.
  • Figure 2B is a schematic cross-sectional view of one embodiment of a barrier layer 204 formed over the substrate structure 250 of Figure 2A by atomic layer deposition (ALD).
  • the barrier layer comprises a tantalum nitride layer.
  • barrier layer materials which may be used include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), and combinations thereof.
  • atomic layer deposition of a tantalum nitride barrier layer comprises sequentially providing a tantalum containing compound and a nitrogen containing compound to a process chamber, such as the process chamber of Figure 1. Sequentially providing a tantalum containing compound and a nitrogen containing compound may result in the alternating chemisorption of monolayers of a tantalum containing compound and of monolayers of a nitrogen containing compound on the substrate structure 250.
  • Figures 3A-C illustrate one embodiment of the alternating chemisorption of monolayers of a tantalum containing compound and a nitrogen containing compound on an exemplary portion of substrate 300 in a stage of integrated circuit fabrication, and more particularly at a stage of barrier layer formation.
  • a monolayer of a tantalum containing compound is chemisorbed on the substrate 300 by introducing a pulse of the tantalum containing compound 305 into a process chamber, such as a process chamber shown in Figure 1.
  • the chemisorption processes used to absorb the monolayer of the tantalum containing compound 305 are self-limiting in that only one monolayer may be chemisorbed onto the surface of the substrate 300 during a given pulse because the surface of the substrate has a finite number of sites for chemisorbing the tantalum containing compound. Once the finite number of sites are occupied by the tantalum containing compound 305, further chemisorportion of any tantalum containing compound will be blocked.
  • the tantalum containing compound 305 typically comprises tantalum atoms 310 with one or more reactive species 315.
  • the tantalum containing compound may be a tantalum based organo-metallic precursor or a derivative thereof.
  • the organo-metallic precursor is pentadimethylamino- tantalum (PDMAT; Ta(NMe 2 )s).
  • PDMAT may be used to advantage for a number of reasons. PDMAT is relatively stable. PDMAT has an adequate vapor pressure which makes it easy to deliver. In particular, PDMAT may be produced with a low halide content.
  • the halide content of PDMAT may be produced with a halide content of less than 100 ppm, and may even be produced with a halide content of less than 30 ppm or even less than 5 ppm.
  • an organo-metallic precursor with a low halide content is beneficial because halides (such as chlorine) incorporated in the barrier layer may attack the copper layer deposited thereover.
  • the tantalum containing compounds may be other organo-metallic precursors or derivatives thereof such as, but not limited to pentaethylmethylamino-tantalum (PEMAT; Ta[N(C 2 H5CH3) 2 ]5), pentadiethylamino-tantalum (PDEAT; Ta(NEt 2 ) 5 ,) > an any and all of derivatives of PEMAT, PDEAT, or PDMAT.
  • Other tantalum containing compounds include without limitation TBTDET (Ta(NEt 2 )3NC 4 H 9 or C ⁇ 6 H 39 N 4 Ta) and tantalum halides, for example TaX 5 where X is fluorine (F), bromine (Br) or chlorine (CI), and derivatives thereof.
  • the tantalum containing compound may be provided as a gas or may be provided with the aid of a carrier gas.
  • carrier gases include, but are not limited to, helium (He), argon (Ar), nitrogen (N 2 ), and hydrogen
  • tantalum containing compound After the monolayer of the tantalum containing compound is chemisorbed onto the substrate 300, excess tantalum containing compound is removed from the process chamber by introducing a pulse of a purge gas thereto.
  • purge gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N 2 ), hydrogen (H 2 ), and other gases.
  • a pulse of a nitrogen containing compound 325 is introduced into the process chamber.
  • the nitrogen containing compound 325 may be provided alone or may be provided with the aid of a carrier gas.
  • the nitrogen containing compound 325 may comprise nitrogen atoms 330 with one or more reactive species 335.
  • the nitrogen containing compound preferably comprises ammonia gas (NH 3 ).
  • nitrogen containing compounds may be used which include, but are not limited to, N x H y with x and y being integers (e.g., hydrazine (N 2 H 4 )), dimethyl hydrazine ((CH 3 ) 2 N2H 2 ), t- butylhydrazine (C H 9 N 2 H 3 ) phenylhydrazine (C 6 H 5 N 2 H3), other hydrazine derivatives, a nitrogen plasma source (e.g., N 2 , N 2 /H 2 , NH 3 , or a N 2 H 4 plasma), 2,2'-azoisobutane ((CH 3 ) 6 C 2 N 2 ), ethylazide (C 2 H 5 N 3 ), and other suitable gases.
  • a carrier gas may be used to deliver the nitrogen containing compound if necessary.
  • a monolayer of the nitrogen containing compound 325 may be chemisorbed on the monolayer of the tantalum containing compound 305.
  • the composition and structure of precursors on a surface during atomic-layer deposition (ALD) is not precisely known. Not wishing to be bound by theory, it is believed that the chemisorbed monolayer of the nitrogen containing compound 325 reacts with the monolayer of the tantalum containing compound 305 to form a tantalum nitride layer 309.
  • the reactive species 315, 335 form by-products 340 that are transported from the substrate surface by the vacuum system.
  • the reaction of the nitrogen containing compound 325 with the tantalum containing compound 305 is self-limited since only one monolayer of the tantalum containing compound 305 was chemisorbed onto the substrate surface.
  • the precursors may be in an intermediate state when on a surface of the substrate.
  • the deposited tantalum nitride layer may also contain more than simply elements of tantalum (Ta) or nitrogen (N); rather, the tantalum nitride layer may also contain more complex molecules having carbon (C), hydrogen (H), and/or oxygen (O).
  • any excess nitrogen containing compound is removed from the process chamber by introducing another pulse of the purge gas therein.
  • the tantalum nitride layer deposition sequence of alternating chemisorption of monolayers of the tantalum containing compound and of the nitrogen containing compound may be repeated, if necessary, until a desired tantalum nitride thickness is achieved.
  • the tantalum nitride layer formation is depicted as starting with the chemisorption of a monolayer of a tantalum containing compound on the substrate followed by a monolayer of a nitrogen containing compound.
  • the tantalum nitride layer formation may start with the chemisorption of a monolayer of a nitrogen containing compound on the substrate followed by a monolayer of the tantalum containing compound.
  • a pump evacuation alone between pulses of reactant gases may be used to prevent mixing of the reactant gases.
  • the time duration for each pulse of the tantalum containing compound, the nitrogen containing compound, and the purge gas is variable and depends on the volume capacity of a deposition chamber employed as well as a vacuum system coupled thereto. For example, (1) a lower chamber pressure of a gas will require a longer pulse time; (2) a lower gas flow rate will require a longer time for chamber pressure to rise and stabilize requiring a longer pulse time; and (3) a large-volume chamber will take longer to fill, longer for chamber pressure to stabilize thus requiring a longer pulse time. Similarly, time between each pulse is also variable and depends on volume capacity of the process chamber as well as the vacuum system coupled thereto.
  • the time duration of a pulse of the tantalum containing compound or the nitrogen containing compound should be long enough for chemisorption of a monolayer of the compound.
  • the pulse time of the purge gas should be long enough to remove the reaction by-products and/or any residual materials remaining in the process chamber.
  • a pulse time of about 1.0 second or less for a tantalum containing compound and a pulse time of about 1.0 second or less for a nitrogen containing compound are typically sufficient to chemisorb alternating monolayers on a substrate.
  • a pulse time of about 1.0 second or less for a purge gas is typically sufficient to remove reaction by-products as well as any residual materials remaining in the process chamber.
  • a longer pulse time may be used to ensure chemisorption of the tantalum containing compound and the nitrogen containing compound and to ensure removal of the reaction by-products.
  • the substrate may be maintained approximately below a thermal decomposition temperature of a selected tantalum containing compound.
  • An exemplary heater temperature range to be used with tantalum containing compounds identified herein is approximately between about 20°C and about 500°C at a chamber pressure less than about 100 torr, preferably less than 50 torr.
  • the heater temperature is preferably between about 100°C and about 300°C, more preferably between about 175°C and 250°C.
  • a temperature above a thermal decomposition temperature may be used. However, the temperature should be selected so that more than 50 percent of the deposition activity is by chemisorption processes.
  • a temperature above a thermal decomposition temperature may be used in which the amount of decomposition during each precursor deposition is limited so that the growth mode will be similar to an atomic layer deposition growth mode.
  • One exemplary process of depositing a tantalum nitride layer by atomic layer deposition in a process chamber comprises sequentially providing pentadimethylamino-tantalum (PDMAT) at a flow rate between about 100 seem and about 1000 seem, and preferably between about 200 seem and 500 seem, for a time period of about 1.0 second or less, providing ammonia at a flow rate between about 100 seem and about 1000 seem, preferably between about 200 seem and 500 seem, for a time period of about 1.0 second or less, and a purge gas at a flow rate between about 100 seem and about 1000 seem, preferably between about 200 seem and 500 seem for a time period of about 1.0 second or less.
  • PDMAT pentadimethylamino-tantalum
  • the heater temperature preferably is maintained between about 100°C and about 300°C at a chamber pressure between about 1.0 and about 5.0 torr. This process provides a tantalum nitride layer in a thickness between about 0.5 A and about 1.0 A per cycle. The alternating sequence may be repeated until a desired thickness is achieved.
  • the barrier layer such as a tantalum nitride barrier layer
  • the barrier layer is deposited to a sidewall coverage of about 50 A or less.
  • the barrier layer is deposited to a sidewall coverage of about 20 A or less.
  • the barrier layer is deposited to a sidewall coverage of about 10 A or less.
  • a barrier layer with a thickness of about 10 A or less is believed to be a sufficient barrier layer to prevent copper diffusion.
  • a thin barrier layer may be used to advantage in filling sub-micron and smaller features having high aspect ratios.
  • a barrier layer having a sidewall coverage of greater than 50 A may be used.
  • the barrier layer may be further plasma annealed.
  • the barrier lay may be plasma annealed with an argon plasma or an argon/hydrogen plasma.
  • the RF power supplied to an RF electrode may be between about 100 W and about 2000 W, preferably between about 500 W and about 1000 W for a 200 mm diameter substrate and preferably between about 1000 W and about 2000 W for a 300 mm diameter substrate.
  • the pressure of the chamber may be less than 100 torr, preferably between 0.1 torr and about 5 torr, and more preferably between about 1 torr and 3 torr.
  • the heater temperature may be between about 20°C and about 500°C.
  • the plasma anneal may be performed after a cycle, a plurality of cycles, or after formation of the barrier layer.
  • Embodiments of atomic layer deposition of the barrier layer have been described above as chemisorption of a monolayer of reactants on a substrate.
  • the present invention also includes embodiments in which the reactants are deposited to more or less than a monolayer.
  • the present invention also includes embodiments in which the reactants are not deposited in a self-limiting manner.
  • the present invention also includes embodiments in which the barrier layer 204 is deposited in mainly a chemical vapor deposition process in which the reactants are delivered sequentially or simultaneously.
  • the present invention also include embodiments in which the barrier layer 204 is deposited in a physical vapor deposition process in which the target comprises the material to be deposited (i.e. a tantalum target in a nitrogen atmosphere for the deposition of tantalum nitride).
  • the seed layer may be deposited by any suitable technique such as physical vapor deposition, chemical vapor deposition, electroless deposition, or a combination of techniques.
  • Suitable physical vapor deposition techniques for the deposition of the seed layer include techniques such as high density plasma physical vapor deposition (HDP PVD) or collimated or long throw sputtering.
  • HDP PVD high density plasma physical vapor deposition
  • One type of HDP PVD is self-ionized plasma physical vapor deposition.
  • An example of a chamber capable of self-ionized plasma physical vapor deposition of a seed layer is a SIPTM chamber, available from Applied Materials, Inc. of Santa Clara, California. Exemplary embodiments of chambers capable of self-ionized physical vapor deposition are described in U.S. Patent No. 6,183,614, entitled "Rotating Sputter Magnetron Assembly," which is herein incorporated by reference to the extent not inconsistent with the present invention.
  • Figure 4 is a schematic cross-sectional view of one embodiment of a process system 410 capable of physical vapor deposition which may be used to deposit a seed layer.
  • a process system 410 capable of physical vapor deposition which may be used to deposit a seed layer.
  • other processing systems and other types of physical vapor deposition may also be used.
  • the process system 410 includes a vacuum chamber 412 sealed to a PVD target 414 composed of the material to be sputter deposited on a wafer 416 held on a heater pedestal 418.
  • a shield 420 held within the chamber protects the walls of the chamber 412 from the sputtered material and provides the anode grounding plane.
  • a selectable DC power supply 422 negatively biases the target 414 with respect to the shield 420.
  • a gas source 424 supplies a sputtering working gas, typically the chemically inactive gas argon, to the chamber 412 through a mass flow controller 426.
  • a vacuum system 428 maintains the chamber at a low pressure.
  • a computer-based controller 430 controls the reactor including the DC power supply 422 and the mass flow controllers 426.
  • the DC voltage between the target 414 and the shield 420 ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target 414.
  • the ions strike the target 414 at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target 414. Some of the target particles strike the wafer 416 and are thereby deposited on it, thereby forming a film of the target material.
  • a magnetron 432 is positioned in back of the target 414. It has opposed magnets 434, 436 creating a magnetic field within the chamber in the neighborhood of the magnets 434, 436.
  • the magnetic field traps electrons and, for charge neutrality, the ion density also increases to form a high- density plasma region 438 within the chamber adjacent to the magnetron 432.
  • the magnetron 432 usually rotates about a rotational axis 458 at the center of the target 414 to achieve full coverage in sputtering of the target 414.
  • the pedestal 418 develops a DC self-bias, which attracts ionized sputtered particles from the plasma across the plasma sheath adjacent to the wafer 416.
  • the effect can be accentuated with additional DC or RF biasing of the pedestal electrode 418 to additionally accelerate the ionized particles extracted across the plasma sheath towards the wafer 416, thereby controlling the directionality of sputter deposition.
  • Figure 5A- 5C are schematic cross-sectional view of exemplary embodiments of depositing a seed layer over a barrier layer.
  • One embodiment, as shown in Figure 5A, comprises depositing a copper alloy seed layer 502 over a barrier layer 204 of Figure 2B and depositing a copper conductive material layer 506 over the copper alloy seed layer 502 to fill the feature.
  • the term "copper conductive material layer" as used in the specification is defined as a layer comprising copper or a copper alloy.
  • the copper alloy seed layer 502 comprises a copper metal alloy that aids in subsequent deposition of materials thereover.
  • the copper alloy seed layer 502 may comprise copper and a second metal, such as aluminum, magnesium, titanium, zirconium, tin, other metals, and combinations thereof.
  • the second metal preferably comprises aluminum, magnesium, titanium, and combinations thereof and more preferably comprises aluminum.
  • the copper alloy seed layer comprises a second metal in a concentration having the lower limits of about 0.001 atomic percent, about 0.01 atomic percent, or about 0.1 atomic percent and having the upper limits of about 5.0 atomic percent, about 2.0 atomic percent, or about 1.0 atomic percent.
  • concentration of the second metal in a range from any lower limit to any upper limit is within the scope of the present invention.
  • the concentration of the second metal in the copper alloy seed layer 502 is preferably less than about 5.0 atomic percent to lower the resistance of the copper alloy seed layer 502.
  • the term "layer" as used in the specification is defined as one or more layers.
  • the copper alloy seed layer 502 may comprise a plurality of layers in which the total composition of the layers comprises copper and the second metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent.
  • examples of a copper alloy seed layer 502 comprising a plurality of layers in which the total composition of the layers comprises copper and the second metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent may comprises a first seed layer comprising the second metal and a second seed layer comprising copper, may comprise a first seed layer comprising a copper/second metal alloy and a second seed layer comprising a copper/second metal alloy, or may comprise a first seed layer comprising a copper/second metal alloy and a second seed layer comprising copper, etc.
  • the copper alloy seed layer 502 is deposited to a thickness of at least about a 5 A coverage of the sidewalls of the feature or to a thickness of at least a continuous coverage of the sidewalls of the feature. In one embodiment, the copper alloy seed layer 502 is deposited to a thickness at the field areas between about 10 A and about 2000 A, preferably between about 500 A and about 1000 A for a copper alloy seed layer 502 deposited by physical vapor deposition.
  • FIG. 5B Another embodiment, as shown in Figure 5B, comprises depositing a copper alloy seed layer 512 over a barrier layer 204 of Figure 2B, depositing a second seed layer 514 over the copper alloy seed layer 512, and depositing a copper conductive material layer 516 over the second seed layer 514 to fill the feature.
  • the copper alloy seed layer 512 comprises a copper metal alloy that aids in subsequent deposition of materials thereover.
  • the copper alloy seed layer 512 may comprise copper and a second metal, such as aluminum, magnesium, titanium, zirconium, tin, other metals, and combinations thereof.
  • the second metal preferably comprises aluminum, magnesium, titanium, and combinations thereof and more preferably comprises aluminum.
  • the copper alloy seed layer comprises a second metal in a concentration having the lower limits of about 0.001 atomic percent, about 0.01 atomic percent, or about 0.1 atomic percent and having the upper limits of about 5.0 atomic percent, about 2.0 atomic percent, or about 1.0 atomic percent.
  • concentration of the second metal in a range from any lower limit to any upper limit is within the scope of the present invention.
  • the second seed layer 514 comprises undoped copper (i.e. pure copper).
  • a second seed layer 514 comprising undoped copper is used because of its lower electrical resistivity than a copper alloy seed layer 512 of the same thickness and because of its higher resistance to surface oxidation.
  • the copper alloy seed layer 512 may be deposited to a thickness of less than a monolayer (i.e. a sub-monolayer thickness or a discontinuous layer) over the sidewalls of the feature.
  • the combined thickness of the copper alloy seed layer 512 and the second seed layer 514 at the field areas is between about 10 A and about 2000 A, preferably between about 500 A and about 1000 A for a copper alloy seed layer 512 and second seed layer 514 deposited by physical vapor deposition.
  • FIG. 5C Another embodiment, as shown in Figure 5C, comprises depositing a first seed layer 523 over a barrier layer 204 of Figure 2B, depositing a second seed layer 524 over the first seed layer 523, and depositing a copper conductive material layer 526 over the second seed layer 524 to fill the feature.
  • the first seed layer 523 comprises a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
  • the first seed layer 523 comprises aluminum.
  • the second seed layer 514 comprises undoped copper (i.e. pure copper).
  • the first seed layer 523 may be deposited to a thickness of less than a monolayer (i.e. a sub-monolayer thickness or a discontinuous layer) over the sidewalls of the feature. In one embodiment, the first seed layer is deposited to a thickness of less than about 50 A sidewall coverage, preferably less than about 40 A sidewall coverage, to lower the total resistance of the combined seed layer.
  • the combined thickness of the first seed layer 523 and the second seed layer 524 at the field areas is between about 10 A and about 2000 A, preferably between about 500 A and about 1000 A for a first seed layer 523 and second seed layer 524 deposited by physical vapor deposition.
  • the copper alloy seed layer 502, 512, the first seed layer 523, or the second seed layer 514, 524 may be deposited by such techniques including physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless deposition, or a combination of techniques.
  • a chamber such as the chamber 412 as described in Figure 4
  • a target such as target 414
  • the target may comprise copper and a second metal, such as aluminum, magnesium, titanium, zirconium, tin, other metals, and combinations thereof.
  • the second metal preferably comprises aluminum.
  • the target comprises a second metal in a concentration having the lower limits of about 0.001 atomic percent, about 0.01 atomic percent, or about 0.1 atomic percent and having the upper limits of about 5.0 atomic percent, about 2.0 atomic percent, or about 1.0 atomic percent.
  • concentration of the second metal in a range from any lower limit to any upper limit is within the scope of the present invention.
  • the target comprises a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. If a seed layer is deposited by chemical vapor deposition or atomic layer deposition, a chamber, such as the chamber as described in Figure 1 , is adapted to deliver suitable metal precursors of the metal or metal alloy to be deposited.
  • One exemplary process of depositing a seed layer by physical vapor deposition in a process chamber comprises utilizing a target of the material to be deposited.
  • the process chamber may be maintained at a pressure of between about 0.1 mtorr and about 10 mtorr.
  • the target may be DC-biased at a power between about 5 kW and about 100 kW.
  • the pedestal may be RF-biased at a power between about 0 and about 1000 W.
  • the pedestal may be unheated (i.e. room temperature).
  • the copper conductive material layer 506, 516, 526 may be deposited by electroplating, physical vapor deposition, chemical vapor deposition, electroless deposition or a combination of techniques.
  • the copper conductive material layer 506, 516, 526 is deposited by electroplating because of the bottom-up growth which may be obtained in electroplating processes.
  • An exemplary electroplating method is described in United States Patent No. 6,113,771, entitled “Electro Deposition Chemistry", issued September 5, 2000, and is incorporated herein by reference to the extent not inconsistent with this invention.
  • a copper alloy seed layer such as a copper- aluminum seed layer
  • the copper alloy seed layer acts as a good wetting agent to materials deposited thereon.
  • concentration of the copper and other metals of the copper seed layer provides a seed layer with good wetting properties and good electrical characteristics.
  • a copper alloy seed layer having a total thickness of less than a monolayer may be used as long as a second seed layer, such as an undoped seed layer, is deposited thereover to provide at least a combined continuous seed layer since the copper alloy seed layer provides an improved interface for adhesion of materials thereon.
  • a metal seed layer such as an aluminum seed layer
  • a metal seed layer such as an aluminum seed layer, having a total thickness of less than a monolayer may be used since the metal layer provides an improved interface for adhesion of materials thereon, such as an undoped copper seed layer deposited over the metal layer.
  • the seed layers as disclosed herein have improved adhesion over barrier layers and have good wetting properties for materials deposited thereover, such as a copper conductive material layer deposited thereover. Therefore, the seed layers increase device reliability by reducing the likelihood of agglomeration, dewetting, or the formation of voids in the copper conductive material layer during deposition of the copper conductive material layer, during subsequent processing at high temperatures, and during thermal stressing of the devices during use of the devices.
  • the seed layers may be used with any barrier layer and may be used with barrier layers deposited by any deposition technique.
  • the seed layers also may be deposited by any deposition technique.
  • a conductive material layer such as a copper conductive material layer, may be deposited over the seed layers by any deposition technique.
  • the present process may be used to advantage in filling apertures having less than about 0.2 micron opening width and having an aspect ratio of greater than about 4:1 , about 6:1; or about 10:1.
  • the processes as disclosed herein may be carried out in separate chambers or may be carried out in a multi-chamber processing system having a plurality of chambers.
  • Figure 6 is a schematic top-view diagram of one example of a multi- chamber processing system 600 which may be adapted to perform processes as disclosed herein.
  • the apparatus is an ENDURATM system and is commercially available from Applied Materials, Inc., of Santa Clara, California.
  • a similar multi- chamber processing system is disclosed in U.S. Patent No.
  • the system 600 generally includes load lock chambers 602, 604 for the transfer of substrates into and out from the system 600.
  • the load lock chambers 602, 604 may "pump down" the substrates introduced into the system 600.
  • a first robot 610 may transfer the substrates between the load lock chambers 602, 604, processing chambers 612, 614, transfer chambers 622, 624, and other chambers 616, 618.
  • a second robot 630 may transfer the substrates between processing chambers 632, 634, 636, 638 and the transfer chambers 622, 624. Processing chambers 612, 614, 632, 634, 636, 638 may be removed from the system 600 if not necessary for the particular process to be performed by the system 600.
  • the system 600 is configured so that processing chamber 634 is adapted to deposit a copper alloy seed layer 502.
  • the processing chamber 634 for depositing a copper alloy seed layer 502 may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber.
  • the system 600 may be further configured so that processing chamber 632 is adapted to deposit a barrier layer 204 in which the copper alloy seed layer 502 is deposited over the barrier layer.
  • the processing chamber 632 for depositing the barrier layer 204 may be an atomic layer deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber.
  • the processing chamber 632 may be an atomic layer deposition chamber, such as the chamber shown in Figure 1
  • the processing chamber 634 may be a physical vapor deposition chamber, such as the chamber shown in Figure 4.
  • the system 600 is configured so that processing chamber 634 is adapted to deposit a copper alloy seed layer 512 and so that processing chamber 636 is adapted to deposit a second seed layer 514 over the copper alloy seed layer 512.
  • the processing chamber 634 for depositing a copper alloy seed layer 512 and/or the processing chamber 636 for depositing a second seed layer may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber.
  • the system 600 may be further configured so that processing chamber 632 is adapted to deposit a barrier layer 204 in which the copper alloy seed layer 512 is deposited over the barrier layer.
  • processing chamber 632 for depositing the barrier layer 204 may be an atomic layer deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber.
  • processing chamber 632 may be an atomic layer deposition chamber, such as the chamber shown in Figure 1
  • processing chambers 634, 636 may be physical vapor deposition chambers, such as the chamber shown in Figure 4.
  • the system 600 is configured so that processing chamber 634 is adapted to deposit a metal seed layer 523 and so that processing chamber 636 is adapted to deposit a second seed layer 524 over the metal seed layer 523.
  • the processing chamber 634 for depositing a metal seed layer 523 and/or the processing chamber 636 for depositing a second seed layer 524 may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber.
  • the system may be further configured so that processing chamber 632 is adapted to deposit a barrier layer 204 in which the metal seed layer 523 is deposited over the barrier layer.
  • processing chamber 632 for depositing the barrier layer 204 may be an atomic layer deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber.
  • processing chamber 632 may be an atomic layer deposition chamber, such as the chamber shown in Figure 1
  • processing chambers 634, 636 may be physical vapor deposition chambers, such as the chamber shown in Figure 4.
  • deposition of a barrier layer 204 and a seed layer may be performed in a multi-chamber processing system under vacuum to prevent air and other impurities from being incorporated into the layers and to maintain the seed structure over the barrier layer 204.
  • system 600 is within the scope of the present invention.
  • position of a particular processing chamber on the system may be altered.
  • a single processing chamber may be adapted to deposit two different layers.
  • a TaN layer was deposited over a substrate by atomic layer deposition to a thickness of about 20 A.
  • a seed layer was deposited over the TaN layer by physical vapor deposition to a thickness of about 100 A.
  • the seed layer comprised either 1) undoped copper deposited utilizing a target comprising undoped copper, 2) a copper alloy comprising aluminum in a concentration of about 2.0 atomic percent deposited utilizing a copper-aluminum target comprising aluminum in a concentration of about 2.0 atomic percent, 3) a copper alloy comprising tin in a concentration of about 2.0 atomic percent deposited utilizing a copper-tin target comprising tin in a concentration of about 2.0 atomic percent, or 4) a copper alloy comprising zirconium in a concentration of about 2.0 atomic percent deposited utilizing a copper-zirconium target comprising zirconium in a concentration of about 2.0 atomic percent.
  • the resulting substrate was annealed at a temperature of about 380°C for a time period of
  • Copper-aluminum alloy films comprising about 2.0 atomic percent of aluminum were deposited on different substrates by physical vapor deposition utilizing a copper-aluminum target comprising aluminum in a concentration of 2.0 atomic percent.
  • the resulting substrates included 1 ) a copper-aluminum layer deposited to a thickness of about 50 A over an ALD TaN layer, 2) a copper-aluminum layer deposited to a thickness of about 50 A over about a 100 A Ta layer, 3) a copper- aluminum layer deposited to a thickness of about 100 A over an ALD TaN layer, 4) a copper-aluminum layer deposited to a thickness of about 100 A over a silicon nitride (SiN) layer, and 5) a copper-aluminum layer deposited to a thickness of about 100 A over a silicon oxide layer.
  • SiN silicon nitride
  • the resulting substrates were annealed at a temperature of about 380°C for a time period of about 15 minutes in a nitrogen (N 2 ) and hydrogen (H 2 ) ambient. Scanning electron microscope photographs showed that there was no significant agglomeration of the copper-aluminum alloy over the various substrates.
  • Copper-aluminum alloy films comprising about 2.0 atomic percent of aluminum were deposited by physical vapor deposition utilizing a copper-aluminum target comprising aluminum in a concentration of 2.0 atomic percent to either a 50 A or 100 A thickness over an ALD TaN layer.
  • the resulting substrates were annealed at a temperature of about 380°C, about 450°C, or about 500°C for a time period of about 15 minutes in a nitrogen (N 2 ) and hydrogen (H 2 ) ambient. Scanning electron microscope photographs showed that there was no significant agglomeration of the copper-aluminum alloy for substrates annealed at temperatures of about 380°C or about 450°C.
  • the copper-aluminum alloy showed some dewetting began to occur for substrates annealed at a temperature of about 500°C.
  • Copper-aluminum alloy films comprising about 2.0 atomic percent of aluminum were deposited by physical vapor deposition utilizing a copper-aluminum target comprising aluminum in a concentration of about 2.0 atomic percent to either about a 50 A or about a 100 A thickness over an ALD TaN layer.
  • the resulting substrates were annealed at a temperature of about 450°C for a time period of about 30 minutes in a nitrogen (N 2 ) and hydrogen (H 2 ) ambient. Scanning electron microscope photographs showed that there was no significant agglomeration of the copper- aluminum alloy for substrates annealed at a temperature of about 450°C for a time period of about 30 minutes.

Abstract

The present invention generally relates to filling of a feature by depositing a barrier layer (1204), depositing a seed layer (1502) over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper alloy seed layer (1512) deposited over the barrier layer and a second seed layer (1514) deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer. The first seed layer may comprise a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. The second seed layer may comprise a metal, such as undoped copper.

Description

Integration of Barrier Layer and Seed Layer
Technical Field
The present invention generally relates to an apparatus and method of depositing a barrier layer and a seed layer over the barrier layer. More particularly, the present invention relates to an apparatus and method of depositing a barrier layer and depositing a seed layer comprising copper and another metal over the barrier layer.
Background Art
Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions (e.g., less than 0.20 micrometers or less), whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increase. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free and seam-free sub-micron features having high aspect ratios.
Currently, copper and its alloys have become the metals of choice for sub- micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
Copper metallization can be achieved by a variety of techniques. A typical method generally comprises physical vapor depositing a barrier layer over a feature, physical vapor depositing a copper seed layer over the barrier layer, and then electroplating a copper conductive material layer over the copper seed layer to fill the feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
However, one problem with the use of copper is that copper diffuses into silicon, silicon dioxide, and other dielectric materials which may compromise the integrity of devices. Therefore, conformal barrier layers become increasingly important to prevent copper diffusion. Tantalum nitride has been used as a barrier material to prevent the diffusion of copper into underlying layers. One problem with prior uses of tantalum nitride and other barrier layers, however, is that these barrier layers are poor wetting agents for the deposition of copper thereon which may cause numerous problems. For example, during deposition of a copper seed layer over these barrier layers, the copper seed layer may agglomerate and become discontinuous, which may prevent uniform deposition of a copper conductive material layer (i.e. electroplating of a copper layer) over the copper seed layer. In another example, subsequent processing at high temperatures of a substrate structure having a copper layer deposited over these barrier layers may cause dewetting and the formation of voids in the copper layer. In still another example, thermal stressing of formed devices through use of the devices may cause the generation of voids in the copper layer and device failure. Thus, there is a need for an improved interconnect structure and method of depositing the interconnect structure. Disclosure of Invention
The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer and a second seed layer deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof of. The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer. The first seed layer may comprise a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. The second seed layer may comprise a metal, such as undoped copper.
Brief Description of Drawings
So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Figure 1 is a schematic cross-sectional view of one embodiment of a processing system that may be used to form one or more barrier layers by atomic layer deposition.
Figure 2A is a schematic cross-sectional view of one embodiment of a substrate having a dielectric layer deposited thereon. Figure 2B is a schematic cross-sectional view of one embodiment of a barrier layer formed over the substrate structure of Figure 2A.
Figures 3A-C illustrate one embodiment of alternating chemisorption of monolayers of a tantalum containing compound and a nitrogen containing compound on a portion of substrate at a stage of barrier layer formation.
Figure 4 is a schematic cross-sectional view of one embodiment of a process system capable of physical vapor deposition which may be used to deposit a copper alloy seed layer.
Figures 5A-C are schematic cross-sectional views of embodiments of depositing a seed layer over a barrier layer of Figure 2B.
Figure 6 is a schematic top-view diagram of one example of a multi-chamber processing system.
Detailed Description of the Preferred Embodiment
Process Chamber Adapted for Depositing a Barrier Layer
Figure 1 is a schematic cross-sectional view of one exemplary embodiment of a processing system 10 that may be used to form one or more barrier layers by atomic layer deposition in accordance with aspects of the present invention. Of course, other processing systems may also be used.
The process system 10 generally includes a process chamber 100, a gas panel 130, a control unit 110, a power supply 106, and a vacuum pump 102. The process chamber 100 generally houses a support pedestal 150, which is used to support a substrate such as a semiconductor wafer 190 within the process chamber 100.
In the chamber 100, the support pedestal 150 may be heated by an embedded heating element 170. For example, the pedestal 150 may be resistively heated by applying an electric current from an AC power supply to the heating element 170. The wafer 190 is, in turn, heated by the pedestal 150, and may be maintained within a desired process temperature range, for example, between about 20°C and about 1000°C depending on the specific process. A temperature sensor 172, such as a thermocouple, may be embedded in the wafer support pedestal 150 to monitor the pedestal temperature. For example, the measured temperature may be used in a feedback loop to control electric current applied to the heating element 170 from the power supply 106, such that the wafer temperature can be maintained or controlled at a desired temperature or within a desired temperature range suitable for a certain process application. The pedestal 150 may also be heated using radiant heat (not shown) or other heating methods.
The vacuum pump 102 may be used to evacuate process gases from the process chamber 100 and may be used to help maintain a desired pressure or desired pressure within a pressure range inside the chamber 100. An orifice 120 through a wall of the chamber 100 is used to introduce process gases into the process chamber 100. The size of the orifice 120 conventionally depends on the size of the process chamber 100.
The orifice 120 is coupled to the gas panel 130 in part by a valve 125. The gas panel 130 may be configured to receive and then provide a resultant process gas from two or more gas sources 135, 136 to the process chamber 100 through the orifice 120 and the valve 125. The gas sources 135, 136 may store precursors in a liquid phase at room temperature, which are later heated when in the gas panel 130 to convert them to a vapor-gas phase for introduction into the chamber 100. The gas sources 135, 136 may also be adapted to provide precursors through the use of a carrier gas. The gas panel 130 may be further configured to receive and then provide a purge gas from a purge gas source 138 to the process chamber 100 through the orifice 120 and the valve 125. A showerhead 160 may be coupled to the orifice 120 to deliver a process gas, purge gas, or other gas toward the wafer 190 on the support pedestal 150.
The showerhead 160 and the support pedestal 150 may serve as spaced apart electrodes for providing an electric field for igniting a plasma. A RF power source 162 may be coupled to the showerhead 160, a RF power source 163 may be coupled to the support pedestal 150, or RF power sources 162, 163 may be coupled to the showerhead 160 and the support pedestal 150, respectively. A matching network 164 may be coupled to the RF power sources 162, 163, which may be coupled to the control unit 110 to control the power supplied to the RF power sources 162, 163.
The control unit 110, such as a programmed personal computer, work station computer, and the like, may also be configured to control flow of various process gases through the gas panel 130 as well as the valve 125 during different stages of a wafer process sequence. Illustratively, the control unit 110 comprises a central processing unit (CPU) 112, support circuitry 114, and memory 116 containing associated control software 113. In addition to control of process gases through the gas panel 130, the control unit 110 may be configured to be responsible for automated control of other activities used in wafer processing— such as wafer transport, temperature control, chamber evacuation, among other activities, some of which are described elsewhere herein.
The control unit 110 may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The CPU 112 may use any suitable memory 116, such as random access memory, read only memory, floppy disk drive, hard disk, or any other form of digital storage, local or remote. Various support circuits may be coupled to the CPU 112 for supporting the system 10. Software routines 113 as required may be stored in the memory 116 or executed by a second computer processor that is remotely located (not shown). Bi-directional communications between the control unit 110 and various other components of the wafer processing system 10 are handled through numerous signal cables collectively referred to as signal buses 118, some of which are illustrated in FIG. 1.
Barrier Laver Formation
The exemplary chamber as described in Figure 1 may be used to implement the following process. Of course, other process chambers may be used. Figures 2A- 2B illustrate one exemplary embodiment of barrier layer formation for fabrication of an interconnect structure in accordance with one or more aspects of the present invention. Figure 2A is a schematic cross-sectional view of one embodiment of a substrate 200 having a dielectric layer 202 deposited thereon. Depending on the processing stage, the substrate 200 may be a silicon semiconductor wafer, or other material layer, which has been formed on the wafer. The dielectric layer 202 may be an oxide, a silicon oxide, carbon-silicon-oxide, a fluoro-silicon, a porous dielectric, or other suitable dielectric formed and patterned to provide a contact hole or via 202H extending to an exposed surface portion 202T of the substrate 200. For purposes of clarity, the substrate 200 refers to any workpiece upon which film processing is performed, and a substrate structure 250 is used to denote the substrate 200 as well as other mateπal layers formed on the substrate 200, such as the dielectric layer 202. It is also understood by those with skill in the art that the present invention may be used in a dual damascene process flow.
Figure 2B is a schematic cross-sectional view of one embodiment of a barrier layer 204 formed over the substrate structure 250 of Figure 2A by atomic layer deposition (ALD). Preferably, the barrier layer comprises a tantalum nitride layer. Examples of other barrier layer materials which may be used include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), and combinations thereof.
For clarity reasons, deposition of the barrier layer will be described in more detail in reference to one embodiment of the barrier layer comprising a tantalum nitride barrier layer. In one aspect, atomic layer deposition of a tantalum nitride barrier layer comprises sequentially providing a tantalum containing compound and a nitrogen containing compound to a process chamber, such as the process chamber of Figure 1. Sequentially providing a tantalum containing compound and a nitrogen containing compound may result in the alternating chemisorption of monolayers of a tantalum containing compound and of monolayers of a nitrogen containing compound on the substrate structure 250.
Figures 3A-C illustrate one embodiment of the alternating chemisorption of monolayers of a tantalum containing compound and a nitrogen containing compound on an exemplary portion of substrate 300 in a stage of integrated circuit fabrication, and more particularly at a stage of barrier layer formation. In Figure 3A, a monolayer of a tantalum containing compound is chemisorbed on the substrate 300 by introducing a pulse of the tantalum containing compound 305 into a process chamber, such as a process chamber shown in Figure 1. It is believed that the chemisorption processes used to absorb the monolayer of the tantalum containing compound 305 are self-limiting in that only one monolayer may be chemisorbed onto the surface of the substrate 300 during a given pulse because the surface of the substrate has a finite number of sites for chemisorbing the tantalum containing compound. Once the finite number of sites are occupied by the tantalum containing compound 305, further chemisorportion of any tantalum containing compound will be blocked.
The tantalum containing compound 305 typically comprises tantalum atoms 310 with one or more reactive species 315. In one embodiment, the tantalum containing compound may be a tantalum based organo-metallic precursor or a derivative thereof. Preferably, the organo-metallic precursor is pentadimethylamino- tantalum (PDMAT; Ta(NMe2)s). PDMAT may be used to advantage for a number of reasons. PDMAT is relatively stable. PDMAT has an adequate vapor pressure which makes it easy to deliver. In particular, PDMAT may be produced with a low halide content. The halide content of PDMAT may be produced with a halide content of less than 100 ppm, and may even be produced with a halide content of less than 30 ppm or even less than 5 ppm. Not wishing to be bound by theory, it is believed that an organo-metallic precursor with a low halide content is beneficial because halides (such as chlorine) incorporated in the barrier layer may attack the copper layer deposited thereover.
The tantalum containing compounds may be other organo-metallic precursors or derivatives thereof such as, but not limited to pentaethylmethylamino-tantalum (PEMAT; Ta[N(C2H5CH3)2]5), pentadiethylamino-tantalum (PDEAT; Ta(NEt2)5,)> an any and all of derivatives of PEMAT, PDEAT, or PDMAT. Other tantalum containing compounds include without limitation TBTDET (Ta(NEt2)3NC4H9 or Cι6H39N4Ta) and tantalum halides, for example TaX5 where X is fluorine (F), bromine (Br) or chlorine (CI), and derivatives thereof. The tantalum containing compound may be provided as a gas or may be provided with the aid of a carrier gas. Examples of carrier gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), and hydrogen
(H2).
After the monolayer of the tantalum containing compound is chemisorbed onto the substrate 300, excess tantalum containing compound is removed from the process chamber by introducing a pulse of a purge gas thereto. Examples of purge gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), hydrogen (H2), and other gases.
Referring to Figure 3B, after the process chamber has been purged, a pulse of a nitrogen containing compound 325 is introduced into the process chamber. The nitrogen containing compound 325 may be provided alone or may be provided with the aid of a carrier gas. The nitrogen containing compound 325 may comprise nitrogen atoms 330 with one or more reactive species 335. The nitrogen containing compound preferably comprises ammonia gas (NH3). Other nitrogen containing compounds may be used which include, but are not limited to, NxHy with x and y being integers (e.g., hydrazine (N2H4)), dimethyl hydrazine ((CH3)2N2H2), t- butylhydrazine (C H9N2H3) phenylhydrazine (C6H5N2H3), other hydrazine derivatives, a nitrogen plasma source (e.g., N2, N2/H2, NH3, or a N2H4 plasma), 2,2'-azoisobutane ((CH3)6C2N2), ethylazide (C2H5N3), and other suitable gases. A carrier gas may be used to deliver the nitrogen containing compound if necessary.
A monolayer of the nitrogen containing compound 325 may be chemisorbed on the monolayer of the tantalum containing compound 305. The composition and structure of precursors on a surface during atomic-layer deposition (ALD) is not precisely known. Not wishing to be bound by theory, it is believed that the chemisorbed monolayer of the nitrogen containing compound 325 reacts with the monolayer of the tantalum containing compound 305 to form a tantalum nitride layer 309. The reactive species 315, 335 form by-products 340 that are transported from the substrate surface by the vacuum system. It is believed that the reaction of the nitrogen containing compound 325 with the tantalum containing compound 305 is self-limited since only one monolayer of the tantalum containing compound 305 was chemisorbed onto the substrate surface. In another theory, the precursors may be in an intermediate state when on a surface of the substrate. In addition, the deposited tantalum nitride layer may also contain more than simply elements of tantalum (Ta) or nitrogen (N); rather, the tantalum nitride layer may also contain more complex molecules having carbon (C), hydrogen (H), and/or oxygen (O).
After the monolayer of the nitrogen containing compound 325 is chemisorbed on the monolayer of the tantalum containing compound, any excess nitrogen containing compound is removed from the process chamber by introducing another pulse of the purge gas therein. Thereafter, as shown in Figure 3C, the tantalum nitride layer deposition sequence of alternating chemisorption of monolayers of the tantalum containing compound and of the nitrogen containing compound may be repeated, if necessary, until a desired tantalum nitride thickness is achieved.
In Figures 3A-3C, the tantalum nitride layer formation is depicted as starting with the chemisorption of a monolayer of a tantalum containing compound on the substrate followed by a monolayer of a nitrogen containing compound. Alternatively, the tantalum nitride layer formation may start with the chemisorption of a monolayer of a nitrogen containing compound on the substrate followed by a monolayer of the tantalum containing compound. Furthermore, in an alternative embodiment, a pump evacuation alone between pulses of reactant gases may be used to prevent mixing of the reactant gases.
The time duration for each pulse of the tantalum containing compound, the nitrogen containing compound, and the purge gas is variable and depends on the volume capacity of a deposition chamber employed as well as a vacuum system coupled thereto. For example, (1) a lower chamber pressure of a gas will require a longer pulse time; (2) a lower gas flow rate will require a longer time for chamber pressure to rise and stabilize requiring a longer pulse time; and (3) a large-volume chamber will take longer to fill, longer for chamber pressure to stabilize thus requiring a longer pulse time. Similarly, time between each pulse is also variable and depends on volume capacity of the process chamber as well as the vacuum system coupled thereto. In general, the time duration of a pulse of the tantalum containing compound or the nitrogen containing compound should be long enough for chemisorption of a monolayer of the compound. In general, the pulse time of the purge gas should be long enough to remove the reaction by-products and/or any residual materials remaining in the process chamber.
Generally, a pulse time of about 1.0 second or less for a tantalum containing compound and a pulse time of about 1.0 second or less for a nitrogen containing compound are typically sufficient to chemisorb alternating monolayers on a substrate. A pulse time of about 1.0 second or less for a purge gas is typically sufficient to remove reaction by-products as well as any residual materials remaining in the process chamber. Of course, a longer pulse time may be used to ensure chemisorption of the tantalum containing compound and the nitrogen containing compound and to ensure removal of the reaction by-products.
During atomic layer deposition, the substrate may be maintained approximately below a thermal decomposition temperature of a selected tantalum containing compound. An exemplary heater temperature range to be used with tantalum containing compounds identified herein is approximately between about 20°C and about 500°C at a chamber pressure less than about 100 torr, preferably less than 50 torr. When the tantalum containing gas is PDMAT, the heater temperature is preferably between about 100°C and about 300°C, more preferably between about 175°C and 250°C. In other embodiments, it should be understood that other temperatures may be used. For example, a temperature above a thermal decomposition temperature may be used. However, the temperature should be selected so that more than 50 percent of the deposition activity is by chemisorption processes. In another example, a temperature above a thermal decomposition temperature may be used in which the amount of decomposition during each precursor deposition is limited so that the growth mode will be similar to an atomic layer deposition growth mode.
One exemplary process of depositing a tantalum nitride layer by atomic layer deposition in a process chamber, such as the process chamber of Figure 1 , comprises sequentially providing pentadimethylamino-tantalum (PDMAT) at a flow rate between about 100 seem and about 1000 seem, and preferably between about 200 seem and 500 seem, for a time period of about 1.0 second or less, providing ammonia at a flow rate between about 100 seem and about 1000 seem, preferably between about 200 seem and 500 seem, for a time period of about 1.0 second or less, and a purge gas at a flow rate between about 100 seem and about 1000 seem, preferably between about 200 seem and 500 seem for a time period of about 1.0 second or less. The heater temperature preferably is maintained between about 100°C and about 300°C at a chamber pressure between about 1.0 and about 5.0 torr. This process provides a tantalum nitride layer in a thickness between about 0.5 A and about 1.0 A per cycle. The alternating sequence may be repeated until a desired thickness is achieved.
In one embodiment, the barrier layer, such as a tantalum nitride barrier layer, is deposited to a sidewall coverage of about 50 A or less. In another embodiment, the barrier layer is deposited to a sidewall coverage of about 20 A or less. In still another embodiment, the barrier layer is deposited to a sidewall coverage of about 10 A or less. A barrier layer with a thickness of about 10 A or less is believed to be a sufficient barrier layer to prevent copper diffusion. In one aspect, a thin barrier layer may be used to advantage in filling sub-micron and smaller features having high aspect ratios. Of course, a barrier layer having a sidewall coverage of greater than 50 A may be used.
The barrier layer may be further plasma annealed. In one embodiment, the barrier lay may be plasma annealed with an argon plasma or an argon/hydrogen plasma. The RF power supplied to an RF electrode may be between about 100 W and about 2000 W, preferably between about 500 W and about 1000 W for a 200 mm diameter substrate and preferably between about 1000 W and about 2000 W for a 300 mm diameter substrate. The pressure of the chamber may be less than 100 torr, preferably between 0.1 torr and about 5 torr, and more preferably between about 1 torr and 3 torr. The heater temperature may be between about 20°C and about 500°C. The plasma anneal may be performed after a cycle, a plurality of cycles, or after formation of the barrier layer.
Embodiments of atomic layer deposition of the barrier layer have been described above as chemisorption of a monolayer of reactants on a substrate. The present invention also includes embodiments in which the reactants are deposited to more or less than a monolayer. The present invention also includes embodiments in which the reactants are not deposited in a self-limiting manner. The present invention also includes embodiments in which the barrier layer 204 is deposited in mainly a chemical vapor deposition process in which the reactants are delivered sequentially or simultaneously. The present invention also include embodiments in which the barrier layer 204 is deposited in a physical vapor deposition process in which the target comprises the material to be deposited (i.e. a tantalum target in a nitrogen atmosphere for the deposition of tantalum nitride).
Process Chamber Adapted for Depositing a Seed Layer
In one embodiment, the seed layer may be deposited by any suitable technique such as physical vapor deposition, chemical vapor deposition, electroless deposition, or a combination of techniques. Suitable physical vapor deposition techniques for the deposition of the seed layer include techniques such as high density plasma physical vapor deposition (HDP PVD) or collimated or long throw sputtering. One type of HDP PVD is self-ionized plasma physical vapor deposition. An example of a chamber capable of self-ionized plasma physical vapor deposition of a seed layer is a SIPTM chamber, available from Applied Materials, Inc. of Santa Clara, California. Exemplary embodiments of chambers capable of self-ionized physical vapor deposition are described in U.S. Patent No. 6,183,614, entitled "Rotating Sputter Magnetron Assembly," which is herein incorporated by reference to the extent not inconsistent with the present invention.
Figure 4 is a schematic cross-sectional view of one embodiment of a process system 410 capable of physical vapor deposition which may be used to deposit a seed layer. Of course, other processing systems and other types of physical vapor deposition may also be used.
The process system 410 includes a vacuum chamber 412 sealed to a PVD target 414 composed of the material to be sputter deposited on a wafer 416 held on a heater pedestal 418. A shield 420 held within the chamber protects the walls of the chamber 412 from the sputtered material and provides the anode grounding plane. A selectable DC power supply 422 negatively biases the target 414 with respect to the shield 420.
A gas source 424 supplies a sputtering working gas, typically the chemically inactive gas argon, to the chamber 412 through a mass flow controller 426. A vacuum system 428 maintains the chamber at a low pressure. A computer-based controller 430 controls the reactor including the DC power supply 422 and the mass flow controllers 426.
When the argon is admitted into the chamber, the DC voltage between the target 414 and the shield 420 ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target 414. The ions strike the target 414 at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target 414. Some of the target particles strike the wafer 416 and are thereby deposited on it, thereby forming a film of the target material.
To provide efficient sputtering, a magnetron 432 is positioned in back of the target 414. It has opposed magnets 434, 436 creating a magnetic field within the chamber in the neighborhood of the magnets 434, 436. The magnetic field traps electrons and, for charge neutrality, the ion density also increases to form a high- density plasma region 438 within the chamber adjacent to the magnetron 432. The magnetron 432 usually rotates about a rotational axis 458 at the center of the target 414 to achieve full coverage in sputtering of the target 414.
The pedestal 418 develops a DC self-bias, which attracts ionized sputtered particles from the plasma across the plasma sheath adjacent to the wafer 416. The effect can be accentuated with additional DC or RF biasing of the pedestal electrode 418 to additionally accelerate the ionized particles extracted across the plasma sheath towards the wafer 416, thereby controlling the directionality of sputter deposition.
Seed Layer Formation
The exemplary chamber as described in Figure 4 may be used to implement the following process. Of course, other process chambers may be used. Figure 5A- 5C are schematic cross-sectional view of exemplary embodiments of depositing a seed layer over a barrier layer.
One embodiment, as shown in Figure 5A, comprises depositing a copper alloy seed layer 502 over a barrier layer 204 of Figure 2B and depositing a copper conductive material layer 506 over the copper alloy seed layer 502 to fill the feature. The term "copper conductive material layer" as used in the specification is defined as a layer comprising copper or a copper alloy. The copper alloy seed layer 502 comprises a copper metal alloy that aids in subsequent deposition of materials thereover. The copper alloy seed layer 502 may comprise copper and a second metal, such as aluminum, magnesium, titanium, zirconium, tin, other metals, and combinations thereof. The second metal preferably comprises aluminum, magnesium, titanium, and combinations thereof and more preferably comprises aluminum. In certain embodiments, the copper alloy seed layer comprises a second metal in a concentration having the lower limits of about 0.001 atomic percent, about 0.01 atomic percent, or about 0.1 atomic percent and having the upper limits of about 5.0 atomic percent, about 2.0 atomic percent, or about 1.0 atomic percent. The concentration of the second metal in a range from any lower limit to any upper limit is within the scope of the present invention. The concentration of the second metal in the copper alloy seed layer 502 is preferably less than about 5.0 atomic percent to lower the resistance of the copper alloy seed layer 502. The term "layer" as used in the specification is defined as one or more layers. For example, for a copper alloy seed layer 502 comprising copper and a second metal in a concentration in a range between about 0.001 atomic percent and about 5.0 atomic percent, the copper alloy seed layer 502 may comprise a plurality of layers in which the total composition of the layers comprises copper and the second metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent. For illustration, examples of a copper alloy seed layer 502 comprising a plurality of layers in which the total composition of the layers comprises copper and the second metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent may comprises a first seed layer comprising the second metal and a second seed layer comprising copper, may comprise a first seed layer comprising a copper/second metal alloy and a second seed layer comprising a copper/second metal alloy, or may comprise a first seed layer comprising a copper/second metal alloy and a second seed layer comprising copper, etc.
The copper alloy seed layer 502 is deposited to a thickness of at least about a 5 A coverage of the sidewalls of the feature or to a thickness of at least a continuous coverage of the sidewalls of the feature. In one embodiment, the copper alloy seed layer 502 is deposited to a thickness at the field areas between about 10 A and about 2000 A, preferably between about 500 A and about 1000 A for a copper alloy seed layer 502 deposited by physical vapor deposition.
Another embodiment, as shown in Figure 5B, comprises depositing a copper alloy seed layer 512 over a barrier layer 204 of Figure 2B, depositing a second seed layer 514 over the copper alloy seed layer 512, and depositing a copper conductive material layer 516 over the second seed layer 514 to fill the feature. The copper alloy seed layer 512 comprises a copper metal alloy that aids in subsequent deposition of materials thereover. The copper alloy seed layer 512 may comprise copper and a second metal, such as aluminum, magnesium, titanium, zirconium, tin, other metals, and combinations thereof. The second metal preferably comprises aluminum, magnesium, titanium, and combinations thereof and more preferably comprises aluminum. In certain embodiments, the copper alloy seed layer comprises a second metal in a concentration having the lower limits of about 0.001 atomic percent, about 0.01 atomic percent, or about 0.1 atomic percent and having the upper limits of about 5.0 atomic percent, about 2.0 atomic percent, or about 1.0 atomic percent. The concentration of the second metal in a range from any lower limit to any upper limit is within the scope of the present invention. In one embodiment, the second seed layer 514 comprises undoped copper (i.e. pure copper). In one aspect, a second seed layer 514 comprising undoped copper is used because of its lower electrical resistivity than a copper alloy seed layer 512 of the same thickness and because of its higher resistance to surface oxidation.
The copper alloy seed layer 512 may be deposited to a thickness of less than a monolayer (i.e. a sub-monolayer thickness or a discontinuous layer) over the sidewalls of the feature. In one embodiment, the combined thickness of the copper alloy seed layer 512 and the second seed layer 514 at the field areas is between about 10 A and about 2000 A, preferably between about 500 A and about 1000 A for a copper alloy seed layer 512 and second seed layer 514 deposited by physical vapor deposition.
Another embodiment, as shown in Figure 5C, comprises depositing a first seed layer 523 over a barrier layer 204 of Figure 2B, depositing a second seed layer 524 over the first seed layer 523, and depositing a copper conductive material layer 526 over the second seed layer 524 to fill the feature. The first seed layer 523 comprises a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. Preferably, the first seed layer 523 comprises aluminum. In one embodiment, the second seed layer 514 comprises undoped copper (i.e. pure copper).
The first seed layer 523 may be deposited to a thickness of less than a monolayer (i.e. a sub-monolayer thickness or a discontinuous layer) over the sidewalls of the feature. In one embodiment, the first seed layer is deposited to a thickness of less than about 50 A sidewall coverage, preferably less than about 40 A sidewall coverage, to lower the total resistance of the combined seed layer. The combined thickness of the first seed layer 523 and the second seed layer 524 at the field areas is between about 10 A and about 2000 A, preferably between about 500 A and about 1000 A for a first seed layer 523 and second seed layer 524 deposited by physical vapor deposition.
The copper alloy seed layer 502, 512, the first seed layer 523, or the second seed layer 514, 524 may be deposited by such techniques including physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless deposition, or a combination of techniques. In general, if a seed layer is deposited utilizing physical vapor deposition techniques, a chamber, such as the chamber 412 as described in Figure 4, includes a target, such as target 414, having a composition similar to the metal or metal alloy intended to be deposited. For example, to deposit a copper alloy seed layer 502, 512 the target may comprise copper and a second metal, such as aluminum, magnesium, titanium, zirconium, tin, other metals, and combinations thereof. The second metal preferably comprises aluminum. In certain embodiments, the target comprises a second metal in a concentration having the lower limits of about 0.001 atomic percent, about 0.01 atomic percent, or about 0.1 atomic percent and having the upper limits of about 5.0 atomic percent, about 2.0 atomic percent, or about 1.0 atomic percent. The concentration of the second metal in a range from any lower limit to any upper limit is within the scope of the present invention. In another example, to deposit a first seed layer 523, the target comprises a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. If a seed layer is deposited by chemical vapor deposition or atomic layer deposition, a chamber, such as the chamber as described in Figure 1 , is adapted to deliver suitable metal precursors of the metal or metal alloy to be deposited.
One exemplary process of depositing a seed layer by physical vapor deposition in a process chamber, such as the process chamber of Figure 4, comprises utilizing a target of the material to be deposited. The process chamber may be maintained at a pressure of between about 0.1 mtorr and about 10 mtorr. The target may be DC-biased at a power between about 5 kW and about 100 kW. The pedestal may be RF-biased at a power between about 0 and about 1000 W. The pedestal may be unheated (i.e. room temperature).
The copper conductive material layer 506, 516, 526 may be deposited by electroplating, physical vapor deposition, chemical vapor deposition, electroless deposition or a combination of techniques. Preferably, the copper conductive material layer 506, 516, 526 is deposited by electroplating because of the bottom-up growth which may be obtained in electroplating processes. An exemplary electroplating method is described in United States Patent No. 6,113,771, entitled "Electro Deposition Chemistry", issued September 5, 2000, and is incorporated herein by reference to the extent not inconsistent with this invention.
It has been observed that a copper alloy seed layer, such as a copper- aluminum seed layer, has improved adhesion over a barrier layer when compared to an undoped copper seed layer over the barrier layer. Because the copper alloy seed layer has good adhesion over a barrier layer, the copper alloy seed layer acts as a good wetting agent to materials deposited thereon. Not wishing to bound by theory, it is believed that the concentration of the copper and other metals of the copper seed layer provides a seed layer with good wetting properties and good electrical characteristics. It is further believed that a copper alloy seed layer having a total thickness of less than a monolayer may be used as long as a second seed layer, such as an undoped seed layer, is deposited thereover to provide at least a combined continuous seed layer since the copper alloy seed layer provides an improved interface for adhesion of materials thereon.
Similarly, it has been observed that a metal seed layer, such as an aluminum seed layer, has improved adhesion over a barrier layer when compared to an undoped copper seed layer over the barrier layer. Because the metal seed layer has good adhesion over a barrier layer, the metal seed layer acts as a good wetting agent to materials deposited thereon. Not wishing to bound by theory, it is believed that a metal seed layer, such as an aluminum seed layer, having a total thickness of less than a monolayer may be used since the metal layer provides an improved interface for adhesion of materials thereon, such as an undoped copper seed layer deposited over the metal layer.
The seed layers as disclosed herein have improved adhesion over barrier layers and have good wetting properties for materials deposited thereover, such as a copper conductive material layer deposited thereover. Therefore, the seed layers increase device reliability by reducing the likelihood of agglomeration, dewetting, or the formation of voids in the copper conductive material layer during deposition of the copper conductive material layer, during subsequent processing at high temperatures, and during thermal stressing of the devices during use of the devices.
In one aspect, the seed layers may be used with any barrier layer and may be used with barrier layers deposited by any deposition technique. The seed layers also may be deposited by any deposition technique. Furthermore, a conductive material layer, such as a copper conductive material layer, may be deposited over the seed layers by any deposition technique.
The present process may be used to advantage in filling apertures having less than about 0.2 micron opening width and having an aspect ratio of greater than about 4:1 , about 6:1; or about 10:1. The processes as disclosed herein may be carried out in separate chambers or may be carried out in a multi-chamber processing system having a plurality of chambers. Figure 6 is a schematic top-view diagram of one example of a multi- chamber processing system 600 which may be adapted to perform processes as disclosed herein. The apparatus is an ENDURATM system and is commercially available from Applied Materials, Inc., of Santa Clara, California. A similar multi- chamber processing system is disclosed in U.S. Patent No. 5,186,718, entitled "Stage Vacuum Wafer Processing System and Method," (Tepman et al.), issued on February 16, 1993, where is hereby incorporated by reference to the extent not inconsistent with the present disclosure. The particular embodiment of the system 600 is provided to illustrate the invention and should not be used to limit the scope of the invention.
The system 600 generally includes load lock chambers 602, 604 for the transfer of substrates into and out from the system 600. Typically, since the system 600 is under vacuum, the load lock chambers 602, 604 may "pump down" the substrates introduced into the system 600. A first robot 610 may transfer the substrates between the load lock chambers 602, 604, processing chambers 612, 614, transfer chambers 622, 624, and other chambers 616, 618. A second robot 630 may transfer the substrates between processing chambers 632, 634, 636, 638 and the transfer chambers 622, 624. Processing chambers 612, 614, 632, 634, 636, 638 may be removed from the system 600 if not necessary for the particular process to be performed by the system 600.
In one embodiment, the system 600 is configured so that processing chamber 634 is adapted to deposit a copper alloy seed layer 502. For example, the processing chamber 634 for depositing a copper alloy seed layer 502 may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber. The system 600 may be further configured so that processing chamber 632 is adapted to deposit a barrier layer 204 in which the copper alloy seed layer 502 is deposited over the barrier layer. For example, the processing chamber 632 for depositing the barrier layer 204 may be an atomic layer deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber. In one specific embodiment, the processing chamber 632 may be an atomic layer deposition chamber, such as the chamber shown in Figure 1 , and the processing chamber 634 may be a physical vapor deposition chamber, such as the chamber shown in Figure 4.
In another embodiment, the system 600 is configured so that processing chamber 634 is adapted to deposit a copper alloy seed layer 512 and so that processing chamber 636 is adapted to deposit a second seed layer 514 over the copper alloy seed layer 512. For example, the processing chamber 634 for depositing a copper alloy seed layer 512 and/or the processing chamber 636 for depositing a second seed layer may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber. The system 600 may be further configured so that processing chamber 632 is adapted to deposit a barrier layer 204 in which the copper alloy seed layer 512 is deposited over the barrier layer. For example, the processing chamber 632 for depositing the barrier layer 204 may be an atomic layer deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber. In one specific embodiment, processing chamber 632 may be an atomic layer deposition chamber, such as the chamber shown in Figure 1, and processing chambers 634, 636 may be physical vapor deposition chambers, such as the chamber shown in Figure 4.
In another embodiment, the system 600 is configured so that processing chamber 634 is adapted to deposit a metal seed layer 523 and so that processing chamber 636 is adapted to deposit a second seed layer 524 over the metal seed layer 523. For example, the processing chamber 634 for depositing a metal seed layer 523 and/or the processing chamber 636 for depositing a second seed layer 524 may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or an atomic layer deposition chamber. The system may be further configured so that processing chamber 632 is adapted to deposit a barrier layer 204 in which the metal seed layer 523 is deposited over the barrier layer. For example, the processing chamber 632 for depositing the barrier layer 204 may be an atomic layer deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber. In one specific embodiment, processing chamber 632 may be an atomic layer deposition chamber, such as the chamber shown in Figure 1 , and processing chambers 634, 636 may be physical vapor deposition chambers, such as the chamber shown in Figure 4.
In one aspect, deposition of a barrier layer 204 and a seed layer (such as a copper alloy seed layer 502, a copper alloy seed layer 512 and a second seed layer 514, or a metal seed layer 523 and a second seed layer 524) may be performed in a multi-chamber processing system under vacuum to prevent air and other impurities from being incorporated into the layers and to maintain the seed structure over the barrier layer 204.
Other embodiments of the system 600 are within the scope of the present invention. For example, the position of a particular processing chamber on the system may be altered. In another example, a single processing chamber may be adapted to deposit two different layers.
EXAMPLES Example 1
A TaN layer was deposited over a substrate by atomic layer deposition to a thickness of about 20 A. A seed layer was deposited over the TaN layer by physical vapor deposition to a thickness of about 100 A. The seed layer comprised either 1) undoped copper deposited utilizing a target comprising undoped copper, 2) a copper alloy comprising aluminum in a concentration of about 2.0 atomic percent deposited utilizing a copper-aluminum target comprising aluminum in a concentration of about 2.0 atomic percent, 3) a copper alloy comprising tin in a concentration of about 2.0 atomic percent deposited utilizing a copper-tin target comprising tin in a concentration of about 2.0 atomic percent, or 4) a copper alloy comprising zirconium in a concentration of about 2.0 atomic percent deposited utilizing a copper-zirconium target comprising zirconium in a concentration of about 2.0 atomic percent. The resulting substrate was annealed at a temperature of about 380°C for a time period of about 15 minutes in a nitrogen (N2) and hydrogen (H2) ambient.
Scanning electron microscope photographs showed agglomeration of the undoped copper layer after the anneal. The copper-zirconium alloy showed less agglomeration than the undoped copper layer. The copper-tin alloy showed less agglomeration than the copper-zirconium alloy. The copper-aluminum alloy showed no significant agglomeration.
Example 2
Copper-aluminum alloy films comprising about 2.0 atomic percent of aluminum were deposited on different substrates by physical vapor deposition utilizing a copper-aluminum target comprising aluminum in a concentration of 2.0 atomic percent. The resulting substrates included 1 ) a copper-aluminum layer deposited to a thickness of about 50 A over an ALD TaN layer, 2) a copper-aluminum layer deposited to a thickness of about 50 A over about a 100 A Ta layer, 3) a copper- aluminum layer deposited to a thickness of about 100 A over an ALD TaN layer, 4) a copper-aluminum layer deposited to a thickness of about 100 A over a silicon nitride (SiN) layer, and 5) a copper-aluminum layer deposited to a thickness of about 100 A over a silicon oxide layer. The resulting substrates were annealed at a temperature of about 380°C for a time period of about 15 minutes in a nitrogen (N2) and hydrogen (H2) ambient. Scanning electron microscope photographs showed that there was no significant agglomeration of the copper-aluminum alloy over the various substrates.
Example 3
Copper-aluminum alloy films comprising about 2.0 atomic percent of aluminum were deposited by physical vapor deposition utilizing a copper-aluminum target comprising aluminum in a concentration of 2.0 atomic percent to either a 50 A or 100 A thickness over an ALD TaN layer. The resulting substrates were annealed at a temperature of about 380°C, about 450°C, or about 500°C for a time period of about 15 minutes in a nitrogen (N2) and hydrogen (H2) ambient. Scanning electron microscope photographs showed that there was no significant agglomeration of the copper-aluminum alloy for substrates annealed at temperatures of about 380°C or about 450°C. The copper-aluminum alloy showed some dewetting began to occur for substrates annealed at a temperature of about 500°C. Example 4
Copper-aluminum alloy films comprising about 2.0 atomic percent of aluminum were deposited by physical vapor deposition utilizing a copper-aluminum target comprising aluminum in a concentration of about 2.0 atomic percent to either about a 50 A or about a 100 A thickness over an ALD TaN layer. The resulting substrates were annealed at a temperature of about 450°C for a time period of about 30 minutes in a nitrogen (N2) and hydrogen (H2) ambient. Scanning electron microscope photographs showed that there was no significant agglomeration of the copper- aluminum alloy for substrates annealed at a temperature of about 450°C for a time period of about 30 minutes.
While foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1. A method of filling a feature, comprising: depositing a barrier layer; depositing a seed layer over the barrier layer, the seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and depositing a copper conductive material layer over the seed layer.
2. A method of depositing a seed layer over a barrier layer for subsequent deposition of a conductive material layer over the seed layer, comprising: depositing a copper alloy seed layer over the barrier layer, the copper alloy seed layer comprising copper and a metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent, the metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
3. A method of depositing a seed layer over a barrier layer for subsequent deposition of a conductive material layer over the seed layer, comprising: depositing a copper alloy seed layer over the barrier layer, the copper alloy seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and depositing a second seed layer over the copper alloy seed layer.
4. The method of claim 3, wherein the copper alloy seed layer comprises the metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent.
5. The method of claim 2 or 3, wherein the copper alloy seed layer comprises the metal in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
6. The method of claim 2 or 3, wherein the copper alloy seed layer comprises the metal in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
7. A method of depositing a seed layer over a barrier layer for subsequent deposition of a conductive material layer over the seed layer, comprising: depositing a first seed layer over the barrier layer, the first seed layer comprising a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and depositing a second seed layer over the first seed layer.
8. The method of claim 7, wherein the first seed layer is deposited to a sidewall coverage between a sub-monolayer and about 50 A.
9. The method of claim 7, wherein the first seed layer is deposited to a sidewall coverage between a sub-monolayer and about 40 A.
10. The method of claim 3 or 7, wherein the copper conductive material layer is deposited over the second seed layer.
11. A method of preparing a substrate structure for copper metallization, comprising: depositing a barrier layer to a sidewall coverage of about 50 A or less; and depositing a seed layer over the barrier layer, the seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
12. The method of claim 11 , wherein the barrier layer is deposited to a sidewall coverage of about 20 A or less.
13. The method of claim 11 , wherein the barrier layer is deposited to a sidewall of about 10 A or less.
14. The method of claim 1 or 11 , wherein the seed layer comprises a copper alloy seed layer of the copper and the metal.
15. A method of filling a feature, comprising: depositing a barrier layer; depositing a copper alloy seed layer over the barrier layer, the copper alloy seed layer comprising copper and a metal in a concentration between about 0.01 atomic percent and 5.0 atomic percent, the metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and depositing a copper conductive material layer over the copper alloy seed layer.
16. The method of claim 1 , 11 , or 15, wherein the barrier layer is deposited by a technique selected from the group consisting of atomic layer deposition, chemical vapor deposition, physical vapor deposition, and combinations thereof.
17. A method of filling a feature, comprising: depositing a barrier layer by atomic layer deposition; depositing a copper alloy seed layer over the barrier layer, the copper alloy seed layer comprising copper and a metal in a concentration between about 0.01 atomic percent and 5.0 atomic percent, the metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; depositing a second seed layer over the copper alloy seed layer; and depositing a copper conductive material layer over the second seed layer.
18. The method of claim 2, 3, 15, or 17, wherein the copper alloy seed layer is deposited by a technique selected from the group consisting of physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless deposition, and combinations thereof.
19. A method of filling a feature, comprising: depositing a barrier layer by atomic layer deposition; depositing a first seed layer over the barrier layer to a sidewall coverage between a sub-monolayer and about 50 A, the first seed layer comprising aluminum; depositing a second seed layer over the first seed layer; and depositing a conductive material layer over the second seed layer.
20. The method of claim 7 or 19, wherein the first seed layer is deposited by a technique selected from the group consisting of physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless deposition, and combinations thereof.
21. The method of claim 3, 7, 17, or 19, wherein the second seed layer is deposited by a technique selected from the group consisting of physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless deposition, and combinations thereof.
22. The method of claim 1 , 15, 17, or 19, wherein the copper conductive material layer is deposited by a technique selected from the group consisting of electroplating, electroless deposition, chemical vapor deposition, physical vapor deposition, and combinations thereof.
23. A method of preparing a substrate structure for electroplating of copper, comprising: depositing a barrier layer by atomic layer deposition; and depositing a seed layer over the barrier layer, the seed layer comprising copper and aluminum.
24. The method of claim 23, wherein the seed layer comprises a copper alloy seed layer of the copper and the aluminum, the aluminum present in the copper alloy seed layer in a concentration between about 0.001 atomic percent and about 5.0 atomic percent.
25. The method of claim 1 , 11 , 23, wherein the seed layer comprises a first seed layer deposited over the barrier layer and a second seed layer deposited over the first seed layer.
26. The method of claim 25, wherein the first seed layer comprises a copper alloy seed layer of the copper and the aluminum, the aluminum present in the copper alloy seed layer in a concentration between about 0.001 atomic percent and about 5.0 atomic percent and wherein the second seed layer comprises undoped copper.
27. The method of claim 24, wherein the copper alloy seed layer comprises the aluminum in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
28. The method of claim 26, wherein the copper alloy seed layer comprises the aluminum in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
29. The method of claim 24, wherein the copper alloy seed layer comprises the aluminum in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
30. The method of claim 26, wherein the copper alloy seed layer comprises the aluminum in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
31. The method of claim 25, wherein the first seed layer comprises aluminum to a sidewall coverage between a sub-monolayer and about 50 A and wherein the second seed layer comprises undoped copper.
32. The method of claim 1 , 11 , 15, 17, 19, or 23 wherein the barrier layer comprises a material selected from the group consisting of titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, and combinations thereof.
33. The method of claim 1 or 11 , wherein the seed layer is deposited by a technique selected from the group consisting of physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroless deposition, and combinations thereof.
34. The method of claim 25, wherein the first seed layer comprises a copper alloy seed layer of the copper and the metal.
35. The method of claim 25, wherein the first seed layer comprises the metal.
36. The method of claim 3, 7, or 17, wherein the second seed layer comprises undoped copper.
37. The method of claim 34, wherein the second seed layer comprises undoped copper.
38. The method of claim 35, wherein the second seed layer comprises undoped copper.
39. A target for physical vapor deposition of a seed layer, comprising: copper; and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof, wherein the metal is present in the target in a concentration between about 0.001 atomic percent and about 5.0 atomic percent.
40. The target of claim 39, wherein the metal is present in the target in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
41. The target of claim 39, wherein the metal is present in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
42. A chamber adapted to deposit a seed layer, comprising: a target comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof, wherein the metal is present in the target in a concentration between about 0.001 atomic percent and about 5.0 atomic percent.
43. The chamber of claim 42, wherein the metal is present in the target in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
44. The chamber of claim 42, wherein the metal is present in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
45. A system for processing a substrate, comprising: a first chamber for depositing a copper alloy seed layer, wherein the copper alloy seed layer comprises copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof and wherein the metal is present in the copper alloy in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
46. The system of claim 45, further comprising a second chamber for depositing a barrier layer, wherein the copper alloy seed layer is deposited over the barrier layer.
47. The system of claim 46, wherein the second chamber is selected from the group consisting of an atomic layer depositing chamber, a chemical vapor deposition chamber, and a physical vapor deposition chamber.
48. The system of claim 46, wherein the first chamber is a physical vapor deposition chamber and the second chamber is an atomic layer deposition chamber.
49. The system of claim 46, further comprising a transfer chamber in communication with the first chamber and the second chamber.
50. The system of claim 46, wherein at least two of the chambers are a single chamber.
51. A system for processing a substrate, comprising: a first chamber for depositing a copper alloy seed layer, wherein the copper alloy seed layer comprises copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof, and a second chamber for depositing an undoped copper seed layer over the copper alloy seed layer.
52. The system of claim 51 , further comprising a third chamber for depositing a barrier layer, wherein the copper alloy seed layer is deposited over the barrier layer.
53. A system for processing a substrate, comprising: a first chamber for depositing a metal seed layer, wherein the metal seed layer comprises a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof, and a second chamber for depositing an undoped copper seed layer over the metal seed layer.
54. The system of claim 53, further comprising a third chamber for depositing a barrier layer, wherein the metal seed layer is deposited over the barrier layer.
55. The system of claim 45, 51 , or 53, wherein the first chamber is selected from the group consisting of a physical vapor deposition chamber, a chemical vapor deposition chamber, an atomic layer deposition chamber, and an electroless deposition chamber.
56. The system of claim 51 or 53, wherein the second chamber is selected from the group consisting of a physical vapor deposition chamber, a chemical vapor deposition chamber, an atomic layer deposition chamber, and an electroless deposition chamber.
57. The system of claim 52 or 54, wherein the third chamber is selected from the group consisting of an atomic layer depositing chamber, a chemical vapor deposition chamber, and a physical vapor deposition chamber.
58. The system of claim 52 or 54, wherein the first chamber is a physical vapor deposition chamber, the second chamber is a physical vapor deposition chamber, and the third chamber is an atomic layer deposition chamber.
59. The system of claim 52 or 54, further comprising a transfer chamber in communication with the first chamber, the second chamber, and the third chamber.
60. The system of claim 52 or 54, wherein at least two of the chambers are a single chamber.
61. A structure, comprising: a substrate having a dielectric layer formed thereon, the dielectric layer having an aperture formed therein to a top surface of the substrate; at least one barrier layer formed over the dielectric layer; a copper alloy seed layer formed over the at least one barrier layer, the copper alloy seed layer comprising copper and a metal in a concentration of between about 0.001 atomic percent and about 5.0 atomic percent, the metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and a copper conductive material layer formed over the copper alloy seed layer.
62. The structure of claim 61 , wherein the copper alloy seed layer comprises the metal in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
63. The structure of claim 61 , wherein the copper alloy seed layer comprises the metal in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
64. A structure, comprising: a substrate having a dielectric layer formed thereon, the dielectric layer having an aperture formed therein to a top surface of the substrate; at least one barrier layer formed over the dielectric layer; a copper alloy seed layer formed over the at least one barrier layer, the copper alloy seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; a second seed layer formed over the copper alloy seed layer; and a copper conductive material layer formed over the second seed layer.
65. The structure of claim 64, wherein the second seed layer comprises undoped copper.
66. The structure of claim 64, wherein the copper alloy seed layer comprises the metal in a concentration between about 0.001 atomic percent and about 5.0 atomic percent.
67. The structure of claim 64, wherein the copper alloy seed layer comprises the metal in a concentration between about 0.01 atomic percent and about 2.0 atomic percent.
68. The structure of claim 64, wherein the copper alloy seed layer comprises the metal in a concentration between about 0.1 atomic percent and about 1.0 atomic percent.
69. A structure, comprising: a substrate having a dielectric layer formed thereon, the dielectric layer having an aperture formed therein to a top surface of the substrate; at least one barrier layer formed over the dielectric layer; a first seed layer formed over the at least one barrier layer, the first seed layer comprising a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; a second seed layer formed over the first seed layer; and a copper conductive material layer formed over the second seed layer.
70. The structure of claim 69, wherein the second seed layer comprises undoped copper.
71. The structure of claim 69, wherein the first seed layer has a sidewall coverage between a sub-monolayer and about 50 A.
72. The structure of claim 69, wherein the first seed layer has a sidewall coverage between a sub-monolayer and about 40 A.
73. The structure of claim 61 , 64, or 69, wherein the barrier layer comprises a material selected from the group consisting of titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, and combinations thereof.
74. The structure of claim 61 , 64, or 69, wherein the barrier layer has a sidewall coverage of about 50 A or less.
75. The structure of claim 61 , 64, or 69, wherein the barrier layer has a sidewall coverage of about 20 A or less.
76. The structure of claim 61 , 64, or 69, wherein the barrier layer has a sidewall coverage of about 10 A or less.
EP02757668A 2001-09-26 2002-09-09 Integration of barrier layer and seed layer Withdrawn EP1433202A2 (en)

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US09/965,370 US20030059538A1 (en) 2001-09-26 2001-09-26 Integration of barrier layer and seed layer
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