JP5380838B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5380838B2 JP5380838B2 JP2007522218A JP2007522218A JP5380838B2 JP 5380838 B2 JP5380838 B2 JP 5380838B2 JP 2007522218 A JP2007522218 A JP 2007522218A JP 2007522218 A JP2007522218 A JP 2007522218A JP 5380838 B2 JP5380838 B2 JP 5380838B2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Description
前記(c)工程で形成する銅又は銅合金膜は、室温から400℃の範囲で酸化反応の標準生成エネルギーの絶対値が前記バリアメタル膜のそれよりも大きい添加元素を固溶させた銅合金膜をシードとした銅メッキ膜であり、前記添加元素の酸化反応の標準生成エネルギーの絶対値は、前記バリアメタル膜のそれよりも大きく、且つ、前記(d)工程において形成する酸素吸収膜を構成する金属のそれ以下であることを特徴とする。
2;層間絶縁膜
3a・3b;エッチストップ膜
4a・4b・4c;バリアメタル膜
5a・5b;銅又は銅合金配線
5c;銅又は銅合金ビア
6a・6b;配線保護膜
7;ビア層間絶縁膜
9;ビア層ハードマスク
10a・10b;配線層間絶縁膜
11a・11b;配線溝
11c;ビアホール
12;銅又は銅合金シード膜
13;銅メッキ膜
14;酸素吸収膜
15a・15b・15c;低酸素濃度銅膜
16a・16b・16c;側壁保護膜
17a・17b;配線層ハードマスク
本発明の第1の実施形態の配線構造について図3を用いて説明する。本発明の第1の実施形態は、本発明をデュアルダマシン配線に適用した形態である。
本発明の第2の実施形態の配線構造について図5を参照して説明する。本発明の第2の実施形態は、本発明をシングルダマシン配線に適用した形態である。
Claims (2)
- (a)半導体基板上方に形成された絶縁膜中の所定の領域に、配線を形成するための溝及び/又はビアを形成する工程と、(b)前記溝及び/又はビアが形成された前記絶縁膜上にバリアメタル膜を形成する工程と、(c)前記バリアメタル膜上に銅又は銅合金膜を形成する工程と、(d)前記銅又は銅合金膜上に、室温から400℃の範囲で酸化反応の標準生成エネルギーが負であり且つ前記(b)工程で形成されたバリアメタル膜よりも前記標準生成エネルギーの絶対値が大きい酸素吸収膜を形成する工程と、(e)前記バリアメタル膜、前記銅又は銅合金膜及び前記酸素吸収膜からなる積層膜を200乃至400℃の範囲の温度で加熱する工程と、(f)前記積層膜の上部を除去して、配線を形成する工程と、を有し、
前記(c)工程で形成する銅又は銅合金膜は、室温から400℃の範囲で酸化反応の標準生成エネルギーの絶対値が前記バリアメタル膜のそれよりも大きい添加元素を固溶させた銅合金膜をシードとした銅メッキ膜であり、前記添加元素の酸化反応の標準生成エネルギーの絶対値は、前記バリアメタル膜のそれよりも大きく、且つ、前記(d)工程において形成する酸素吸収膜を構成する金属のそれ以下であることを特徴とする半導体装置の製造方法。 - 前記シードの前記銅合金膜中の前記添加元素がAl,Mnから選択された一つであり、前記添加元素がAlの場合には、前記酸素吸収膜がAl,Mg,Ca,Zr,Be,Hfから選択された一つであり、前記添加元素がMnの場合には、前記酸素吸収膜がAl,Ti,Mg,Ca,Zr,Be、Hfから選択された一つであることを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (1)
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JP2007522218A JP5380838B2 (ja) | 2005-06-22 | 2006-05-23 | 半導体装置の製造方法 |
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JP2005182645 | 2005-06-22 | ||
JP2005182645 | 2005-06-22 | ||
JP2007522218A JP5380838B2 (ja) | 2005-06-22 | 2006-05-23 | 半導体装置の製造方法 |
PCT/JP2006/310253 WO2006137237A1 (ja) | 2005-06-22 | 2006-05-23 | 半導体装置及びその製造方法 |
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JPWO2006137237A1 JPWO2006137237A1 (ja) | 2009-01-08 |
JP5380838B2 true JP5380838B2 (ja) | 2014-01-08 |
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US (2) | US7867906B2 (ja) |
JP (1) | JP5380838B2 (ja) |
WO (1) | WO2006137237A1 (ja) |
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JP5309722B2 (ja) * | 2007-11-14 | 2013-10-09 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
JP5135002B2 (ja) | 2008-02-28 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5501586B2 (ja) * | 2008-08-22 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2010087094A (ja) * | 2008-09-30 | 2010-04-15 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US8049305B1 (en) * | 2008-10-16 | 2011-11-01 | Intermolecular, Inc. | Stress-engineered resistance-change memory device |
JP5560696B2 (ja) * | 2009-12-21 | 2014-07-30 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US9209134B2 (en) * | 2013-03-14 | 2015-12-08 | Intermolecular, Inc. | Method to increase interconnect reliability |
US20140339661A1 (en) * | 2013-05-20 | 2014-11-20 | T3Memory, Inc. | Method to make mram using oxygen ion implantation |
KR102275705B1 (ko) * | 2014-07-11 | 2021-07-09 | 삼성전자주식회사 | 웨이퍼 대 웨이퍼 접합 구조 |
JP6527420B2 (ja) * | 2015-07-31 | 2019-06-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
FR3057705B1 (fr) * | 2016-10-13 | 2019-04-12 | Soitec | Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant |
CN109037445A (zh) * | 2018-08-01 | 2018-12-18 | 德淮半导体有限公司 | Mim电容器及其制造方法 |
CN109148363A (zh) * | 2018-09-12 | 2019-01-04 | 德淮半导体有限公司 | 半导体制备方法 |
US11177170B2 (en) * | 2020-01-16 | 2021-11-16 | International Business Machines Corporation | Removal of barrier and liner layers from a bottom of a via |
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- 2006-05-23 WO PCT/JP2006/310253 patent/WO2006137237A1/ja active Application Filing
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JP2004031847A (ja) * | 2002-06-28 | 2004-01-29 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2004146519A (ja) * | 2002-10-23 | 2004-05-20 | Nec Yamagata Ltd | 半導体装置の製造方法 |
WO2004053971A1 (ja) * | 2002-12-09 | 2004-06-24 | Nec Corporation | 配線用銅合金、半導体装置、配線の形成方法及び半導体装置の製造方法 |
WO2004061931A1 (ja) * | 2002-12-26 | 2004-07-22 | Fujitsu Limited | 多層配線構造を有する半導体装置およびその製造方法 |
JP2004235415A (ja) * | 2003-01-30 | 2004-08-19 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2005039142A (ja) * | 2003-07-18 | 2005-02-10 | Nec Electronics Corp | 半導体装置の製造方法 |
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US20100193953A1 (en) | 2010-08-05 |
JPWO2006137237A1 (ja) | 2009-01-08 |
WO2006137237A1 (ja) | 2006-12-28 |
US20110068472A1 (en) | 2011-03-24 |
US8174122B2 (en) | 2012-05-08 |
US7867906B2 (en) | 2011-01-11 |
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