JP4876067B2 - 採取薄膜の品質改善処理方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- Microelectronics & Electronic Packaging (AREA)
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Description
(a)所定の深さでドナー基板において脆化ゾーンを形成するために、核種を注入するステップと、
(b)受容基板にドナー基板を接着するステップと、
(c)脆化ゾーンでドナー基板から採取層を分離するために、エネルギーを供給するステップと、
(d)採取層を処理するステップとを含むものである。
のような、絶縁体の上に半導体がある構造を形成することができる。
(a)第二層の下に脆化ゾーンを形成するために、核種を注入するステップと、
(b)受容基板にドナー基板を接着するステップと、
(c)脆化ゾーンでドナー基板から採取層を分離するために、エネルギーを供給するステップと、
(d)第二層に対して第一層の残部を選択エッチングするステップとを含み、
ステップ(a)で実施する注入のパラメータが、ステップ(c)の実施直後に出現する粗さが最小になるように調整され、約800℃未満の温度で実施される接着を強化するのに適したステップをさらに含むことを特徴とする。
‐注入時(図3b参照)および結束解除時(図3d参照)の損傷部分の結晶品質の改善;
‐特に、高い頻度の粗さ(HF粗さ)について滑らかな面;
‐約0.8J/m2超の接着エネルギー(プラズマ活性化なし)。
‐特に、ヘリウムのピークが水素拡散ゾーンより深く、また、ヘリウムのピークが脆化ゾーンより深くなるように、ヘリウムと水素の濃度ピークをずらすために適合される注入パラメータによる、SiGe層への典型的にはヘリウムと水素の共注入の実施、および、
‐30分〜4時間(例えば、約1時間)保持できる約600℃(+/−25℃)の温度での後分離修復熱処理の実施。
H:30kev−1×1016/cm2
He:52または60keV−1.0×1016/cm2
H:30keV−1×1016/cm2
He:48,52,56または60keV−1×1016/cm2
2 第二層
3 第三層
4 脆化ゾーン
5 SiO2層
6 接着界面
10 ドナー基板
20 受容基板
30 構造
Claims (20)
- 半導体材料から選択される第一の材料でできた第一層(1)と半導体材料から選択される第二の材料でできた第一層(1)の上にある第二層(2)とを含むドナー基板(10)から、第二層(2)を採取する方法であり、該方法は以下の:
(a)前記第二層(2)の下の前記ドナー基板に脆化ゾーン(4)を形成するために、前記ドナー基板に核種を注入するステップと、
(b)受容基板(20)にドナー基板(10)を接着するステップと、
(c)第二層と第一層の少なくとも一部を含むドナー基板の少なくとも一部が受容基板に転送され、脆化ゾーン(4)でドナー基板(10)を分離するために、炉において受容基板に接着されたドナー基板に熱処理を実施するステップと、
(d)第二層(2)に対して第一層の少なくとも一部(1’)を選択エッチングするステップとを含み、
ステップ(a)で注入する核種は二つの異なる原子を含み、
同じ炉内でステップ(c)から続けて350℃から800℃の間に含まれる温度で30分から4時間行なわれる熱処理を含む接着強化に適したステップをさらに含むことを特徴とするものである。 - ステップ(b)の前に実施される、ドナー基板または受容基板の片面または両面のプラズマ活性化をさらに含むことを特徴とする、請求項1に記載の方法。
- 熱処理は550℃〜800℃の間に含まれる温度で行われることを特徴とする、請求項1に記載の方法。
- 熱処理にはステップ(c)の分離温度から熱処理のために選択される温度までの単純温度変化が含まれることを特徴とする、請求項1に記載の方法。
- ステップ(c)は30分〜2時間に及ぶ期間の間、500℃で実施されることを特徴とする、請求項4に記載の方法。
- 接着強化に適したステップは、ステップ(d)の前に接着エネルギーが0.8J/m2以上になるように実施されることを特徴とする、請求項1に記載の方法。
- ステップ(c)の実施直後に出現する前記粗さは、表面10×10μm2で測定される40ÅRMS未満であることを特徴とする、請求項1に記載の方法。
- ステップ(a)の間に注入する核種は、ヘリウムと水素を含むことを特徴とする、請求項1に記載の方法。
- ドナー基板はSiGe層を具備し、前記ステップ(a)は、前記SiGe層に、ドナー基板の厚さのうち、水素拡散ゾーンより深く、またピークが脆化ゾーンより深い位置にくるヘリウム濃度で、脆化ゾーンを形成するように実施されることを特徴とする、請求項8に記載の方法。
- 熱処理は575℃〜625℃の間に含まれる温度で実施されることを特徴とする、請求項9に記載の方法。
- ヘリウムと水素の量はそれぞれ0.9×1016/cm2 、1.0×1016/cm2になるように選択されることを特徴とする、請求項9または請求項10に記載の方法。
- ステップ(c)の後、機械研磨手段を実施しないことを特徴とする、請求項1に記載の方法。
- ステップ(d)の後、第二層を厚くするために、第二層(2)上の第二の材料の結晶を成長させることをさらに含んでいることを特徴とする、請求項1に記載の方法。
- 第一層(1)は0<x≦1のSi1-xGexでできており、第二層(2)は歪みSiでできていることを特徴とする、請求項1に記載の方法。
- ドナー基板(10)はバルクSi支持基板、SiGeでできた緩衝構造、Si1-xGex(x≠0)を含む第一層(1)および歪みSiでできた第二層(2)を具備することを特徴とする、請求項1に記載の方法。
- 第一層(1)は歪みSiでできており、第二層(2)は0<x≦1のSi1-xGexでできており、ドナー基板(10)はさらに第一層(1)の下にSi1-xGexでできた第三層(3)を具備することを特徴とする、請求項1に記載の方法。
- ステップ(a)の注入は第一層(1)の下でも実施されるものであり、方法はさらに、ステップ(c)とステップ(d)との間に、第一層(1)に対して第三層(3)の残部を選択エッチングすることを含むことを特徴とする、請求項16に記載の方法。
- ドナー基板(10)はバルクSi支持基板、SiGeでできた緩衝構造および同じドナー基板(10)から複数の採取ができるように、交互に、x≠0であるSi1-xGe x でできた第一層(1A、1B、1C、1D、1E)と、歪みSiでできた第二層(2A、2B、2C、2D、2E)とを含む多層構造とを具備することを特徴とする、請求項1に記載の方法。
- ステップ(a)の前に、450℃〜650℃の間に含まれる温度で歪んだ層を形成することをさらに含み、この歪んだ層を形成するステップとステップ(c)で得られる取り外しとの間で行われる処理は、前記450℃〜650℃の間に含まれる温度以下で実施されることを特徴とする、請求項14〜18のいずれか一つに記載の方法。
- ステップ(b)の前に、ドナー基板(10)および/または受容基板(20)へ接着層を形成するステップであって、接着層は電気的絶縁材を含む、形成ステップをさらに含むことを特徴とする、請求項1に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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FR0402340A FR2867307B1 (fr) | 2004-03-05 | 2004-03-05 | Traitement thermique apres detachement smart-cut |
FR0402340 | 2004-03-05 | ||
FR0409980A FR2867310B1 (fr) | 2004-03-05 | 2004-09-21 | Technique d'amelioration de la qualite d'une couche mince prelevee |
FR0409980 | 2004-09-21 | ||
PCT/FR2005/000542 WO2005086227A1 (fr) | 2004-03-05 | 2005-03-07 | Technique d’amelioration de la qualite d’une couche mince prelevee |
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US (2) | US7276428B2 (ja) |
EP (2) | EP1733423A1 (ja) |
JP (2) | JP2007526644A (ja) |
KR (1) | KR100860271B1 (ja) |
FR (1) | FR2867310B1 (ja) |
WO (2) | WO2005086226A1 (ja) |
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US6717213B2 (en) * | 2001-06-29 | 2004-04-06 | Intel Corporation | Creation of high mobility channels in thin-body SOI devices |
FR2837981B1 (fr) * | 2002-03-28 | 2005-01-07 | Commissariat Energie Atomique | Procede de manipulation de couches semiconductrices pour leur amincissement |
US20090325362A1 (en) * | 2003-01-07 | 2009-12-31 | Nabil Chhaimi | Method of recycling an epitaxied donor wafer |
FR2892228B1 (fr) * | 2005-10-18 | 2008-01-25 | Soitec Silicon On Insulator | Procede de recyclage d'une plaquette donneuse epitaxiee |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
FR2858461B1 (fr) * | 2003-07-30 | 2005-11-04 | Soitec Silicon On Insulator | Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques |
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Publication number | Publication date |
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US7276428B2 (en) | 2007-10-02 |
WO2005086227A8 (fr) | 2006-10-19 |
EP1733423A1 (fr) | 2006-12-20 |
US20050196937A1 (en) | 2005-09-08 |
US7449394B2 (en) | 2008-11-11 |
JP2007526645A (ja) | 2007-09-13 |
WO2005086227A1 (fr) | 2005-09-15 |
FR2867310A1 (fr) | 2005-09-09 |
WO2005086226A8 (fr) | 2006-10-26 |
US20050245049A1 (en) | 2005-11-03 |
WO2005086226A1 (fr) | 2005-09-15 |
EP1721333A1 (fr) | 2006-11-15 |
FR2867310B1 (fr) | 2006-05-26 |
KR20070085086A (ko) | 2007-08-27 |
KR100860271B1 (ko) | 2008-09-25 |
JP2007526644A (ja) | 2007-09-13 |
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